JP2008130605A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To always establish optimal output resistance in self-cascode method. <P>SOLUTION: Two nMISFETs (MN1 and MN2) with the same polarity wherein sources or drains are connected in series with each other are provided on a semiconductor substrate. The gates of MN1 and MN2 are connected to the same gate terminal VG. DC gate bias voltage and AC signal voltage are applied to the gate terminal VG. Higher potential is applied to the drain of MN2 than that of MN1. DC substrate bias voltage VSUB applied to the MN2 substrate is higher than ground voltage applied to MN1 substrate. The DC substrate bias voltage VSUB of MN2 varies according to the condition of a circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a logic element having an analog transistor as a component is formed.

  In semiconductor devices, MISFETs (Metal Insulator Semiconductor Field Effect Transistors), which are transistors for analog applications, generally become increasingly smaller as the channel length (and gate length) becomes smaller as the channel length (and gate length) decreases. The short channel effect of coming is remarkable. In a long channel MISFET, ideally, the threshold voltage does not depend on the drain voltage, but in the short channel, DIBL (Drain Induced Barrier Lowering) occurs in which the threshold voltage decreases as the drain voltage increases. This DIBL reduces the differential output resistance ro of the MISFET. The gain in the AC (alternating current) operation of the MISFET is given by the equation “gm × ro” where the transconductance of the MISFET is gm. Therefore, even if gm increases due to miniaturization, the gain becomes smaller as a result. There is a characteristic that becomes smaller. DIBL occurs when a high electric field is applied near the drain in the channel of the MISFET.

  FIG. 13 is a cross-sectional view schematically showing a MISFET. In the state where the MISFET is operating in the saturation region, the channel resistance is high in the vicinity of the drain, so that a higher lateral electric field is applied than in other regions. Due to this high electric field, the drain voltage dependency on the channel resistance in the vicinity of the drain increases, which is the cause of DIBL. In order to suppress DIBL, it is effective to form an asymmetric channel having a low threshold value near the drain as shown in FIG. By forming an asymmetric channel, the resistance of the channel in the vicinity of the drain is lowered, and the lateral electric field in this region is reduced. As a result, the drain voltage dependency on the channel resistance in the vicinity of the drain is reduced, so that DIBL is suppressed. For this reason, since the differential output resistance ro becomes large, it is known that a high gain can be obtained (see Non-Patent Document 1).

  However, in order to create such a structure, when performing channel implantation (impurity implantation) for adjusting the threshold value of the MISFET, non-uniform channel implantation is performed so that the implantation amount on the drain side of the channel is reduced. There must be. Since such implantation becomes more difficult as the channel length becomes shorter, it is not practical for a fine MISFET. For example, in Non-Patent Document 1, this structure is prototyped with a MISFET having a gate length of 0.3 μm. However, when the gate length is 0.1 μm or less, an implantation mask in the manufacturing process is used even if channel implantation is uneven. Due to the difference between the mask for forming the gate electrode and the heat treatment after channel implantation, a non-uniform channel impurity distribution cannot be formed.

  As an alternative method, a self-cascode method has been proposed (see Non-Patent Document 2). In this method, as shown in FIG. 15, the gates of two MISFETs are connected to each other, and the drain of the lower nMISFET MN1 and the source of the upper nMISFET MN2 are connected so that the two MISFETs function as one MISFET. To do. Here, if the threshold value of MN2 is set lower than that of MN1, an effect equivalent to the method of making the channel injection nonuniform in FIG. 14 can be obtained. That is, since the resistance of the channel portion of MN2 is lowered, the electric field applied to MN2 is weakened. As a result, the threshold voltages of MN1 and MN2 are less affected by the drain voltage VD of MN2, and DIBL is reduced. As a result, the differential output resistance ro can be increased as a whole of the two MISFETs.

Masafumi Miyamoto, 3 others, “Asymmetrically-Doped Buried Layer (ADB) Structure CMOS for Low-Voltage Mixed Analog-Digital Applications”, Symposium on VLSI Technology Digest of Technical Papers, USA, American Institute of Electrical and Electronics Engineers (IEEE) July 1996, p. 102-103 Carlos Galup-Montoro, “Series-Parallel of FET's for High Gain and High Frequency Applications”, IEEE Journal of Solid-State Circuits, USA, American Institute of Electrical and Electronics Engineers (IEEE), 1994 9 Month, Vol. 29, no. 9, p. 1094-1101 Ichiro Fujimori, 1 other, A 1.5V, 4.1mW, Dual-Channel Audio Delta-Sigma D / A Converter ", IEEE Journal of Solid-State Circuits, USA, American Institute of Electrical and Electronics Engineers (IEEE), 1998 December, Vol. 33, no. 12, p. 1863-1870

  In the self-cascode method, it is necessary to prepare two types of MISFETs having different MISFET threshold values. There is also a method of changing the substrate voltage of two types of MISFETs (see Non-Patent Document 3), but the substrate voltage is fixed. However, since the threshold difference for obtaining the optimum ro in the self-cascode method differs depending on the gate voltage, the optimum differential output resistance ro cannot be obtained when the bias condition changes if the threshold difference is fixed. There was a problem.

  The main object of the present invention is to always obtain an optimum output resistance in the self-cascode system.

  In one aspect of the present invention, a semiconductor device includes a plurality of MISFETs having the same polarity in which sources or drains are connected in series on a semiconductor substrate, and the gates of the plurality of MISFETs are connected to the same gate terminal. A DC gate bias voltage and an AC signal voltage are applied to the gate terminal, and a MISFET having a higher potential applied to the source or the drain among the plurality of MISFETs is applied to the substrate. The DC substrate bias voltage of the MISFET to which the high potential is applied and the high potential is applied is changed according to a circuit state.

  In the semiconductor device of the present invention, the plurality of MISFETs are preferably two MISFETs.

  In the semiconductor device of the present invention, a first circuit that detects the DC gate bias voltage applied to the gate terminal, and a second circuit that generates a DC reference voltage based on an output signal of the first circuit. The substrate and the source of the first MISFET in which a low or high potential is applied to the source of the two MISFETs are connected to the ground, and the DC reference voltage is the second MISFET separated from the ground The DC reference voltage is a voltage between the ground voltage and the drain voltage of the second MISFET and monotonously decreases with respect to the decrease of the DC gate bias voltage. It is preferable.

  In the semiconductor device of the present invention, it is preferable that the first circuit is a low-pass filter.

  The semiconductor device of the present invention includes a second circuit that generates a DC reference voltage based on the DC gate bias voltage applied to the gate terminal, and a low or high potential is applied to the source of the two MISFETs. The first MISFET substrate and source are connected to ground, the DC reference voltage is applied to a second MISFET substrate remote from the ground, and the DC reference voltage is equal to the ground voltage. It is preferable that the voltage be between the drain voltage of the second MISFET and monotonously decrease with respect to the decrease of the DC gate bias voltage.

  In the semiconductor device of the present invention, it is preferable that the DC reference voltage is represented by a linear function of the DC gate bias voltage.

  In the semiconductor device of the present invention, the second circuit generates the DC reference voltage based on an external reference voltage input from a positive input unit and an output signal of the first circuit input from a negative input unit. Preferably, an operational amplifier to be generated is included.

  According to the present invention, by changing the DC substrate bias voltage of the substrate in accordance with the DC gate bias voltage of the gate terminal, an optimum output resistance can always be obtained in the self-cascode method.

(Embodiment 1)
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram schematically showing the configuration of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a graph showing characteristics of drain voltage VD−drain current ID for each bias voltage VG in the semiconductor device according to Embodiment 1 of the present invention. Hereinafter, an n-type MISFET will be described as an example, but the same circuit can be applied to a p-type MISFET by reversing the polarity of all voltages (the p-type MISFET will be described later).

  In the semiconductor device according to the first embodiment, n-type MISFETs MN1 and MN2 are connected in series. That is, the gate terminals of MN1 and MN2 are connected to each other, and the drain terminal of MN1 and the source terminal of MN2 are connected. The substrate voltage (DC substrate bias voltage) VSUB of MN2 is higher than the substrate voltage (ground voltage; 0 V) of MN1. When the source voltage and the substrate voltage of MN1 are set to 0V, and the drain voltage VD of MN2 is changed with a constant bias voltage (gate voltage) VG applied to the gates of MN1 and MN2, the drain current ID flowing through MN1 and MN2 is As shown in FIG.

  Next, a comparison is made with a circuit obtained by removing MN2 from the semiconductor device according to the first embodiment. FIG. 3 is a circuit diagram schematically showing a configuration of a semiconductor device according to a comparative example. FIG. 4 is a graph showing characteristics of drain voltage VD−drain current ID for each bias voltage VG in the semiconductor device according to the comparative example.

  In the circuit (comparative example; see FIG. 3) in which MN2 is removed from the semiconductor device according to the first embodiment (see FIG. 1), when the drain voltage VD is changed with a constant bias voltage VG applied to the gate, MN1 The drain current ID flowing through is as shown in FIG. The circuit of the first embodiment (see FIG. 2) is less dependent on the drain voltage VD with respect to the drain current ID in the region where the drain voltage VD is higher than the circuit of the comparative example (see FIG. 4). That is, it can be seen that ro (= dVD / dID) is increased.

  FIG. 5 is a graph showing simultaneously the drain voltage VD-drain current ID characteristics and the drain voltage VD-voltage VN characteristics for each bias voltage VG in the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 5, when the drain voltage VD of MN2 is increased, the voltage VN (see FIG. 1) at the connection point between MN1 and MN2 changes greatly at first, but when the drain voltage VD increases to some extent, the connection point voltage is increased. The amount of change in VN becomes small. This is because, when the drain voltage VD is small, both MN1 and MN2 operate in the linear region, so that voltages of almost the same magnitude are applied between the source / drain of MN1 and MN2, but the drain voltage VD is somewhat When it becomes larger, MN2 shifts to the saturation region first, so that a larger voltage is applied between the source / drain of MN2 than between the source / drain of MN1. As a result, the voltage between the source and drain of MN1 is less affected by the drain voltage VD, and the dependency of the drain voltage VD of MN2 on the drain current ID is reduced.

  If the drain voltage VD for shifting the MN2 to the saturation region is too high, the MN1 shifts to the saturation region first, so that an appropriate output resistance cannot be obtained. On the other hand, if it is too low, the channel resistance of MN2 becomes too high and the drain current ID becomes small. Therefore, it is necessary to appropriately select a voltage at which MN2 moves to the saturation region. However, the drain voltage VD depends on the threshold voltage VTH2 of MN2 and the bias voltage VG of MN1 and MN2. Therefore, in FIG. 1, the threshold voltage TH2 of MN2 is changed by manipulating the substrate voltage VSUB applied to the substrate of MN2.

  6 shows a differential output resistance when the bias voltage VG and the drain voltage VD are fixed and the substrate voltage VSUB of MN2 is changed in the circuit of the semiconductor device according to the first embodiment of the present invention (see FIG. 1). It is the graph which showed typically the change of ro (= dVD / dID). Here, the vertical axis represents the value obtained by normalizing the differential output resistance ro with the drain current ID. L is the gate length.

  The substrate voltage VSUB at which the differential output resistance ro is maximized is the optimum substrate bias in the circuit of FIG. 1, but it can be seen that this value varies with the bias voltage VG. Therefore, the result of obtaining the voltage VSUBPEAK of the substrate voltage VSUB at which the differential output resistance ro is maximized corresponds to the point portion shown in FIG. FIG. 7 is a graph schematically showing the results of obtaining the VSUB voltage VSUBPEAK that maximizes the differential output resistance ro for each drain voltage VD of the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 7, VSUBPEAK decreases as the bias voltage VG increases. This bias voltage VG is a value between the ground potential and the drain voltage VD. This relationship is not strictly a linear function, but can be approximated by a linear function in a narrow bias voltage VG range (0.3 to 0.7 V in FIG. 7) as shown by the solid line portion in FIG. Therefore, by generating a reference voltage that is a linear function of the bias voltages VG of MN1 and MN2 in FIG. 1 and applying it to VSUB, the optimum substrate voltage VSUB with respect to the bias voltage VG, that is, the threshold value of MN2 Is obtained.

  FIG. 8 is a circuit diagram schematically showing the configuration (configured with three or more MISFETs) of Modification 1 of the semiconductor device according to Embodiment 1 of the present invention.

  FIG. 8 shows a case where n n-type MISFETs MN1 to MNn are connected in series. Here, the gate terminals of MN1 to MNn are connected to each other, the drain terminal of MN1 and the source terminal of MN2 are connected, the drain terminal of MN2 and the source terminal of MN3 are connected, and the drain terminal of MNn-1 The source terminal of MNn is connected, and the source and substrate of MN1 are connected to the ground. A voltage between the ground voltage and the drain voltage of each MISFET is applied to the substrate voltages VSUB2 to VSUBn of MN2 to MNn, so that “0 <VSUB2 <VSUB3 <... <VSUBn”. A constant bias voltage (gate voltage) VG is applied to the gates of MN1 to MNn. A drain voltage VD (= VDn) is applied to the drain of MNn.

  FIG. 9 is a circuit diagram schematically showing a configuration (configuration in which two p-type MISFETs are connected in series) of Modification 2 of the semiconductor device according to Embodiment 1 of the present invention.

  In the case of FIG. 9, the polarity of all the terminals is reversed from that in FIG. 1 (configuration in which two n-type MISFETs are connected in series), and the voltage of VSUB becomes “VD <VSUB <ground”.

  According to the first embodiment, by changing the DC bias voltage of the substrate in accordance with the DC bias voltage of the gate electrode, it is possible to always obtain an optimum output resistance in the self-cascode method.

  A semiconductor device according to Example 1 of the present invention will be described with reference to the drawings. FIG. 10 is a circuit diagram schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention.

  The semiconductor device according to the first embodiment includes an amplifier circuit including a circuit in which n-type MISFETs MN1 and MN2 are connected in series. The gate of MN1 is connected to the gate of MN2, and is connected to the input unit IN. The source and substrate of MN1 are connected to ground (0V). The drain of MN1 is connected to the source of MN2. The gate of MN2 is connected to the gate of MN1 and is connected to the input unit IN. The source of MN2 is connected to the drain of MN1. The substrate voltage of MN2 is the reference voltage from the reference voltage generation circuit REF1, and is higher than the substrate voltage (ground voltage) of MN1. The drain of MN2 is connected to the power supply voltage VDD via the load resistor RL and is connected to the output unit OUT.

  A signal composed of a DC gate bias voltage and an AC signal voltage is input to the input section IN. The low-pass filter LP1 is a circuit that detects a bias voltage of the gate electrode, and a signal obtained by removing interference waves and spurious components generated by the signal itself from the signal from the input unit IN is supplied to the reference voltage generation circuit REF1. Output toward. Based on the signal from the low-pass filter LP1, the reference voltage generation circuit REF1 generates a reference voltage that monotonously decreases with respect to the decrease in the bias voltage, and outputs the reference voltage toward the substrate of MN2.

  According to the first embodiment, since the gate voltage (bias voltage) can be detected and the threshold voltage of MN2 can be automatically changed, the optimum threshold value of MN2 can always be obtained.

  Example 2 A semiconductor device according to Example 2 of the present invention will be described with reference to the drawings. FIG. 11 is a circuit diagram schematically showing a configuration of a semiconductor device according to the second embodiment of the present invention.

  The semiconductor device according to the second embodiment includes an amplifier circuit including a circuit in which n-type MISFETs MN1 and MN2 are connected in series. The gate of MN1 is connected to the gate of MN2, and is connected to the input unit IN. The source and substrate of MN1 are connected to ground (0V). The drain of MN1 is connected to the source of MN2. The gate of MN2 is connected to the gate of MN1 and is connected to the input unit IN. The source of MN2 is connected to the drain of MN1. The substrate voltage of MN2 is the output voltage “− (IN−VR) × R2 / R1 + VR” of the operational amplifier O1, which is higher than the substrate voltage (ground voltage) of MN1. The drain of MN2 is connected to the power supply voltage VDD via the load resistor RL and is connected to the output unit OUT.

  A signal composed of a DC bias voltage and an AC signal voltage is input to the input unit IN. The low-pass filter LP1 directs a signal obtained by removing interference waves and spurious components generated in the signal itself from the signal from the input unit IN to the resistor R2 and the negative input unit of the operational amplifier O1 via the resistor R1. Output. The resistor R2 is connected in parallel with the operational amplifier O1 between the resistor R1 and the substrate of MN2. The operational amplifier O1 outputs the output voltage “− (IN−) based on the external reference voltage VR input from the positive input unit, the input voltage IN input from the negative input unit, the resistor R1, and the resistor R2. VR) × R2 / R1 + VR ”is output toward the substrate of MN2. The output voltage of the operational amplifier O1 is expressed by a linear function determined by the resistor R1, the resistor R2, and the reference voltage VR.

  According to the second embodiment, by applying the output voltage of the operational amplifier O1 to the substrate of MN2, a substrate voltage of MN2 proportional to the gate voltage (bias voltage) is generated, and an optimum threshold value of MN2 is always obtained. It is done.

  Example 3 A semiconductor device according to Example 3 of the present invention will be described with reference to the drawings. FIG. 12 is a circuit diagram schematically showing the configuration of the semiconductor device according to the third embodiment of the present invention.

  The semiconductor device according to the third embodiment includes an amplifier circuit including a circuit in which n-type MISFETs MN1 and MN2 are connected in series. The gate of MN1 is connected to the gate of MN2, and is connected to the input unit IN. The source and substrate of MN1 are connected to ground (0V). The drain of MN1 is connected to the source of MN2. The gate of MN2 is connected to the gate of MN1 and is connected to the input unit IN. The source of MN2 is connected to the drain of MN1. The substrate voltage of MN2 is the output voltage “− (IN−VR) × R2 / R1 + VR” of the operational amplifier O1, which is higher than the substrate voltage (ground voltage) of MN1. The drain of MN2 is connected to the power supply voltage VDD via the load resistor RL and is connected to the output unit OUT.

  A signal composed of a DC bias voltage and an AC signal voltage is input to the input unit IN. A signal from the input unit IN is input to the resistor R2 and the negative input unit of the operational amplifier O1 via the resistor R1. The resistor R2 is connected in parallel with the operational amplifier O1 between the resistor R1 and the substrate of MN2. The operational amplifier O1 outputs the output voltage “− (IN−) based on the external reference voltage VR input from the positive input unit, the input voltage IN input from the negative input unit, the resistor R1, and the resistor R2. VR) × R2 / R1 + VR ”is output toward the substrate of MN2. The output voltage of the operational amplifier O1 is expressed by a linear function determined by the resistor R1, the resistor R2, and the reference voltage VR. Here, the band of the output voltage of the operational amplifier O1 is lower than the AC signal input to the input unit IN, and only the DC bias voltage is amplified.

  According to the third embodiment, by applying the output voltage of the operational amplifier O1 to the substrate of MN2, a substrate voltage of MN2 proportional to the gate voltage (bias voltage) is generated, and an optimum threshold value of MN2 is always obtained. It is done.

1 is a circuit diagram schematically showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. 4 is a graph showing the characteristics of drain voltage VD−drain current ID for each bias voltage VG in the semiconductor device according to the first exemplary embodiment of the present invention. It is the circuit diagram which showed typically the structure of the semiconductor device which concerns on a comparative example. It is the graph which showed the characteristic of drain voltage VD-drain current ID for every bias voltage VG in the semiconductor device concerning a comparative example. 6 is a graph showing simultaneously the drain voltage VD−drain current ID characteristics and the drain voltage VD−voltage VN characteristics for each bias voltage VG in the semiconductor device according to the first exemplary embodiment of the present invention. In the circuit of the semiconductor device according to the first embodiment of the present invention (see FIG. 1), the differential output resistance ro (= dVD) when the bias voltage VG and the drain voltage VD are fixed and the substrate voltage VSUB of MN2 is changed. / DID) is a graph schematically showing changes. 6 is a graph schematically showing a result of obtaining a VSUB voltage VSUBPEAK at which a differential output resistance ro for each drain voltage VD of the semiconductor device according to the first exemplary embodiment of the present invention is maximized. FIG. 6 is a circuit diagram schematically showing a configuration (configured with three or more MISFETs) of Modification 1 of the semiconductor device according to Embodiment 1 of the present invention. It is the circuit diagram which showed typically the structure (structure which connected two p-type MISFET in series) of the modification 2 of the semiconductor device which concerns on Embodiment 1 of this invention. It is the circuit diagram which showed typically the structure of the semiconductor device which concerns on Example 1 of this invention. It is the circuit diagram which showed typically the structure of the semiconductor device which concerns on Example 2 of this invention. It is the circuit diagram which showed typically the structure of the semiconductor device which concerns on Example 3 of this invention. 10 is a schematic diagram for explaining the operation of a MISFET in a semiconductor device according to Conventional Example 1. FIG. 10 is a schematic diagram for explaining the operation of an asymmetric MISFET in a semiconductor device according to Conventional Example 2. FIG. 10 is a circuit diagram schematically showing a self-cascode configuration in a semiconductor device according to Conventional Example 3. FIG.

Explanation of symbols

MN1, MN2, MN3, MNn nMISFET
MP1, MP2 pMISFET
VG bias voltage (gate voltage, DC gate bias voltage)
VD, VD1, VD2, VD3, VDn Drain voltage VSUB, VSUB2, VSUB3, VSUBn Substrate voltage (DC substrate bias voltage)
VN Connection point voltage ID Drain current VDD Power supply voltage RL Load resistance OUT Output part IN Input part (input voltage, gate terminal)
LP1 Low-pass filter REF1 Reference voltage generation circuit R1, R2 Resistance VR Reference voltage O1 Operational amplifier

Claims (7)

A plurality of MISFETs having the same polarity in which sources or drains are connected in series with each other on a semiconductor substrate;
The gates of the plurality of MISFETs are connected to the same gate terminal,
A DC gate bias voltage and an AC signal voltage are applied to the gate terminal,
The MISFET having a higher potential applied to the source or the drain among the plurality of MISFETs has a higher DC substrate bias voltage applied to the substrate,
A semiconductor device configured to change the DC substrate bias voltage of the MISFET to which the high potential is applied in accordance with a circuit state.   2. The semiconductor device according to claim 1, wherein the plurality of MISFETs are two MISFETs. A first circuit for detecting the DC gate bias voltage applied to the gate terminal;
A second circuit for generating a DC reference voltage based on an output signal of the first circuit;
With
The substrate and source of the first MISFET in which a low or high potential is applied to the source of the two MISFETs are connected to the ground,
The DC reference voltage is applied to a substrate of a second MISFET remote from the ground,
The DC reference voltage is a voltage between the ground voltage and the drain voltage of the second MISFET, and monotonously decreases with respect to a decrease in the DC gate bias voltage. Item 3. The semiconductor device according to Item 2.   The semiconductor device according to claim 3, wherein the first circuit is a low-pass filter. A second circuit for generating a DC reference voltage based on the DC gate bias voltage applied to the gate terminal;
The substrate and source of the first MISFET in which a low or high potential is applied to the source of the two MISFETs are connected to the ground,
The DC reference voltage is applied to a substrate of a second MISFET remote from the ground,
The DC reference voltage is a voltage between the ground voltage and the drain voltage of the second MISFET, and monotonously decreases with respect to a decrease in the DC gate bias voltage. Item 3. The semiconductor device according to Item 2.   6. The semiconductor device according to claim 3, wherein the DC reference voltage is expressed by a linear function of the DC gate bias voltage.   The second circuit includes an operational amplifier that generates the DC reference voltage based on an external reference voltage input from a positive input unit and an output signal of the first circuit input from a negative input unit. The semiconductor device according to claim 3, wherein the semiconductor device is a semiconductor device.

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