JP2011113321A - Reference voltage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage circuit for achieving reduction in size by microfabrication process and obtaining a high power supply rejection ratio. <P>SOLUTION: The reference voltage circuit includes: a first transistor M1, i.e., an enhancement type N-channel transistor the gate and the drain of which are connected; a second transistor M2, i.e., a depletion type N-channel transistor the gate of which is connected to the gate of the first transistor M1 and the source of the transistor M2 itself where the first transistor M1 and the second transistor M2 are connected in series via the drain of the first transistor M1, and the reference voltage is generated at each gate of the first transistor M1 and the second transistor M2. The reference voltage circuit further includes a third transistor M3, i.e., a depletion type N-channel transistor the absolute threshold of which is larger than that of the second transistor M2, and the current drive capability of which is higher than that of the second transistor M2, and the third transistor M3 is connected in series via the drain of the second transistor M2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a reference voltage circuit, and is particularly useful when applied to power management of equipment represented by a voltage regulator.

  In recent years, mobile devices represented by mobile phones and the like have been widely used, and the size of the devices has been reduced. It is miniaturization of the semiconductor integrated circuit that enables such miniaturization. With the miniaturization of such semiconductor integrated circuits, the operating voltage decreases, while stabilization of the power supply voltage is required from the viewpoint of preventing malfunction of the logic circuit.

  By the way, various noises and voltage fluctuations are included in a power supply line that is input to a power management IC represented by a voltage regulator that is responsible for supplying a power supply voltage for a semiconductor integrated circuit. For this reason, the power management IC is required to have a high power supply voltage fluctuation removal characteristic (PSRR; Power Supply Rejection Ratio). Here, the power supply voltage fluctuation removal characteristic is an index representing the ability to remove noise and voltage fluctuations included in the power supply line.

  Furthermore, the power management IC itself needs to be downsized. For this reason, it is also necessary to promote high integration using a fine process.

  Therefore, various reference voltage circuits have been proposed in order to obtain higher power supply voltage fluctuation elimination characteristics than ever before. For example, reference voltage circuits disclosed in Patent Documents 1 to 3 can be given.

  As shown in FIG. 21, the reference voltage circuit disclosed in Patent Document 1 includes a first transistor M1 that is an N-channel enhancement type transistor and an N-channel that is connected in series via the drain of the first transistor M1. A second transistor M2 which is a depletion type transistor, and the reference voltage Vref resulting from the difference in threshold value VTH between the first transistor M1 and the second transistor M2 is used as the first transistor M1 and the second transistor M2. A circuit generated at the gate of the second transistor M2 is a basic circuit. The basic circuit includes a third transistor which is an N-channel depletion type transistor having its own gate connected to its own source via the drain of the second transistor M2. The transistors M3 are connected in series.

  As shown in FIG. 22, the reference voltage circuit disclosed in Patent Document 2 forms a current mirror circuit with a third transistor M3 and a thirteenth transistor M13, which is an N-channel depletion type transistor, and includes a first transistor M1. A fourteenth transistor M14, which is an N-channel enhancement type transistor with its own gate connected to the gate of the first transistor, is connected in series via the source of the thirteenth transistor M13. Therefore, the configuration can be such that the gate of the third transistor M3 in the reference voltage circuit of Patent Document 1 (see FIG. 21) is not connected to the source.

  As shown in FIG. 23, the reference voltage circuit disclosed in Patent Document 3 is provided with a voltage regulator in the preceding stage on the power supply side of the reference voltage generation circuit.

Japanese Patent No. 4084872 JP 2007-188245 A JP 2004-362300 A

  However, in Patent Document 1, the power supply voltage fluctuation removal characteristic in the high frequency region is significantly reduced.

  In Patent Document 2, the power supply voltage fluctuation elimination characteristic in the high frequency region is improved. However, if the process becomes finer and the gate length modulation effect of the transistor itself becomes larger, the influence of the gate length modulation effect may be removed. As a result, the overall power supply voltage fluctuation removal characteristic including the low frequency region is deteriorated. As a result, a problem arises in coexistence with downsizing.

  In Patent Document 3, although a high power supply voltage fluctuation elimination characteristic can be obtained with respect to a high input voltage, a large voltage regulator must be disposed in front of the reference voltage generation circuit, and the power management IC itself can be downsized. It can not meet the demands of.

  An object of the present invention is to provide a reference voltage circuit capable of obtaining a high power supply voltage fluctuation removal characteristic while realizing miniaturization by a fine process in view of the above-described prior art.

  According to a first aspect of the present invention for achieving the above object, there is provided a first transistor which is an N-channel enhancement type transistor having its own gate connected to its own drain, and its own gate is the gate of the first transistor. And a second transistor which is an N-channel depletion type transistor connected to its own source and connected in series via the drain of the first transistor, the first transistor and the second transistor A reference voltage circuit for generating a reference voltage at the gate of the second transistor, the threshold value of the reference voltage circuit having a larger absolute value than the threshold value of the second transistor, and a current drive capability higher than that of the second transistor A third transistor, which is an N-channel depletion type transistor, includes the second transistor. The transistors are connected in series via the drain of the transistor, a constant voltage is applied to the gate of the third transistor, and the substrate of the third transistor is connected to the substrate of the first transistor. The reference voltage circuit is characterized by the following.

  According to this aspect, the back gate bias effect caused by the potential difference between the source of the third transistor and the substrate is more prominent as compared with the prior art shown in FIGS. That is, since the third transistor is connected in series to the second transistor, it is necessary to pass the same current through both transistors, and the source voltage of the third transistor is set slightly higher than the reference voltage by applying a back gate bias. Try to fix at a high potential. At this time, in this embodiment, the current driving capability of the third transistor is made larger than that of the second transistor, and the absolute value of the threshold value of the third transistor is made larger than that of the second transistor. The back gate bias can be applied more effectively, and the reference voltage can be stabilized more remarkably.

  As a result, it is possible to obtain a high power supply voltage fluctuation removal characteristic in a wide frequency band without causing a reduction in the power supply voltage fluctuation removal characteristic due to the gate length modulation effect by a fine process.

  A second aspect of the present invention is the reference voltage circuit according to the first aspect, wherein a bias voltage generated by a bias circuit different from the reference voltage circuit is applied to the gate of the third transistor. The reference voltage circuit is configured as described above.

  According to a third aspect of the present invention, there is provided the reference voltage circuit according to the first aspect, wherein the reference voltage is applied to a gate of the third transistor. In the reference voltage circuit.

  According to a fourth aspect of the present invention, there is provided the reference voltage circuit according to the first aspect, wherein the source voltage of the first transistor is applied to the gate of the third transistor. The reference voltage circuit is characterized in that.

  According to the second to fourth aspects, the voltage applied to the gate of the third transistor can be easily made constant. At the same time, the same actions and effects as the first aspect are also exhibited.

  According to a fifth aspect of the present invention, in any one of the reference voltage circuits described in the first to fourth aspects, the N channel is connected in series to the third transistor via the drain of the third transistor. A fourth transistor which is a depletion type transistor, and a predetermined bias voltage is applied to the gate of the fourth transistor from a bias circuit different from the reference voltage circuit. It is in the characteristic reference voltage circuit.

  According to this aspect, since the fourth transistor is connected in series via the drain of the third transistor, and the predetermined bias voltage is applied to the fourth transistor, the power supply voltage on the input side varies. Even if the channel resistance of the fourth transistor itself changes, the fluctuation of the voltage on the source side of the fourth transistor, that is, the voltage on the drain side of the third transistor is suppressed. By superimposing the effects of the first embodiment, higher power supply voltage fluctuation elimination characteristics can be obtained.

  According to a sixth aspect of the present invention, in the reference voltage circuit according to the fifth aspect, the threshold value of the fourth transistor is the same as the threshold value of the second transistor. .

  According to a seventh aspect of the present invention, in the reference voltage circuit according to the fifth aspect, the threshold value of the fourth transistor is the same as the threshold value of the third transistor. .

  According to an eighth aspect of the present invention, the current determined by the second transistor, which is an N-channel depletion type transistor whose gate and source are connected, is an N-channel enhancement type transistor via a current mirror circuit. A reference voltage circuit for supplying a reference voltage to a first transistor and generating a reference voltage at the gate of the first transistor. The threshold value of the reference voltage circuit is larger than the threshold value of the second transistor. And a third transistor, which is an N-channel depletion type transistor, whose current driving capability is higher than that of the second transistor, is connected in series via the drain of the second transistor and has its own drain Is connected to the current mirror circuit via Of the gate of the transistor is constant voltage is applied, in the reference voltage circuit substrate of the third transistor is characterized in that it is connected to the substrate of the first transistor.

  According to this aspect, since the current supplied from the power supply voltage is shunted to the first transistor and the second transistor by the current mirror circuit, the first transistor to the third transistor are connected in series. As a result of being able to operate at a lower power supply voltage than in the case of the first aspect and at the same time exhibiting the same effect as the first aspect, high power supply voltage fluctuation removal in a wide frequency band as in the first aspect. Characteristics can be obtained.

  A ninth aspect of the present invention is the reference voltage circuit according to the eighth aspect, wherein a bias voltage generated by a bias circuit different from the reference voltage circuit is applied to the gate of the third transistor. The reference voltage circuit is configured to be configured as described above.

  A tenth aspect of the present invention is the reference voltage circuit according to the eighth aspect, characterized in that the reference voltage is applied to the gate of the third transistor. In the reference voltage circuit.

  An eleventh aspect of the present invention is the reference voltage circuit according to the eighth aspect, wherein the source voltage of the first transistor is applied to the gate of the third transistor. The reference voltage circuit is characterized in that.

  According to the ninth to eleventh aspects, the voltage applied to the gate of the third transistor can be easily made constant. In addition, the same operations and effects as in the eighth aspect are also exhibited.

  According to a twelfth aspect of the present invention, in any one of the reference voltage circuits described in the eighth to eleventh aspects, the third voltage transistor is connected in series to the third transistor via the drain of the third transistor. A fourth transistor which is an N-channel depletion type transistor connected to the current mirror circuit through the drain of the first transistor, and a gate of the fourth transistor is supplied from a bias circuit different from the reference voltage circuit. The reference voltage circuit is configured to apply a predetermined bias voltage.

  According to this aspect, the fourth transistor is connected in series with the current mirror circuit via the drain of the third transistor, and a predetermined bias voltage is applied to the fourth transistor. Even if the power supply voltage on the input side fluctuates, the channel resistance of the fourth transistor itself changes, thereby suppressing the fluctuation of the voltage on the source side of the fourth transistor, that is, the voltage on the drain side of the third transistor. As a result, this suppression effect and operation with a lower power supply voltage than in the fifth embodiment in which the first to third transistors are connected in series are possible, and at the same time as compared with the eighth embodiment. Further, it is possible to obtain a higher power supply voltage fluctuation elimination characteristic.

  According to a thirteenth aspect of the present invention, in the reference voltage circuit according to the twelfth aspect, the threshold value of the fourth transistor is the same as the threshold value of the second transistor. .

  According to a fourteenth aspect of the present invention, in the reference voltage circuit according to the twelfth aspect, the threshold voltage of the fourth transistor is the same as the threshold voltage of the third transistor. .

  According to the present invention, in combination with the stabilization of the reference voltage due to the back gate bias effect caused by the potential difference between the source and the substrate of the third transistor, the power source caused by the gate length modulation effect by the fine process A high power supply voltage fluctuation removal characteristic can be obtained in a wide frequency band without deteriorating the voltage fluctuation removal characteristic.

  Furthermore, since the present invention can be applied not only to a fine process but also to a high withstand voltage process or a mixed mounting process thereof, it can be developed in a wide range of applications. As a result, the power management IC can be miniaturized and high power supply voltage fluctuation elimination characteristics can be realized at the same time.

1 is a circuit diagram showing a reference voltage circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the reference voltage circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit which concerns on the 4th Embodiment of this invention. FIG. 10 is a characteristic diagram illustrating a relationship of power supply voltage fluctuation removal characteristics with respect to a current drive capability ratio (M3 / M2) between the third transistor M3 and the second transistor M2 in the first to fourth embodiments. FIG. 10 is a characteristic diagram illustrating a relationship of power supply voltage fluctuation removal characteristics with respect to a threshold difference between the second transistor M2 and the third transistor M3 in the first to fourth embodiments. The current drive capability ratio (M3 / M2) between the third transistor M3 and the second transistor M2 in the first to fourth embodiments is 12.5, and the second transistor M2 and the third transistor M3 FIG. 22 is a characteristic diagram showing a power supply voltage fluctuation elimination characteristic in comparison with the conventional technique shown in FIG. It is a circuit diagram which shows the reference voltage circuit which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit which concerns on the 7th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit which concerns on the 8th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit which concerns on the 9th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit based on the 10th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit based on the 11th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit based on the 12th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit based on the 13th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit based on the 14th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit based on the 15th Embodiment of this invention. It is a circuit diagram which shows the reference voltage circuit based on the 16th Embodiment of this invention. 1 is a circuit diagram showing an example of a voltage regulator having a reference voltage circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the reference voltage circuit which concerns on a prior art (patent document 1). It is a circuit diagram which shows the reference voltage circuit which concerns on a prior art (patent document 2). It is a block diagram which shows the reference voltage circuit which concerns on a prior art (patent document 3).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that, in each embodiment, functionally identical parts are denoted by the same reference numerals, and redundant description is omitted.

<First to fourth embodiments>
FIG. 1 is a circuit diagram showing a reference voltage circuit according to the first embodiment of the present invention. As shown in the figure, the reference voltage circuit according to the first embodiment includes a first transistor M1, which is an N-channel enhancement type transistor, whose gate is connected to its drain, and whose gate is A basic circuit in which a second transistor M2, which is an N-channel depletion type transistor connected to the gate of the first transistor M1 and connected to its own source, is connected in series via the drain of the first transistor M1. have. In this basic circuit, the reference voltage Vref defined by the difference between the threshold value VTH of the first transistor M1 and the threshold value VTH of the second transistor M2 is the gate of the first transistor M1 and the second transistor M2 (the first transistor Obtained at the drain of the transistor M1 and the source of the second transistor M2.

  The third transistor M3, which is an N-channel depletion type transistor, has an absolute value larger than the threshold value of the second transistor M2 and has a higher current driving capability than the current driving capability of the second transistor M2. Are connected in series via the drain of the second transistor M2. Here, in order to increase the current drive capability, there are a method of reducing the channel length L, a method of increasing the channel width W, and a method of implementing both. Usually, the channel length L of the second transistor M2 is set to be large, so that the method of reducing the channel length L of the third transistor M3 is advantageous in terms of area efficiency in consideration of the transistor size.

  Furthermore, a constant voltage is applied to the gate of the third transistor M3. In the first embodiment, the reference voltage Vref, which is a constant voltage, is applied by commonly connecting the gate of the third transistor M3 to the gates of the first transistor M1 and the second transistor M2. ing.

  The substrate of the third transistor M3 is connected to the substrate of the first transistor M1. The substrate of the third transistor M3 in the first embodiment is connected to GND together with the substrate of the first transistor M1.

  The fourth transistor M4, which is an N-channel depletion type transistor, is connected in series to the third transistor M3 via the drain of the third transistor M3. Here, a predetermined bias voltage is applied to the gate of the fourth transistor M4 from a bias circuit 1 different from the reference voltage circuit, and a power source from a power source (not shown) is applied to the drain of the fourth transistor M4. A voltage Vin is applied. Here, the threshold value of the fourth transistor M4 may be the same as the threshold value of the second transistor M2 or the threshold value of the third transistor M3.

  Further, in the first embodiment, the substrate of the fourth transistor M4 is connected to the GND together with the substrate of the second transistor in the same manner as the first transistor M1 and the third transistor M3. However, the substrates of the second transistor M2 and the fourth transistor M4 do not necessarily have the same potential as the substrates of the first transistor M1 and the third transistor M3.

  In the first embodiment, the reference voltage Vref, which is a constant voltage, is applied to the gate of the third transistor M3. However, the present invention is not limited to this. For example, a GND voltage may be applied as in the second embodiment shown in FIG. 2, and as in the third and fourth embodiments shown in FIGS. The bias voltage generated by the bias circuits 1, 2, and 3 different from the reference voltage circuit may be applied. The third and fourth embodiments shown in FIGS. 3 and 4 have essentially the same configuration, but the third embodiment is independent of the bias circuit 1 of the fourth transistor M4. This is a case where the bias circuit 2 of the third transistor M3 is provided, and the fourth embodiment is a case where the common bias circuit 3 is provided for the fourth transistor M4 and the third transistor M3.

  According to the first to fourth embodiments, the reference voltage is based on the difference between the threshold value VTH of the first transistor M1 that is an enhancement type transistor and the threshold value VTH of the second transistor M2 that is a depletion type transistor. Vref is defined.

  As the process becomes finer, the gate length modulation effect increases, and as a result, it becomes difficult to maintain high power supply voltage fluctuation elimination characteristics in the prior art shown in FIGS.

  In contrast, in the first to fourth embodiments, the third transistor M3 is connected in series to the second transistor M2, and the absolute value of the threshold value of the third transistor M3 is the second value. Is larger than the absolute value of the threshold value of the transistor M2, the current driving capability of the third transistor M3 is set to be larger than that of the second transistor M2, and a constant voltage is applied to the gate of the third transistor M3. Since the substrate of the third transistor M3 is connected to the substrate of the first transistor M1, the back gate bias effect caused by the potential difference between the source of the third transistor M3 and the substrate Is more prominent than the prior art shown in FIGS. That is, since the third transistor M3 is connected in series to the second transistor M2, it is necessary to flow the same current through both transistors, and the source voltage of the third transistor M3 is applied to the reference voltage by applying a back gate bias. An attempt is made to fix the potential slightly higher than Vref. At this time, since the first to fourth embodiments have the above-described specific structural requirements, the back gate bias can be applied more effectively, and the reference voltage can be more significantly stabilized. Can be planned.

  Furthermore, according to the first to fourth embodiments, the fourth transistor M4 is connected in series via the drain of the third transistor M3, and the fourth transistor M4 includes the predetermined bias circuits 1 and 3. Since a predetermined bias voltage is applied from the above, even if the power supply voltage Vin on the input side fluctuates, the channel resistance of the fourth transistor M4 itself changes, so that the voltage on the source side of the fourth transistor M4, that is, The fluctuation of the voltage on the drain side of the third transistor M3 is suppressed, and this suppression effect and the effect of the third transistor M3 as described above are superimposed, so that a higher power supply voltage fluctuation elimination characteristic can be obtained. .

  FIG. 5 is a characteristic showing the relationship of the power supply voltage fluctuation removal characteristic (PSRR) with respect to the current drive capability ratio (M3 / M2) between the third transistor M3 and the second transistor M2 in the first to fourth embodiments. FIG. Referring to the figure, when the channel length L to the channel width W are adjusted to increase the current drive capability of the third transistor M3 relative to the current drive capability of the second transistor M2, the power supply voltage fluctuation elimination characteristic is obtained. It can be seen that is greatly improved. Here, the threshold value of the second transistor M2 is selected to be −0.50 (V), and the threshold value of the third transistor M3 is selected to be −0.85 (V).

  FIG. 6 is a characteristic diagram showing the relationship of the power supply voltage fluctuation removal characteristic with respect to the difference in threshold value VTH between the second transistor M2 and the third transistor M3 in the first to fourth embodiments. Referring to the figure, it can be seen that the larger the difference in threshold value VTH between the second transistor M2 and the third transistor M3, the better the power supply voltage fluctuation removal characteristic. In order to realize a power supply voltage fluctuation elimination characteristic of −88 dB that has recently been required as a reference power supply circuit, it is desirable that the difference in threshold VTH is 0.35 (V) or more. Conventionally, the power supply voltage fluctuation removal characteristic at 10 kHz has been sufficiently satisfied at −60 to −70 dB.

  Furthermore, FIG. 7 shows that the current drive capability ratio (M3 / M2) between the third transistor M3 and the second transistor M2 in the first to fourth embodiments is 12.5, and the second transistor M2 and the second transistor M2 FIG. 22 is a characteristic diagram showing a power supply voltage fluctuation elimination characteristic in comparison with the conventional technique shown in FIG. 21 when the difference in threshold value VTH from the transistor 3 of FIG. Referring to the figure, it can be seen that the power supply voltage fluctuation elimination characteristics are remarkably improved in the wide frequency range in the first to fourth embodiments of the present invention as compared with the prior art. In the first to fourth embodiments, the power supply voltage fluctuation elimination characteristic of −88 dB, which has been recently required, can be easily realized, whereas the conventional technique requires −60. It is clearly shown that only -70 dB is satisfied.

<Fifth to seventh embodiments>
The first to fourth embodiments all have the fourth transistor M4. However, the fourth transistor M4 can be omitted. That is, it can be configured as in the fifth to seventh embodiments shown in FIGS. The fifth embodiment shown in FIG. 8 is obtained by omitting the fourth transistor M4 from the first embodiment shown in FIG. 1. Similarly, the sixth embodiment shown in FIG. From the second embodiment shown, the seventh embodiment shown in FIG. 10 is the case where the fourth transistor M4 is omitted from the third embodiment shown in FIG.

  As a result, in the fifth to seventh embodiments, the fourth transistor M4 is omitted, so that it is possible to operate with a lower power supply voltage Vin than in the first to fourth embodiments. . At the same time, although the power supply voltage fluctuation removal characteristics are slightly inferior to those of the first to fourth embodiments, the power supply voltage fluctuation removal characteristics are higher than those in the case of the reference voltage circuit according to the prior art shown in FIGS. Obtainable. Also in the fifth to seventh embodiments, the back gate bias effect due to the potential difference between the source and the substrate of the third transistor M3 is more prominent than in the prior art shown in FIGS. Because it is done.

<Eighth to Tenth Embodiment>
FIG. 11 is a circuit diagram showing a reference voltage circuit according to the eighth embodiment of the present invention. As shown in the figure, in the reference voltage circuit according to the eighth embodiment, the current determined by the second transistor M2 having its own gate and source connected to each other through the current mirror circuit. The basic circuit configured to be supplied to the transistor M1 is combined with the configuration of the reference voltage circuit according to the first embodiment shown in FIG. More specifically, the current mirror circuit includes a fifth transistor M5, which is a P-channel enhancement type transistor, and a sixth transistor M6, which is a P-channel enhancement type transistor, and the fifth and sixth transistors M5. , M6 has a power supply voltage Vin applied to its drains. A third transistor M3 and a fourth transistor M4 are connected in series between the current mirror circuit and the drain of the second transistor M2. Here, the third transistor M3 has its own threshold value set larger than the threshold value of the M2 and the current drive capability higher than the current drive capability of the second transistor M2. In addition, the gate of the third transistor M3 is connected to GND which is a constant voltage together with the gate of the second transistor M2, and the substrate is connected to GND in the same manner as the substrate of the first transistor M1. . A predetermined bias voltage is applied to the gate of the fourth transistor M4 from a bias circuit 1 different from the reference voltage circuit.

  The threshold value of the fourth transistor M4 may be the same as the threshold value of the second transistor M2 or the threshold value of the third transistor M3. Furthermore, in the eighth embodiment, the substrate of the fourth transistor M4 is connected to the GND together with the substrate of the second transistor, similarly to the first transistor M1 and the third transistor M3. However, the substrates of the second transistor M2 and the fourth transistor M4 do not necessarily have the same potential as the substrates of the first transistor M1 and the third transistor M3.

  On the other hand, the gate of the first transistor M1 is connected to the source of the seventh transistor M7, which is an N-channel depletion type transistor, and to the GND via the resistor R. The power supply voltage Vin is applied to the drain of the seventh transistor M7. As a result, the reference voltage Vref based on the difference between the threshold value VTH of the first transistor M1 and the threshold value VTH of the second transistor M2 is obtained at the gate of the first transistor M1.

  Further, as in the ninth embodiment shown in FIG. 12, the reference voltage Vref1 higher than the reference voltage Vref is obtained by the resistance ratio of the resistors R1 and R2 connected to the gate of the first transistor M1. You may do it. The reference voltage Vref1 in this case is given by the following equation (1).

    Vref1 = {(R1 + R2) / R1} × Vref (1)

  Further, as in the tenth embodiment shown in FIG. 13, the reference voltage Vref2 lower than the reference voltage Vref is obtained by the resistance ratio of the resistors R1 and R2 connected to the gate of the first transistor M1. You may do it. The reference voltage Vref2 in this case is given by the following equation (2).

    Vref2 = {R1 / (R1 + R2)} × Vref (2)

  According to the eighth to tenth embodiments as described above, since the current supplied from the power source is shunted to the first transistor M1 and the second transistor M2 by the current mirror circuit, the first transistor Operation with a lower power supply voltage Vin than in the case of the first embodiment in which M1 to M4 transistors M4 are connected in series is possible, and at the same time, the same operational effects as the first embodiment are exhibited. As a result, high power supply voltage fluctuation removal characteristics can be obtained in a wide frequency band as in the first embodiment.

<Other embodiments>
The reference voltage circuits according to the eighth to tenth embodiments shown in FIGS. 11 to 13 are combinations of the current mirror circuit and the configuration of the reference voltage circuit according to the first embodiment shown in FIG. However, the present invention is not limited to such a combination. Any of the reference voltage circuits according to the second to seventh embodiments can be combined. That is, the block A connected to the fifth transistor M5 constituting the current mirror circuit shown in FIGS. 11 to 13 can be replaced with the blocks A1 to A6 shown in FIGS. These will be described in further detail as eleventh to sixteenth embodiments.

  The block A1 in the eleventh embodiment shown in FIG. 14 is based on the configuration corresponding to the second embodiment shown in FIG. 2, and is configured to apply the reference voltage Vref to the gate of the third transistor M3. Thus, the block A in FIG. 11 is replaced.

  A block A2 in the twelfth embodiment shown in FIG. 15 corresponds to the third embodiment shown in FIG. 3, and a block A3 in the thirteenth embodiment shown in FIG. 16 is shown in FIG. In the configuration corresponding to the fourth embodiment, the block A4 in the fourteenth embodiment shown in FIG. 17 is the configuration corresponding to the fifth embodiment shown in FIG. 8, and each block A4 shown in FIG. Is a replacement.

  The block A5 in the fifteenth embodiment shown in FIG. 18 is based on the configuration corresponding to the sixth embodiment shown in FIG. 9, and is configured to apply the reference voltage Vref to the gate of the third transistor M3. Thus, the block A in FIG. 11 is replaced.

  The block A6 in the sixteenth embodiment shown in FIG. 19 is obtained by replacing the block A shown in FIG. 11 with a configuration corresponding to the seventh embodiment shown in FIG.

  Of course, each reference voltage circuit having the configuration in which the block A shown in FIGS. 12 to 13 is replaced by the blocks A1 to A6 can be included as each embodiment of the present invention.

  Further, each of the above embodiments has been described for the case where an N-channel MOS transistor is formed on a P-type silicon substrate. However, even when a P-well region is formed on an N-type silicon substrate and an N-channel MOS is formed in that region. Similar effects can be obtained. The substrate potential in this case is the potential of the P well regions connected to each other. That is, it does not depend on the polarity of the semiconductor substrate. The effect of the present invention is not affected by the polarity of the gate electrode or the impurity concentration.

  The present invention can achieve the same effect even when the input voltage is a high voltage power supply of, for example, 10 V or more. In this case, the third transistor M3 and the fourth transistor M4 may be high breakdown voltage transistors such as Locos offset type transistors and mask LDD type transistors. At this time, the first transistor M1 or the second transistor M2 may be a conventional transistor having a low breakdown voltage, or may be a transistor with a high breakdown voltage. In this case, since the gate oxide film thickness and the drain structure are often different, the current drive capability ratio is not the transistor size ratio, and it is necessary to consider the current drive capability including the gate oxide film thickness and the drain resistance.

<Voltage regulator>
FIG. 20 is a circuit diagram showing an example of a voltage regulator having the reference voltage circuit according to the first embodiment shown in FIG. As shown in the figure, the voltage regulator uses the feedback voltage Vfb, which is defined by the voltage dividing ratio of the resistors R3 and R4 and follows the output voltage Vout, and a predetermined reference voltage Vref as inputs of the differential amplifier 5. The output voltage Vout is adjusted to be constant by controlling the on-resistance of the tenth transistor M10 according to the deviation between the two. Here, the eleventh and twelfth transistors M11 and M12 constitute a bias circuit that generates a constant voltage to be applied to the gate of the fourth transistor M4 with the current supplied from the current source Iref.

  Thus, an output voltage Vout represented by the following equation (3) is obtained.

    Vout = {(R3 + R4) / R3} × Vref (3)

  Here, the reference voltage circuit according to each embodiment of the present invention generates the reference voltage Vref. FIG. 20 shows the case where the reference voltage circuit is configured in the first embodiment as shown in the block B. Of course, the reference voltage circuit in the block B can be replaced by the reference voltage circuits according to the second to tenth embodiments.

  INDUSTRIAL APPLICABILITY The present invention can be effectively used in an industrial field in which a reference voltage circuit, which is a power management IC typified by a voltage regulator that supplies power supply voltage, is manufactured and sold.

1,2,3 bias circuit,
Vin power supply voltage Vref reference voltage R, R ₁ , R ₂ resistance M1 first transistor (N-channel enhancement type transistor)
M2 Second transistor (N-channel depletion type transistor)
M3 Third transistor (N-channel depletion type transistor)
M4 Fourth transistor (N-channel depletion type transistor)
M5 Fifth transistor (P-channel enhancement type transistor)
M6 6th transistor (P-channel enhancement type transistor)
M7 7th transistor (N-channel depletion type transistor)

Claims (14)

A first transistor that is an N-channel enhancement type transistor with its own gate connected to its own drain, and an N-channel whose own gate is connected to the gate of the first transistor and to its own source A reference voltage circuit which is connected in series via the drain of the first transistor and generates a reference voltage at the gates of the first transistor and the second transistor. ,
A third transistor, which is an N-channel depletion type transistor, whose own threshold value is larger in absolute value than the threshold value of the second transistor and whose current driving capability is higher than the current driving capability of the second transistor, Connected in series via the drain of the second transistor,
Further, a constant voltage is applied to the gate of the third transistor, and the substrate of the third transistor is connected to the substrate of the first transistor. A reference voltage circuit according to claim 1,
A reference voltage circuit, wherein a bias voltage generated by a bias circuit different from the reference voltage circuit is applied to a gate of the third transistor. A reference voltage circuit according to claim 1,
A reference voltage circuit, wherein the reference voltage is applied to a gate of the third transistor. A reference voltage circuit according to claim 1,
The reference voltage circuit, wherein the source voltage of the first transistor is applied to the gate of the third transistor. The reference voltage circuit according to claim 1, wherein:
A fourth transistor that is an N-channel depletion type transistor connected in series to the third transistor via the drain of the third transistor;
A reference voltage circuit, wherein a predetermined bias voltage is applied to a gate of the fourth transistor from a bias circuit different from the reference voltage circuit. The reference voltage circuit according to claim 5, wherein
The reference voltage circuit, wherein a threshold value of the fourth transistor is the same as a threshold value of the second transistor. The reference voltage circuit according to claim 5, wherein
The reference voltage circuit, wherein a threshold value of the fourth transistor is the same as a threshold value of the third transistor. A current determined by a second transistor, which is an N-channel depletion type transistor having its gate and source connected, is supplied to the first transistor, which is an N-channel enhancement type transistor, through a current mirror circuit, Accordingly, a reference voltage circuit for generating a reference voltage at the gate of the first transistor,
A third transistor, which is an N-channel depletion type transistor, whose own threshold value is larger in absolute value than the threshold value of the second transistor and whose current driving capability is higher than the current driving capability of the second transistor, Connected in series via the drain of the second transistor and connected to the current mirror circuit via its own drain;
Further, a constant voltage is applied to the gate of the third transistor, and the substrate of the third transistor is connected to the substrate of the first transistor. A reference voltage circuit according to claim 8, comprising:
A reference voltage circuit, wherein a bias voltage generated by a bias circuit different from the reference voltage circuit is applied to a gate of the third transistor. A reference voltage circuit according to claim 8, comprising:
A reference voltage circuit, wherein the reference voltage is applied to a gate of the third transistor. A reference voltage circuit according to claim 8, comprising:
The reference voltage circuit, wherein the source voltage of the first transistor is applied to the gate of the third transistor. The reference voltage circuit according to any one of claims 8 to 11,
A fourth transistor which is an N-channel depletion type transistor connected in series to the third transistor via the drain of the third transistor and connected to the current mirror circuit via its own drain; And
A reference voltage circuit, wherein a predetermined bias voltage is applied to a gate of the fourth transistor from a bias circuit different from the reference voltage circuit. The reference voltage circuit according to claim 12, wherein
The reference voltage circuit, wherein a threshold value of the fourth transistor is the same as a threshold value of the second transistor. The reference voltage circuit according to claim 12, wherein
The reference voltage circuit, wherein a threshold value of the fourth transistor is the same as a threshold value of the third transistor.

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