JP2008182334A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for compensating for a current error caused by a source voltage variation for a semiconductor integrated circuit device including a constant current circuit. <P>SOLUTION: The semiconductor integrated circuit device includes the constant current circuit composed of a current mirror circuit, a current compensating circuit 101 which compensates for an error current of the constant current circuit, and a ring oscillator 102. Then the current compensating circuit 101 operates by combining a saturation area wherein a drain current value of a transistor is small with a linear area. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique for compensating for a current error of a constant current circuit caused by power supply voltage fluctuation.

  As a technique studied by the present inventor, for example, the following technique is conceivable in a semiconductor integrated circuit device including a constant current circuit.

  In a semiconductor integrated circuit device, the semiconductor manufacturing process is also miniaturized as the digital circuit speeds up. For example, the minimum processing dimension is becoming finer from 0.15 μm to 0.13 μm and then to 90 nm.

  Even in an analog / digital mixed semiconductor integrated circuit device, since a circuit is formed on the same wafer, it is necessary to apply a miniaturization process such as a 90 nm process to the analog circuit.

  By the way, as a result of examination of the technology of the semiconductor integrated circuit device as described above by the present inventors, the following has been clarified.

  For example, in the 90 nm process, the power supply voltage of the semiconductor integrated circuit is about 1.0V. Incidentally, in the process of 0.13 μm or more, the power supply voltage was 1.5 V or more. When the power supply voltage is lowered, the constant current characteristic of a constant current circuit using a MOSFET (Metal Oxide Field Effect Transistor) is deteriorated.

  Generally, a current mirror circuit is used for the constant current circuit. Usually, a current mirror circuit is designed using constant current characteristics in the saturation region of a MOSFET.

  FIG. 7 is a circuit diagram showing a basic configuration of the MOSFET, and FIG. 8 is a diagram showing drain current characteristics of the MOSFET by a 90 nm process. In FIG. 7, Ids is a drain current, Vds is a drain voltage, and Vgs is a gate voltage. In FIG. 8, the horizontal axis represents the drain voltage Vds, and the vertical axis represents the drain current Ids. FIG. 8 shows drain current characteristics at each gate voltage Vgs. A region 801 is a saturation region at a certain gate voltage Vgs = Vgs1 [V], and a region 802 is a saturation region at a gate voltage Vgs = Vgs2 [V].

  As can be seen from FIG. 8, in the miniaturization process (90 nm process), when the drain current Ids increases, the constant current property in the saturation region of the MOSFET deteriorates (for example, the region 801). This is due to the short channel effect and cannot be avoided in the miniaturization process.

  FIG. 9 is a circuit diagram showing a basic configuration of a current mirror circuit using a MOSFET.

  If the sizes of the MOSFET 901 and the MOSFET 902 are the same, the drain current Ids_1 flowing through the MOSFET 901 is usually equal to the drain current Ids_2 flowing through the MOSFET 902 (Ids_1 = Ids_2).

  However, when the miniaturization process is used, when the drain voltage Vds varies, the drain current Ids_2 also changes. That is, it does not become a constant current source.

  FIG. 10 is a circuit diagram showing a basic configuration of the cascade current mirror circuit.

  The circuit shown in FIG. 10 is obtained by cascading a current mirror circuit composed of MOSFETs 1001 and 1002 upstream of the current mirror circuit shown in FIG. With such a circuit configuration, the fluctuation amount of the drain voltage Vds of the second-stage MOSFET 902 can be reduced, so that the constant current property is improved. However, since the power supply voltage is only 1 V in the miniaturization process, in reality, it is impossible to stack two stages of MOSFETs on the current mirror circuit, and this method cannot be applied.

  FIG. 11 is a circuit diagram showing a configuration of an oscillator using a ring oscillator.

  The oscillation circuit shown in FIG. 11 includes a constant current circuit including MOSFETs 1101 to 1103, a ring oscillator 1105 including a plurality of stages of delay amplifiers 1104, and the like. The MOSFET 1101 is a transistor that adjusts the control current If for controlling the oscillation frequency. A current mirror circuit 1106 is configured by the MOSFET 1102 and a plurality of MOSFETs 1103 corresponding to the number of stages of the ring oscillator 1105.

  In the case of the miniaturization process, since the power supply voltage is 1.0 V, there is no overhead. Therefore, when the power supply voltage fluctuates, the drain voltage Vds of the MOSFET 1103 changes as it is. Accordingly, the current flowing through ring oscillator 1105 varies.

  When the current value of the current flowing into the ring oscillator 1105 changes due to the noise component of the power supply voltage, the oscillation frequency varies and becomes frequency noise (jitter). In order to solve this problem, the present inventor studied a circuit that compensates for this current fluctuation.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of compensating for a current error due to power supply voltage fluctuation in a semiconductor integrated circuit device including a constant current circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a semiconductor integrated circuit device according to an embodiment of the present invention includes a constant current circuit using a current mirror circuit and a current compensation circuit that compensates for an error current of the constant current circuit. The current compensation circuit operates by combining a saturation region where the drain current value of the transistor is small and a non-saturation region of a linear region.

  According to one embodiment of the present invention, there is provided a semiconductor integrated circuit device that compensates for an error current of a constant current circuit caused by power supply voltage fluctuation.

  According to an embodiment of the present invention, in a semiconductor integrated circuit device including a constant current circuit, it is possible to compensate for a current error due to power supply voltage fluctuation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

  First, an example of the configuration of the semiconductor integrated circuit device according to the present embodiment will be described with reference to FIG. The semiconductor integrated circuit device of the present embodiment is, for example, an oscillator (VCO or the like) that can control the frequency by adjusting the control current, and is formed on one semiconductor chip by a well-known semiconductor manufacturing technique. It is formed. This semiconductor integrated circuit device includes, for example, a constant current circuit using a current mirror circuit, a current compensation circuit 101 that compensates for an error current of the constant current circuit, and a ring oscillator (oscillation circuit) whose frequency is controlled by the current value of the constant current circuit. ) 102 and the like. The power supply voltage of this semiconductor integrated circuit device is as low as about 1.0 V, and the lower limit value of the operation guarantee power supply voltage is 1.2 V or less. In the following description, the power supply voltage is described as 1.0 V as an example.

  The ring oscillator 102 includes a plurality of stages of delay amplifiers DL1 to DL3. In FIG. 1, the number of stages of the delay amplifier is three as an example, but the number of stages may be any number. The output signal of the final stage delay amplifier DL3 is inverted and input to the first stage delay amplifier DL1. The delay time of each stage of the delay amplifier is determined by the value of the current flowing from the constant current circuit. As the current value increases, the delay time of the delay amplifiers DL1 to DL3 decreases, and the frequency of the ring oscillator 102 increases. Conversely, when the current value decreases, the delay time of the delay amplifiers DL1 to DL3 increases, and the frequency of the ring oscillator 102 decreases. The current value of the constant current circuit is controlled by a control current If flowing through the transistor NT1.

The constant current circuit is composed of, for example, transistors PT1 to 7, NT1 and 2 and the like. A current mirror circuit is composed of transistors NT1 and NT2 having the same size, and a current mirror circuit is composed of transistors PT1 to PT4 having the same size. Further, a current mirror circuit is configured by the transistors PT11 and PT5 to 7 having the same size. Note that in this specification, the size of a transistor refers to the ratio (W / L) of the gate width (W) to the gate length (L) of the transistor, and is a coefficient of the mutual conductance (g _m ) of the transistor.

  The transistors PT1 to PT11 are p-channel MOSFETs (field effect transistors) and the transistors NT1 to NT9 are n-channel MOSFETs (field effect transistors), but may be transistors such as MISFETs and JFETs.

  The current compensation circuit 101 includes, for example, transistors PT8 to 11, NT3 to 9 and the like. Transistors PT8 to 10 constitute a current mirror circuit. The size of the transistor NT3 is 1/10 of the transistors NT1 and NT2, and when the drain current of the transistor NT1 is a (= If), the drain current of the transistor NT3 is a / 10. Further, since the transistors NT6 and NT7 have the same size and constitute a current mirror circuit, the drain currents of the transistors are the same. The size of the transistor NT9 is 10 times that of the transistor NT8, and the drain current of the transistor NT9 is 10 times that of the transistor NT8. The transistors NT4 and NT5 constitute a MOS die auto, and are for reducing the drain voltage of the transistor NT6 so that the transistor NT6 operates in a linear region. Although resistors may be used instead of the transistors NT4 and NT5, the use of MOSFETs is more resistant to process variations. Transistor NT6 is designed so that its current fluctuation is 1/10 of the current fluctuation of transistors PT2 to PT4. In this embodiment, as an example, the ratio of the current values is 1/10. However, the present invention is not limited to this, and other values such as 1/5 may be used. The same applies to the size of the transistor.

  Next, with reference to FIGS. 2 to 6, a mechanism for compensating for a current error generated in the constant current circuit due to power supply voltage fluctuation will be described with respect to the operation of the current compensation circuit 101.

  FIG. 2 is a simplified diagram of the configuration of the semiconductor integrated circuit device (oscillator) when the current compensation circuit 101 is not provided.

  First, as a precondition, in order to oscillate an oscillator at high speed and obtain a high frequency, it is necessary to drive the delay amplifiers DL1 to DL3 at high speed. A certain amount of current is required to drive the delay amplifiers DL1 to DL3 at high speed. That is, it is necessary to increase the size of the current source transistors PT2 to PT4. Further, since the load capacitance of the transistors PT2 to 4 hinders the improvement of the frequency, it is desired to reduce the gate length (L) of the transistors PT2 to PT4. Therefore, a miniaturization process is used. However, if the miniaturization process is used, the following problems occur.

  That is, since the power supply voltage Vdd is as low as 1.0 V, the drain voltage Vds of each transistor is about 0.3 V. However, when noise is mixed in the power supply, the drain voltage Vds1 of the transistors PT2 to PT4 varies. Due to the fluctuation of Vds1, the current flowing through the delay amplifiers DL1 to DL3 changes, resulting in frequency noise (jitter).

  In order to solve the above problems, attention is paid to the fact that when the drain current of the transistor is reduced, the current value is stable in the saturation region even when Vds = 0.3V.

  3 to 5 are diagrams showing drain current characteristics of the transistors used in the semiconductor integrated circuit device of the present embodiment. Each curve is obtained by changing the transistor size. Since the drain voltage Vds1 of the transistors PT2 to PT4 is about 0.3 V, the saturation region 301 cannot be used as shown in FIG. This is because when the drain voltage Vds varies around the drain voltage Vds = 0.3 V, the drain current Ids also varies (operating point A).

  As shown in FIG. 4, when the drain voltage Vds is reduced (for example, 1/10), the drain current Ids is stable in the saturation region 401 even when Vds = 0.3 V (operation point B). Furthermore, when the drain voltage Vds is lowered with the same transistor size, the transistor operates in the linear region 402 (operation point C).

  The current compensation circuit 101 in the semiconductor integrated circuit device (oscillator) according to the present embodiment creates a compensation current by properly using a linear region (non-saturated region) and a saturated region of the drain current characteristics of the transistor.

  Therefore, as shown in FIG. 5, the following three operating points are considered.

  That is, the operating point A is an operating point where the drain size Ids can be sufficiently obtained because the transistor size is sufficiently large, but there is a current variation due to the drain voltage Vds. The operating point B is an operating point where the drain current Ids decreases because the transistor size is small, but there is almost no current fluctuation due to the drain current Vds in the saturation region. The operating point C is an operating point designed so that the drain current Ids is small and is intentionally in the linear region because the transistor size is small.

  6A to 6E are explanatory diagrams showing the operation of the current compensation circuit 101 in the semiconductor integrated circuit device (oscillator) according to the present embodiment. In each figure, the horizontal axis represents the drain voltage Vds of the transistor, and the vertical axis represents the drain current Ids.

  FIG. 6A shows drain current characteristics at the operating point A. FIG. Let a be the current value of the control current If when there is no fluctuation in the power supply voltage Vdd. When the power supply voltage Vdd changes and the drain voltage Vds changes, the drain current Ids changes. The amount of fluctuation of the drain current Ids at the operating point A is b. The transistors PT2 to PT4 operate at the operating point A. Therefore, the drain currents of the transistors PT2 to PT4 when the power supply voltage fluctuates are a−b.

  FIG. 6B shows drain current characteristics at the operating point B. At the operating point B, even if the drain voltage changes, the drain current does not fluctuate. However, since the transistor size is 1/10, the drain current value is small. Transistors NT3, NT8, PT5-7, and PT10 operate at an operating point B. Therefore, the drain currents of the transistors NT3 and PT10 when the power supply voltage fluctuates are a / 10 and are stable.

  FIG. 6C shows drain current characteristics at the operating point C. FIG. Since the operating point C is a linear region, when the drain voltage changes, the drain current also changes. At this time, the drain current fluctuation is designed to be 1/10 of the operating point A at the operating point C. That is, the transistor NT6 is designed so that the fluctuation amount of the drain current is b / 10. Due to the transistors NT4 and NT5 operating as MOS diodes, the drain voltage of the transistor NT6 becomes lower than the drain voltage of the transistor NT3. Therefore, since the transistor NT6 operates at the operating point C, the drain current of the transistor NT6 when the power supply voltage fluctuates is a / 10-b / 10. Since the transistors NT6 and NT7 are current mirrors, the drain current of the transistor NT7 is also a / 10-b / 10.

  Since the drain current of the transistor PT10 is a / 10, the drain current of the transistor NT8 is a / 10− (a / 10−b / 10) = b / 10. Since the size of the transistor NT9 is 10 times the size of the transistor NT8, the drain current of the transistor NT9 is b. This state is shown in FIG.

  Then, as shown in FIG. 6E, by adding the drain current b of the transistors PT5 to PT7 to the drain current (ab) of the transistors PT2 to PT4, the current flowing through the delay amplifiers DL1 to DL3 is a and Become.

  Therefore, the difference when the power supply voltage Vdd moves is as follows.

When there is no current compensation circuit 101: ab
When there is a current compensation circuit 101: a−b + ((a / 10) − (a / 10−b / 10)) × 10 = a
In the above description, the ratio of the drain current in each transistor is 1/10. However, the ratio is not limited to this, and other ratios may be used.

  Therefore, according to the semiconductor integrated circuit device of the present embodiment, the current error of the constant current circuit when the power supply voltage fluctuates is compensated by the operation of the current compensation circuit 101. In the oscillator, fluctuations in the oscillation circuit frequency and frequency noise due to fluctuations in the power supply voltage are reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the oscillator has been described as the semiconductor integrated circuit device. However, the present invention is not limited to this and can be applied to other semiconductor integrated circuit devices.

  The present invention has a constant current circuit and is effective for an analog circuit or the like that is inconvenient if current fluctuation occurs due to power supply voltage fluctuation, and is particularly effective for a VCO, a switched capacitor circuit, or the like.

1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. It is the figure which simplified the structure of the semiconductor integrated circuit device (oscillator) in case there is no current compensation circuit. It is a figure which shows the drain current characteristic of the transistor used with the semiconductor integrated circuit device which is one embodiment of this invention. It is a figure which shows the drain current characteristic of the transistor used with the semiconductor integrated circuit device which is one embodiment of this invention. It is a figure which shows the drain current characteristic of the transistor used with the semiconductor integrated circuit device which is one embodiment of this invention. (A)-(e) is explanatory drawing which shows operation | movement of the current compensation circuit in the semiconductor integrated circuit device (oscillator) by one embodiment of this invention. It is a circuit diagram which shows the basic composition of MOSFET. It is a figure which shows the drain current characteristic of MOSFET by a 90 nm process. It is a circuit diagram which shows the basic composition of the current mirror circuit using MOSFET. It is a circuit diagram which shows the basic composition of a cascade current mirror circuit. It is a circuit diagram which shows the structure of the oscillator using a ring oscillator.

Explanation of symbols

101 Current Compensation Circuits 102 and 1105 Ring Oscillators 301 and 401 Saturation Region 402 Linear Region (Non-saturation Region)
801, 802 region 901, 902, 1001, 1002, 1101-1103 MOSFET
1104, DL1-3, delay amplifier 1106, current mirror circuits NT1-9, PT1-11 transistors

Claims (5)

A constant current circuit having a current mirror circuit including a field effect transistor;
A current compensation circuit that compensates for a current error of the constant current circuit caused by power supply voltage fluctuation,
The semiconductor integrated circuit device, wherein the current compensation circuit compensates a current error of the constant current circuit by using a combination of a saturation region and a linear region of drain current characteristics of the field effect transistor. The semiconductor integrated circuit device according to claim 1.
The current compensation circuit includes: a second field effect transistor that operates with a drain current smaller than a drain current of the first field effect transistor in the constant current circuit;
And a third field effect transistor that operates at a drain voltage lower than that of the second field effect transistor. The semiconductor integrated circuit device according to claim 1.
A semiconductor integrated circuit device further comprising an oscillation circuit whose frequency is controlled by a value of a current supplied from the constant current circuit. The semiconductor integrated circuit device according to claim 3.
The semiconductor integrated circuit device, wherein the oscillation circuit is a ring oscillator having a plurality of stages of delay amplifiers. The semiconductor integrated circuit device according to claim 1.
2. A semiconductor integrated circuit device according to claim 1, wherein the lower limit value of the operation guarantee power supply voltage of the constant current circuit and the current compensation circuit is 1.2V or less.

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