JPH06224220A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an offset region of a film transistor excellently in reproducibility by implanting the ions of impurities at a specified angle to the direction vertical to a substrate with energy penetrating a gate electrode. CONSTITUTION:Ions of impurities are implanted at a angle of 30 deg. or over to the direction vertical to a substrate with energy penetrating a gate electrode layer 104. In the place where they pass the gate electrode layer 104, the distribution becomes shallow, and they are distributed in a polycrystalline silicon layer 102. The place where the distribution of impurities becomes shallow can be controlled by changing the condition of ion implantation. Offset can be provided between the gate electrode and the place where distribution of impurities becomes shallow by selecting the proper condition of ion implantation. Hereby, the drive capacity of a film transistor can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device on an insulating amorphous material and its manufacturing method.

[0002]

2. Description of the Related Art Recently, large-sized, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, and three-dimensional ICs.
In order to meet such needs, there is a demand for a technique for forming a high-performance semiconductor element on an insulating amorphous substrate such as glass or quartz or an insulating amorphous material such as SiO 2.

As such a semiconductor device using amorphous silicon or polycrystalline silicon as a device material, good results have been obtained in terms of variations in characteristics of each device and yield. In particular, the one using polycrystalline silicon as the element material has a relatively high movement due to the technique of melting and recrystallization by laser light and the technique of solid-phase growing amorphous silicon to form a polycrystalline silicon film of large grain size. A device having a certain degree can be manufactured relatively easily. Therefore, L
It has become possible to be applied as a switching element or a driving element of a CD or an image sensor.

However, in recent years, high definition liquid crystal panels and S
For application to RAM and the like, there has been a demand for an element having a small off-leakage as well as an on-current and a high breakdown voltage.

As a structure for realizing such characteristics as a MOS transistor, a structure in which an offset is provided on the drain side is known. Conventionally, as a practical method of manufacturing such a structure, the Extended Abstract of the 1992 International Conference on Solid State Devices and Materials (Extended Abstruc).
to of the 1992 Internationala
l Conference on Solid Sta
te Devices and Material
s), pp. 693 and the like, a method is known in which the source / drain regions are ion-implanted while leaving the resist when forming the pattern of the gate electrode, and then the gate electrode is overetched. This method is an excellent method in that the drain offset can be formed by self-alignment with the gate electrode with a small number of steps.

[0006]

On the other hand, the characteristics of the thin film transistor are very sensitive to the magnitude of this offset. If the offset is too small, the leakage current at the off time increases, and if it is too large, the leakage current at the on time increases. The current drops. Therefore, in order to manufacture a thin film transistor having good characteristics, it is necessary to accurately control the offset magnitude. If an offset structure is to be produced using the above method, it is necessary to overetch the gate electrode very uniformly over the entire substrate.
However, in reality, it is difficult to perform overetching uniformly and with good reproducibility over the entire substrate, and a condition for forming a large offset is often used in order to stably suppress the off current. Therefore, there are problems that it is difficult to obtain a sufficient on-state current, it is necessary to increase the element area, and the usable range is limited due to the characteristics. Therefore, an object of the present invention is to solve such a problem and form an offset region of a thin film transistor with good reproducibility.

[0007]

In order to solve the problems described above, a method of manufacturing an insulated gate semiconductor device according to the present invention comprises a polycrystalline semiconductor layer mainly containing silicon including at least a channel region. Forming step, forming a gate insulating film, forming a gate electrode, and implanting impurity ions having an angle of 30 degrees or more with respect to a direction perpendicular to the substrate by energy transmitted through the gate electrode. It is characterized by having a step of performing. Alternatively, at least a step of forming a gate electrode, a step of forming a gate insulating film, a step of forming a polycrystalline semiconductor layer mainly containing silicon including a channel region, and a step of forming an insulating film layer, The method is characterized by including a step of implanting impurity ions having an angle of 30 degrees or more with respect to a direction perpendicular to the substrate by energy transmitted through the gate electrode.

[0008]

FIG. 1 is a process sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 1A shows a polycrystalline silicon layer 10 which becomes an active region of a thin film transistor on an insulating substrate 101.
2, a state in which the gate insulating film 103 and the gate electrode layer 104 are formed is shown.

As the insulating substrate 101, an APC is provided on the surface.
A quartz glass substrate having an NSG layer formed by the VD method (normal pressure CVD method) is used. Alternatively, a silicon substrate having an insulating film formed on its surface can be used as the substrate.

The polycrystalline silicon layer 102 is formed by forming an amorphous silicon film and then performing heat treatment in a nitrogen atmosphere to perform crystallization. The amorphous silicon film is formed by a parallel plate type plasma CVD method using silane as a source gas, the substrate temperature is 180 ° C., the internal pressure is 0.8 Torr. Film formation with
The film thickness is about 1000Å. Then, in a nitrogen atmosphere,
It is polycrystallized by heat treatment at 50 ° C. for 4 hours and 800 ° C. for 1 hour.

The gate insulating film 103 is a polycrystalline silicon layer 1
No. 02 is formed by dry thermal oxidation at 1050 ° C., and the film thickness is about 1000Å.

The gate electrode layer 102 is a polycrystalline silicon film and is formed by the LPCVD method (low pressure CVD method). Silane (SiH4) was used as a reaction gas, and a 2000 Å film was formed at a film forming temperature of 590 ° C. After the film formation, the resistance is reduced by phosphorus (P) diffusion, and the pattern is formed by the photo-etching process. The gate length is about 0.5μ.
m.

FIG. 1B shows a step of forming the impurity-doped layer 106 by obliquely implanting impurity ions.

In the oblique ion implantation, phosphorus is used as the impurity, and the angle is 70 degrees with respect to the direction perpendicular to the substrate.
Ion implantation with a dose amount of 5 × 10 ¹⁴ is performed from two directions perpendicular to the pattern of the gate electrode layer 103 with acceleration energy corresponding to 700 keV.

As shown in FIG. 1B, the gate electrode layer 104
When ion implantation is carried out with high energy so that the gate electrode layer 104 does not pass through, the implanted phosphorus passes through the polycrystalline silicon layer 102 and is distributed in the insulating substrate 101. The distribution becomes shallower at the location passing through 104, and the polycrystalline silicon layer 10
Distributed within 2. The location where the impurity distribution becomes shallow can be controlled by changing the ion implantation conditions. By selecting appropriate ion implantation conditions, an offset can be provided between the gate electrode and the place where the impurity distribution becomes shallow. This offset amount depends on the ion implantation conditions and the film thickness of the gate electrode, and can be formed with extremely good reproducibility. Therefore, by using this offset as the offset on the drain side of the thin film transistor to be manufactured, it is possible to stably manufacture a thin film transistor having good characteristics.

The optimum conditions for the oblique ion implantation are as follows:
Although it depends largely on the gate length and film thickness of the gate electrode layer 104, the film thickness of the gate insulating film 103, and the film thickness of the polycrystalline silicon film 102, a thin film transistor with a longer gate length is preferable when ion implantation is performed at a larger angle. There is a tendency that a thin film transistor having various characteristics can be obtained. The gate length is 1.0 to 0.4 μm, and the gate electrode film thickness is 1000.
When a thin film transistor of ~ 5000Å is manufactured,
Good characteristics are obtained when the ion implantation is performed at an angle of 30 to 75 degrees with respect to the direction perpendicular to the substrate and within the range of acceleration energy +10 to 100 keV capable of passing through the gate electrode layer 104 in the angle direction. Was obtained. In particular, an angle corresponding to the ratio of the gate length and the film thickness of the gate electrode layer 104, that is, tan ⁻¹ (gate length / gate electrode film thickness)
Good results are obtained in the vicinity of the angle corresponding to.

FIG. 1C shows a step of forming source / drain regions of a thin film transistor by ion implantation.

After obliquely implanting the impurity ions, a resist 107 is formed by a photolithography process. Resist 10
The pattern 7 is such that the source of the thin film transistor is formed so that the end of the pattern is located on the side gate electrode layer 104, and the side where the drain is formed is an offset provided between the gate electrode 104 and the impurity-doped region 106. The pattern is provided so as to cover the position. By implanting phosphorus ions using this resist as an implant mask, the source 108 and the drain 109 are provided with an offset region provided only on the drain side of the thin film transistor.
Is formed.

FIG. 1 (d) shows a completed state of the thin film transistor. After the ion implantation for forming the source / drain of the thin film transistor is performed, the resist 107 is peeled off to remove impurities introduced by the ion implantation. After performing heat treatment for activation, the interlayer insulating film 1
05, the contact hole, and the wiring layer 110 in this order.

The heat treatment for activating the impurities is carried out by treating at 700 ° C. for 2 hours in a nitrogen atmosphere, then raising the temperature from that state to 900 ° C. at a rate of 5 ° C./minute, and then in that state for 20 minutes. Is being processed. After the heat treatment at a temperature of 700 ° C. or lower for a relatively long time, the heat treatment at 850 ° C. or higher increases the activation rate of the introduced impurities and the polycrystalline silicon layer 104 disturbed by the ion implantation is formed. The crystallinity can be effectively restored, and the off-state current of the manufactured thin film transistor can be suppressed low.

As a method of forming the interlayer insulating film 105, the atmospheric pressure CVD method is used. Using silane and oxygen as a reaction gas, a 5000 Å film was formed at 480 ° C. After forming the interlayer insulating film 105, annealing is performed at 350 ° C. in an atmosphere containing hydrogen.

After forming the interlayer insulating film 105, plasma treatment is performed in a hydrogen atmosphere to improve the characteristics of the thin film transistor.

The contact hole is CF as a reaction gas.
It is formed by RIE using 4 and hydrogen.
The metal wiring 110 is formed by a sputtering method using an aluminum-silicon-copper target containing silicon in an amount of 1 to 5%. After the metal wiring 110 is formed, annealing at 250 to 300 ° C. is performed to stabilize the contact portion.

In the above-described embodiment, the polycrystalline silicon layer 10 is used.
As a method of forming No. 2, the amorphous silicon film is crystallized by heat treatment at a low temperature for a long time to form a polycrystalline silicon film with a large grain size, thereby improving the characteristics of the thin film transistor. However, the method for manufacturing a semiconductor device of the present invention is particularly effective when combined with such a technique for improving the quality of polycrystalline silicon. It is also effective when high quality is achieved by other methods such as lamp annealing and laser annealing.

FIG. 2 is a process sectional view showing another example of the semiconductor manufacturing method according to the embodiment of the present invention.

FIG. 2A shows a state in which a gate electrode layer 204, a gate insulating film 203, a polycrystalline silicon layer 202 which becomes an active region of a thin film transistor, and an interlayer insulating film layer 205 are formed on an insulating substrate 201. is there.

As the insulating substrate 201, a reduced pressure C is applied to the surface.
A silicon substrate having an NSG film formed by the VD method is used. As the substrate, other substrates such as a quartz substrate and a ceramic substrate having a heat resistance of 900 ° C. or higher can be used.

The gate electrode layer 202 is formed by the low pressure CVD method under the same conditions as the gate electrode 102 shown in FIG. 1 and has a film thickness of about 2000Å. After reducing the resistance by phosphorus diffusion, a pattern is formed by a photoetching process, and the gate length is about 0.5 μm.

The gate insulating film 203 was formed by a low pressure CVD method using silane and oxygen as source gases. Substrate temperature 7
70 ° C., internal pressure 0.8 Torr. The film thickness is about 1000Å.

The polycrystalline silicon layer 202 was formed by forming an amorphous silicon film and then heat treating it in a nitrogen atmosphere to crystallize it. The amorphous silicon film is formed by a low pressure CVD method using disilane (Si2H6) as a source gas.
Substrate temperature 480 ° C., internal pressure 0.6 Torr. The film thickness is about 1000Å. Then, heat treatment is performed at 650 ° C. for 4 hours and at 750 ° C. for 1 hour in a nitrogen atmosphere to polycrystallize.

The interlayer insulating film 205 is formed by the atmospheric pressure CVD method under the same conditions as the interlayer insulating film 105 shown in FIG. 1, and has a film thickness of about 1000Å. FIG. 2B shows a step of forming an impurity-doped layer 206 by obliquely implanting impurity ions.

In the oblique ion implantation, boron (B) is used as the impurity, and the acceleration voltage is 360 keV from two directions perpendicular to the pattern of the gate electrode layer 203 at an angle of 70 degrees with respect to the direction perpendicular to the substrate. 5 doses each
Ion implantation of × 10 ¹⁴ is performed.

As in the case shown in FIG. 1B, an offset can be provided between the gate electrode and the gate electrode by selecting appropriate ion implantation conditions. Regarding the dependency on the implantation condition, although there is a difference in absolute value of the implantation energy, the same tendency as in the case shown in the case of FIG. 1B was observed.

FIG. 2C shows a step of forming source / drain regions of a thin film transistor by ion implantation.

After obliquely implanting the impurity ions, a resist 207 is formed by a photolithography process. Resist 20
In the pattern No. 7, the side of the thin film transistor on which the source is formed is positioned so that the end of the pattern is located on the gate electrode layer side of the step portion of the gate electrode layer 204, and the side on which the drain is formed is doped with the gate electrode 204 and impurities. Area 206
The end of the pattern is provided so as to cover the offset provided between the patterns. Boron difluoride (BF2) ions are implanted using this resist as an implantation mask to form the source 208 and the drain 209 of the thin film transistor in such a manner that an offset region is provided only on the drain side.

FIG. 2D shows a completed state of the thin film transistor. After the ion implantation for forming the source / drain of the thin film transistor is performed, the resist 207 is peeled off and the impurities introduced by the ion implantation are removed. After heat treatment for activation is performed, the contact hole and the wiring layer 210 are formed in this order.

The heat treatment for activating the impurities is carried out by treating at 700 ° C. for 2 hours in a nitrogen atmosphere, then raising the temperature from that state to 850 ° C. at a rate of 5 ° C./min, and treating for 20 minutes. Is going.

The contact hole and the metal wiring layer 210 are formed by the same method as shown in FIG.

In the above-described embodiments, only the method of manufacturing a thin film transistor is described, but all the steps are 90%.
It is configured at a temperature of 0 ° C. or lower, and can be manufactured on a silicon substrate on which other elements are formed. For this reason,
It can also be applied to applications such as SRAM load transistors.

[0041]

As described above, according to the present invention, it is possible to form the drain side offset of the thin film transistor with good reproducibility, and for the application in which it is necessary to keep the leak current at the time of OFF low. The amount of offset can now be minimized. Therefore, it becomes possible to improve the driving capability of the thin film transistor,
It has become possible to reduce the element area and apply it to devices with higher integration.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an example of a manufacturing process of a semiconductor device in an example of the present invention.

FIG. 2 is a process sectional view showing another example of the manufacturing process of the semiconductor device according to the embodiment of the invention.

[Explanation of symbols]

 101, 201 ... Insulating substrate 102, 202 ... Polycrystalline silicon layer 103, 203 ... Gate insulating film 104, 204 ... Gate electrode layer 105, 205 ... Interlayer insulating film 106, 206. ..Impurity-doped regions 107, 207 ... Resists 108, 208 ... Sources 109, 209 ... Drains 110, 210 ... Wiring layers

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 21/265 8617-4M H01L 21/265 V

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor mainly containing silicon, and a polycrystalline semiconductor layer mainly including silicon including at least the channel region. Forming a gate insulating film, forming a gate insulating film, forming a gate electrode, and implanting impurity ions having an angle of 30 degrees or more with respect to a direction perpendicular to the substrate by energy transmitted through the gate electrode. A method of manufacturing a semiconductor device, comprising the step of: 2. A method of manufacturing a semiconductor device in which a channel region of the insulated gate semiconductor device is formed of a polycrystalline semiconductor mainly containing silicon, and at least a step of forming a gate electrode and forming a gate insulating film. Process, a process for forming a polycrystalline semiconductor layer mainly containing silicon including a channel region, a process for forming an insulating film layer, and 30 for a direction perpendicular to the substrate by energy transmitted through the gate electrode.
A method of manufacturing a semiconductor device, comprising a step of implanting impurity ions having an angle of not less than 100 degrees.