JPH06223035A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To omit program size and improve the processing speed of a CPU by performing complex fixed form arithmetic by a hardware circuit. CONSTITUTION:This arithmetic processor is equipped with CPU 2 which sends out a discrimination address and arithmetic data as one address data to an address bus 4 according to a control program, and inputs an arithmetic result sent to a data bus 5 and performs a specific processing and a fixed form arithmetic circuit 3 which detects a discrimination address specifying itself from address data sent out to the address bus 4, inputting part of address data that the discrimination address belongs as an arithmetic data and performs fixed form arithmetic, and outputs the arithmetic result to the data bus 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit having a CPU for executing complicated arithmetic processing, and more particularly to a CPU.
The present invention relates to an arithmetic processing device that causes a hardware circuit to execute a routine arithmetic operation among various kinds of processing executed by the CPU to improve the processing speed of the CPU.

[0002]

2. Description of the Related Art Conventionally, an arithmetic processing unit based on an arithmetic instruction of a CPU or a program processing of an arithmetic processor has been widely used for executing a routine operation. As a routine operation executed by this type of operation processing device, for example, there is an error detection formula using a cyclic redundancy code, and CRC-16 will be described here as an example.

FIG. 4 is a flow chart when the arithmetic processing unit executes arithmetic processing of CRC-16 by a program. In the arithmetic processing of this CRC-16, C
The PU sets the current value to 0FFFFH (ST1). It should be noted that the processing of the following steps 3 to 9 is looped by the number of bytes of new data for which CRC-16 calculation is performed (ST
2).

Here, the CPU takes the exclusive OR of the current value and the new data and sets the result as the new current value (ST3). In addition, the processing of the following steps 5 to 8
Loop once (ST4).

That is, the CPU shifts the new current value to the right by 1 bit (ST5), and determines whether or not the overflowed bit is 1 (ST6). Further, the CPU exclusively ORs 0A001H with the new current value before shift (ST7), and determines whether or not the processing of steps 5 to 7 has been looped eight times (ST8), and loops. If not, the process returns to step 5, and when looped, the process proceeds to step 9.

In this step 9, the CPU makes the CRC-
It is determined whether or not the processing of steps 3 to 8 has been looped by the number of bytes of new data for which calculation of 16 is performed (ST9),
When not looping, the process returns to step 3, and when looping, the process ends.

[0007]

However, in the arithmetic processing device as described above, it is necessary to execute a plurality of commands in the program when performing a complicated routine operation such as CRC-16. There is a problem that it takes time. In addition, a program for executing a complicated operation has a problem that it is difficult to read because of its large size and it is difficult to find an error location when a trouble occurs.

The present invention has been made in consideration of the above circumstances, and provides an arithmetic processing unit capable of omitting a program size and improving the processing speed of a CPU by causing a hardware circuit to perform a complicated routine operation. The purpose is to do.

[0009]

According to the present invention, an identification address and operation data are sent out as one address data on an address bus according to a control program, and an operation result output on the data bus is fetched and predetermined. Detecting the identification address that specifies itself from the address data sent to the CPU and the CPU that executes the processing of
The arithmetic processing device includes a fixed arithmetic circuit that takes in a part of the address data to which the identification address belongs as the arithmetic data, executes the fixed arithmetic operation, and outputs the calculation result on the data bus.

[0010]

Therefore, according to the present invention, by taking the above-mentioned means, the CPU sends out the identification address and the operation data as one address data on the address bus in accordance with the control program. An identification address designating itself is detected from the address data on the bus, a part of the address data to which the identification address belongs is taken in as operation data, and a fixed operation is executed. Is output to.

As a result, in the CPU, the calculation result on the data bus is fetched and processed. Therefore, by causing the hardware to perform a complicated routine calculation, the program size is omitted and the processing speed of the CPU is increased. Can be improved.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a main configuration of an arithmetic processing unit according to an embodiment of the present invention.

In this arithmetic processing unit, a memory for storing a CPU control program, an identification address and arithmetic data, a CPU 2 for executing a predetermined process based on the CPU control program, and an identification address added from the CPU 2. A fixed-form operation circuit 3 for performing a fixed-form operation on the applied operation data is connected via an address bus 4, a data bus 5 and a control bus 6.

Further, the CPU control program stored in the memory 1 is for performing the arithmetic processing of CRC-16 here, and is configured as shown in the flowchart of FIG. Next, the operation of this arithmetic processing unit will be described with reference to FIGS.

Now, the CPU 2 reads the CPU control program stored in the memory 1. This CPU
2 executes the following processing based on the CPU control program.

First, the CPU 2 sets the current value to 0FFF.
Set to FH (ST11). It should be noted that only the number of bytes of new data for which CRC-16 is calculated is calculated in step 13 below.
The processing of 15 is looped (ST12). Then C
PU2 calculates the exclusive OR of the current value and the new data and sets the calculation result as the new current value (ST1
3).

Next, as shown in FIG. 3, the CPU 2 outputs a plurality of calculated data consisting of the calculated new current value and the identification address as one address data to the address bus 4. The identification address set in the upper bit of the address is a specific bit pattern that specifies the area assigned to the routine circuit 3 in the address space area.

Next, the CPU 2 sends a calculation start command to the fixed form calculation circuit 3 via the control bus 6. Upon receiving this operation start command, the routine operation circuit 3 takes in the operation data output on the address bus, performs the routine operation, and sends the obtained operation result to the data bus 5 (ST.
14).

Further, the CPU 2 fetches the operation result on the data bus 5 and determines whether or not the processes of steps 13 and 14 are looped a number of times equal to the number of bytes of new data for which CRC-16 calculation is performed. (ST15). When it is not looped, the process returns to step 13, and when it is looped, the arithmetic processing is ended.

Thereafter, the CPU 2 executes a predetermined process such as a code error countermeasure based on the calculation result of the CRC-16. Further, the CPU 2 sends a clear command to the fixed form arithmetic circuit 3 via the control bus 6.

As described above, according to this embodiment, the CP
U2 reads the identification address and the operation data from the memory 1 based on the control program stored in the memory 1 and sends them to the address bus 4, and the routine circuit 3 fetches the operation data from the address bus 4 to perform the routine operation. Is executed and sent to the data bus 5, and the CPU 2 fetches the operation result from the data bus 5 and processes it.
The processing speed in the CPU can be improved by causing the hardware circuit to perform a complicated routine operation.

In software, a program for processing a complicated operation is unnecessary,
The size can be reduced by that amount, and the small size makes it easy to check the program in case of trouble.
Also, when creating a new program, by omitting the creation of the part that executes complicated routine operations,
The effort of programming can be reduced. In addition,
The program that can be omitted in this embodiment corresponds to the conventional steps 4 to 8.

Further, in this embodiment, when the CPU 2 sends the identification address to the address bus 4, the operation result is obtained from the data bus 5, and the operation of the CRC-16 is performed as if the memory or I / O is accessed. Since the result can be obtained, the program can be easily created.

Further, in this embodiment, since the routine operation of the CRC-16, which is conventionally executed by the program processing of the CPU, is executed by the routine operation circuit 3, the execution processing used by the CPU 2 for the routine operation is not performed. The processing efficiency of the CPU 2 can be improved.

In the above embodiment, the case where the fixed form operation circuit 3 executes the CRC-16 fixed form operation has been described. However, the present invention is not limited to this, and the fixed form operation circuit 3 may execute another fixed form operation. The same effects can be obtained by implementing the present invention in the same manner.

In the above embodiment, the case where there are a plurality of pieces of operation data has been described. However, the present invention is not limited to this, and the same effect can be obtained by implementing the present invention in the same manner even if there is only one piece of operation data. You can

In the above embodiment, the case where the CPU 2 executes the code error countermeasure processing based on the calculation result has been described, but the present invention is not limited to this, and the CPU 2 stores the calculation result in the memory 1, and Even if the storage-processed calculation result is used as new calculation data, the present invention can be similarly implemented and the same effect can be obtained.

Further, in the above embodiment, the case where one memory and the fixed operation circuit 3 are used has been described, but the present invention is not limited to this, and the present invention can be applied to a configuration including a plurality of memories 1 and the fixed operation circuit 3. The same effect can be obtained by carrying out similarly.

Further, in the above embodiment, the case where only the identification address of the fixed form arithmetic circuit 3 is used has been described, but the present invention is not limited to this, and the identification addresses of the fixed form arithmetic circuit 3 and the memory 1 are used, and via the control bus 6. Even if the chip selector command is applied to the fixed form arithmetic circuit 3 or the memory 1 to perform the bank switching for the fixed form arithmetic circuit 3 and the memory 1, the present invention can be implemented in the same manner and the same effect can be obtained. it can.

In the above embodiment, the case where the identification address is used has been described. However, the identification address is not limited to this, and the chip selector command is applied to the fixed form arithmetic circuit 3 or the memory 1 via the control bus 6. Even if the bank switching is executed for the fixed form arithmetic circuit 3 and the memory 1, the same effect as the present invention can be obtained. In addition, the present invention can be modified in various ways without departing from the scope of the invention.

[0031]

As described above, according to the present invention, C
The PU sends the identification address and the operation data to the address bus according to the control program, the fixed form operation circuit takes in the sent operation data based on the identification address on the address bus, executes the fixed form operation, and outputs the operation result. Is sent to the data bus, and the CPU fetches and processes the calculation result on the data bus. Therefore, by causing the hardware circuit to perform a complicated routine calculation, the program size is omitted and the CPU processing is performed. An arithmetic processing unit that can improve speed can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of an arithmetic processing circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the configuration of a CPU control program in the embodiment.

FIG. 3 is a schematic diagram showing a format of an identification address and operation data in the embodiment.

FIG. 4 is a flowchart showing the configuration of a conventional CPU control program.

[Explanation of symbols]

1 ... Memory, 2 ... CPU, 3 ... Fixed arithmetic circuit, 4 ... Address bus, 5 ... Data bus, 6 ... Control bus.

Claims (1)

[Claims] 1. A CPU that sends an identification address and operation data as one address data on an address bus according to a control program, and that takes in an operation result output on the data bus and executes a predetermined process. An identification address designating itself is detected from the address data sent on the address bus, a part of the address data to which the identification address belongs is fetched as the operation data, a routine operation is executed, and the operation result is An arithmetic processing device comprising: a fixed-form arithmetic circuit for outputting on a data bus.