JPH0622231B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device with an improved lift-off process using a resist pattern as a spacer.

[Technical background of the invention and its problems]

Conventionally, in the manufacturing process of a semiconductor device, the following lift-off method has been adopted to form a wiring of a refractory metal or the like on a semiconductor substrate. First, a resist pattern is formed on a semiconductor substrate by photolithography. Subsequently, after depositing a refractory metal film on the entire surface including the resist pattern as a spacer, the resist pattern is removed with an organic solvent, and the refractory metal film on the resist pattern is lifted off to form a wiring having a desired shape. Form.

However, when the heat resistance of the resist pattern 2 as a spacer formed on the semiconductor substrate 1 is low as shown in FIG. 2A in the above wiring formation, as shown in FIG. When the refractory metal film 3 is deposited on the entire surface including the resist pattern 2, the resist pattern 2 sags due to the heat during the deposition, and the portion where the wiring between the patterns is to be formed is filled with the resist pattern. There was a problem that the target wiring could not be formed even if 2 was removed.

For this reason, using novolac resist,
After the exposure and development, before the post-baking, the entire surface of the resist pattern is irradiated with deep ultraviolet light (DeepUV) to generate unreacted naphthoquinonediazide polymer to improve the heat resistance of the resist pattern and adhere to the substrate. In order to improve the property, the spacer is modified to a state suitable for the spacer of the lift-off method.

The above-mentioned method is suitable when a novolac type resist is used. However, polymethylene sopenyl ketone (PMIPIC) other than the resist
Resists that are sensitive to far-ultraviolet light such as polymethylmethacrylate (PMMA) do not show the effect of the above treatment,
On the contrary, the heat resistance tends to deteriorate. In particular, the resist sensitive to far-ultraviolet light is suitable for forming a fine pattern, but since the heat resistance is very poor, the emergence of a heat-resistant modification method other than irradiation with the far-ultraviolet light is desired. .

[Object of the Invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that enables formation of a resist pattern having excellent heat resistance and is applied to a spacer in a lift-off process to achieve highly accurate electrode wiring formation and the like.

[Outline of Invention]

The present invention comprises the steps of forming a resist layer on a semiconductor substrate, exposing and developing the resist layer to form a resist pattern, and performing reactive ion etching in a gas containing a carbon source and hydrogen to form the resist pattern. Depositing a polymer layer on the resist pattern, depositing a metal film on the substrate including the resist pattern on which the polymer layer is deposited, removing the resist pattern with an organic solvent, and removing the metal on the polymer layer. And a step of forming metal wiring by lifting off the film.

According to the present invention, as described above, it is possible to form a resist pattern having excellent heat resistance and obtain a semiconductor device that achieves highly accurate electrode wiring formation and the like by applying it to a spacer in a lift-off process. it can.

Examples of the resist include polymethylisopenyl ketone (PMIPIC) and its derivatives, polymethyl methacrylate (PMMA) and its derivatives, and the like, which are sensitive to far-ultraviolet light.

In forming the polymer layer on the resist pattern by the reactive ion etching, when a mixed gas of CF ₄ + H ₂ is used, a method of increasing the mixing ratio of H ₂ gas or increasing the pressure is adopted. obtain. By such a method, a polymer layer of H ₂ is formed on the resist pattern. Specifically, when using a reactive ion etching apparatus, power 250 W, pressure 3.0
Pa _{above, CF 4 5~10sccm, H 2 20~30sccm} ,
By setting the etching time to 5 to 10 min, the fine pattern is not deformed on the resist pattern,
A polymer layer can be formed.

Example of Invention

Hereinafter, an example in which the present invention is applied to the wiring formation of a semiconductor device will be described in detail with reference to FIGS.

First, on the silicon substrate 11, polymethyl isopenyl ketone (trade name: OD manufactured by Tokyo Ohka Co., Ltd.) as a positive resist.
UR-1014) was applied to a thickness of 1 μm, and exposed to deep ultraviolet light and developed to form a resist pattern 12 (FIG. 1A). Subsequently, the silicon substrate was set in the chamber of the reactive ion etching apparatus, and the power was 250 W, the pressure was ₄ Pa, the CF _{4 was} 7 sccm, and the H _{2 was} H _2.
By etching for 10 minutes under the condition of 25 sccm, a polymer layer 13 having a thickness of 1000 Å was formed on the resist pattern 12 (shown in FIG. 2B).

Then, Au film 14 ₍₁₄ 1 having a thickness of 5000Å on the entire surface,
14 ₂ ) and a Ti film 15 (15 ₁ , 1) having a thickness of 1000 Å
5 ₂₎ were successively vapor-deposited. At this time, as shown in FIG. 7C, the resist pattern 12 is maintained in the shape before vapor deposition of the Au film 14 and the like without the sagging due to the polymer layer 13 on the resist pattern 12 and the resist pattern 12 and the like. It is separated into the Au film 14 ₂ and the Si film 15 ₂ of the Au film 14 ₁ and the Si film 15 ₁ and the polymer layer 3 on the substrate 11 by the step. Subsequently, the resist pattern 12 and the polymer layer 13 are dissolved and removed with acetone, and the polymer layer 1 is removed.
3 on and lifted off the Au film 14 ₂ and the Si film 15 ₂ forming the Au film 14 ₁ and the Si film 15 bilayer electrode 16 of the structure comprising _one over the substrate 11 (the (d) of FIG shown).

According to the present invention, however, the polymer layer 13 is formed on the surface of the resist pattern 12 having improved heat resistance to serve as a spacer for lift-off.
The deformation and sagging of the spacer at the time of vapor deposition of No. 5 can be suppressed, and the electrode 16 with high precision can be formed.

Although the Au / Ti two-layer film is used as the electrode wiring material in the above-described embodiment, the high-precision electrode wiring can be similarly formed by using another refractory metal such as Mo, Pt, or Ta.

In the above embodiment, the example in which the resist pattern having the polymer layer is used as the spacer for lift-off is described, but the etching for forming the electrode wiring by utilizing the excellent heat resistance and etching resistance of the polymer layer is described. It may be used as a mask.

〔The invention's effect〕

As described above in detail, according to the present invention, it is possible to form a resist pattern having excellent heat resistance, and to apply it to a spacer in the lift-off process to achieve a highly accurate electrode wiring formation method of a semiconductor device. Can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (d) are sectional views showing a process of forming an electrode by a lift-off method according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are conventional methods. It is sectional drawing for demonstrating the problem in a lift-off process. 11 ... Silicon substrate, 12 ... Resist pattern, 1
3 ... Polymer layer, 14 (14 ₁ , 14 ₂ ) ... Au
Membrane, 15 (15 ₁ , 15 ₂ ) ... Ti membrane, 16 ... Electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-58-170014 (JP, A) JP-A-58-68930 (JP, A) JP-A-59-121937 (JP, A)

Claims (1)

[Claims] 1. A step of forming a resist layer on a semiconductor substrate, a step of exposing and developing the resist layer to form a resist pattern, and a step of reactive ion etching in a gas containing a carbon source and hydrogen. Depositing a polymer layer on the resist pattern, depositing a metal film on a substrate including the resist pattern on which the polymer layer is deposited, and removing the resist pattern with an organic solvent on the polymer layer And a step of forming metal wiring by lifting off the metal film.