JPH06217556A - Method and circuit for limiting current of inverter - Google Patents

Abstract

PURPOSE:To provide a method and circuit for limiting currents of inverters by which no transistor is damaged and a highly reliable inverter can be obtained. CONSTITUTION:In the method, the operation of an inverter 11 is stopped when such a state that the load current to the inverter is larger than a prescribed value continues for more than a prescribed period of time. Therefore, a comparator 3 detects the state where the load current is larger than the prescribed value and the operation of the inverter 11 is stopped when the load current flowing to the inverter 11 becomes larger than the prescribed value within one AC cycle after a prescribed period of time from the detecting signal of the comparator 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current limiting method for an inverter and its circuit, and more particularly to a safe current limiting method for an inverter without damaging a semiconductor element constituting the inverter. And its circuit.

[0002]

2. Description of the Related Art Inverters are widely used to generate AC power supplies for driving AC equipment used in industrial applications such as static thyristor leonards. In order to limit the overload current, the conventional inverter has a function of detecting the load current of the inverter and limiting the output of the inverter when the detected current exceeds a predetermined value. In such an inverter current limiting circuit, as shown in FIG. 5, the output current value 1 of the inverter 11 is detected by the current transformer 13 for an instrument, and the detected value 1 is converted into a direct current by the rectifier circuit 2. The voltage is converted into a voltage, and the DC voltage is compared with the comparison voltage to a predetermined voltage value 1
It is supplied to the comparator 3 set to 4. Predetermined voltage value 1
When the inverter output current value converted into the DC voltage is larger than that of 4, the output is obtained from the comparator 3. The output signal of the gate signal generating function 9 for controlling the transistor bridge constituting the inverter is manipulated by the output signal of the comparator 3 in the gate circuit 18 to form the transistor bridge constituting each inverter 11. Is supplied to each gate of the transistor bridge which constitutes the inverter 11 via the driver 10 which outputs each gate signal. Therefore, the output current of the inverter 3 is limited by the output of the comparator 3. In addition,
In the figure, 12 indicates a load device driven by the inverter, and 15 indicates a ground level as a reference of the predetermined voltage 14.

[0003]

By the way, according to the current limiting means of the conventional inverter described above, when the load current becomes larger than the predetermined value, the value of the current flowing from the inverter to the load by the action of the comparator. Is restricted. Therefore, the value of the current flowing from the inverter to the load becomes less than a predetermined value, and the comparator output is restored. If Inver
If the cause of the increase in the current flowing from the inverter to the load is not eliminated, after the comparator output is restored, the current value output from the comparator and flowing from the inverter to the load is limited. Due to the above-mentioned function, the current value flowing through the load is limited to a predetermined value or less. However, due to the intermittent operation of the comparator function described above, a ripple current intermittently flows in the transistor forming the inverter near the upper limit value of the limited current. The ripple current flowing through the transistor described above promotes heat generation of the transistor. Therefore, there is a problem that the transistor forming the inverter is damaged due to such heat generation when the current limiting operation is performed for a long time. The present invention solves the above-mentioned problems (problems), and even if a load current excess state such as a load circuit short-circuit accident continues for a long time, there is no fear of damage to semiconductor elements such as transistors forming an inverter, and safety. It is an object of the present invention to provide an inverter current limiting method capable of providing a high inverter and a circuit thereof.

[0004]

In order to solve the above-mentioned problems, the present invention is directed to a situation in which a load current value exceeds a preset predetermined value for a period of time longer than a preset preset time. , In the current limiting method of the inverter in which the operation of the inverter is stopped, the situation in which the load current flowing through the inverter exceeds a predetermined value is detected by the comparator function, and Also, when the load current flowing through the inverter becomes larger than a predetermined value at least during the time of one AC cycle generated by the inverter after the generation and output of the signal delayed by the predetermined time, the inverter is operated after the detection. I tried to stop. In this case, the current limiting circuit of the inverter is a comparator that detects a situation where the load current flowing through the inverter is larger than a predetermined value.
Timer function for generating a signal delayed by a predetermined time from the detection output signal by the timer function, a function for generating a gate signal having a time width of one AC cycle generated by the inverter after outputting the timer function, and a function for generating the gate signal. A gate function for passing the comparator output signal by a gate signal, and the gate function
It is possible to provide a latch function which is activated by a switch function passing signal, and to stop the operation function of the inverter by the output of the latch function.

[0005]

In the current limiting method for the inverter and the circuit thereof according to the present invention, the current is flown by a predetermined value or more depending on the load condition of the inverter because it is constructed as described above to obtain the desired function. Whenever there is a situation,
The operation of the inverter is stopped, and therefore the semiconductor element forming the inverter is not damaged due to heat generation or the like.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an inverter current limiting method and its circuit according to the present invention will be described in detail with reference to FIGS. Embodiment 1 FIG. 1 shows a circuit of an embodiment in which the current limiting method for an inverter according to the present invention is applied to the circuit of FIG. 5 described in the prior art. The reference numerals of the element circuits shown in FIG. 1 which are common to the element circuits shown in FIG. 5 are designated by the same reference numerals. Further, since the present invention can be implemented by software processing of a computer or by a circuit configured of various parts, main element devices are described by expressions called functions. In FIG. 1, reference numeral 1 denotes the load current supplied from the inverter 11 to the predetermined load device 12 detected by the instrument current transformer 13. The load current 1 is converted by the full-wave rectifier circuit 2 into a DC voltage proportional to the magnitude of the load current 1. The output of the full-wave rectifier circuit 2 is supplied to the comparator 3. In the comparator 3, it is compared with the reference voltage 14, and the output voltage of the full-wave rectifier circuit 2, that is, the inverter 11
When the load current value output from exceeds the specified value,
The signal a is output from the comparator 3. The output signal a of the comparator 3 is input to the AND gate function 8 which will be described in detail later, and is the output signal from the gate signal generating function 9 for controlling each transistor of the transistor bridge which constitutes the inverter 11. A driver 10 having an output function necessary for driving a gate circuit 11g of each transistor that constitutes an inverter of a certain PWM signal, for example.
The driver 10 controls the input to the inverter 11
The normal output current limiting operation of is performed. The above comparator 3
The signal a output from the input terminal is input to the delay function 4 and delayed by a predetermined time set to output the signal b. When the delay function 4 outputs a signal b delayed by a predetermined time, the gate pulse generation function 5 is activated to generate a gate pulse c having a time width of at least one AC cycle generated by the inverter 11.
Is generated and output. The gate pulse c having the output of the gate pulse generating function 5 is inputted to the first AND gate function 6 having two inputs. If there is an output from the comparator 3 during this gate pulse time, the first AND gate function 6 outputs to activate the latch function 7, and a signal d holding a predetermined output state is output. . The latch function output d is a three-input second AND gate together with the output of the comparator 3 described above.
Input to function 8. The AND gate function 8 has the number of semiconductors forming the inverter 11, for example, the number of bridge-connected transistors forming the inverter.
The gate signal of the transistor, for example, the gate signal output from the gate signal generating function 9 for continuously generating the PWM signal is input. When the output of the comparator 3 and the output of the latch function 7 which are input to the AND gate function 8 are in a normal state, that is, in a high state, for example, the AND gate function 8 opens the gate. Signal generation function 9
The gate signal output from the device is passed through, and the passed signal is supplied to a predetermined gate by the driver 10 having an output function required to drive the gate circuit 11g of each transistor constituting the inverter. Signal to drive each of the above transistors. The AC power output from the inverter 11 controlled by the output of the driver 10 is supplied to the load device 12. The AND gate function 8 outputs when the output of the comparator 3 or the latch function 7 functions, that is, when there is an output of either the comparator 3 or the latch function 7, that is, when it becomes a low state, for example. The gate signal output from the gate signal generating function 9 is operated to control or stop the output current of the inverter 11. An instrument current transformer 13 is inserted in the circuit connecting the inverter 11 and the load device 12 to detect the load current 1 of the inverter and input it to the full-wave rectifier circuit 2 as described above. .

The operation of the current limiting method of the inverter in the above circuit configuration will be described with reference to FIG. In FIG. 2, the horizontal axis shows the flow of time, and the vertical axis shows the waveform of each part.
That is, in FIG. 2, load current 1, comparator 3 output signal a, delay function 4 output signal b, gate pulse generation function 5 output c, and latch function output d are shown from the top. In FIG. 2, when the load current 1 exceeds the set value of the comparator 3 at time t1, the comparator
A low-direction output appears from the conventional high state from the gate 3 as shown by a, and the second AND gate function 8 causes the gate to output.
The gate signal output from the gate signal generation function 9 is an inverter.
The inverter 11 is controlled and the load current 1 is limited because the supply to each transistor constituting the inverter 11 is limited. Therefore, the output of the comparator 3 is lost and the inverter 11 returns to normal operation. Therefore,
The output a from the controller 3 also returns to high. Even if the inverter 11 returns to the normal operation, if the condition of the load device 12 is not improved, the load current immediately increases and the comparator 3 is made to function. Therefore, as shown by s of the load current 1 shown in FIG. 2, it pulsates at the peak portion of the alternating current, and the output signal a of the comparator 3 is intermittently pulsed. When the comparator output signal a is output as the signal b by the function of the delay function 4,
At time t2, the gate pulse generation function 5 causes the time width of one cycle of the waveform generated by the inverter 11, that is, a one-shot pulse (gate) which continues from time t2 to t4.
Pulse) c is output. This one-shot pulse c
If there is a comparator output signal a during the output of
This comparator output signal c from the AND gate function 6 of
Is output, and the latch function 7 is latched in a predetermined state. The output signal d of the latch function 7 is converted from the conventional high state to the low state and continuously output. When the output d of the latch function 7 goes low, the second AND gate function 8 is closed, so that the gate signal output from the gate signal generating function 9 is not supplied to the inverter 11. Therefore, the operation of the inverter is stopped, and the current supply to the load device 12 is stopped. When the cause of current increase in the load device is removed by operating the operator and the latch function 7 is reset by a reset function (not shown), the inverter returns to normal operation. Although the delay function 4 is provided in the above description, a timer for a predetermined time may be used instead of the delay function. Further, each of the above-mentioned functions may convert the load current into a predetermined digital code to perform software processing by the computer, and the comparator and the following may be configured by a digital circuit. Alternatively, it may be configured by an analog circuit. The second AND gate function 8 corresponds to the conventional inverter current limiting circuit, and may be appropriately configured so that the output signal of the latch function 7 can be turned on and off. That is, the type of the output signal from the gate signal generating function 9 corresponding to the type of the elements forming the inverter, the conventional current limiting circuit, and the driver circuit corresponding to these circuits are adapted. It suffices to configure the second and gate function. For example, as described above, in the case of PWM or in the case of forming the inverter by a thyristor, digital processing is performed to obtain the gate of the transistor forming the inverter.
An analog processing circuit is formed when analog control is performed on the printer. Each function shown in FIG. 1 may be appropriately combined or separated as long as a predetermined function can be comprehensively exhibited. In the above description, the case where the semiconductor element forming the inverter is a bridge-coupled transistor has been described, but it goes without saying that any inverter can be applied.

Embodiment 2 A case where the above-mentioned function is soft-processed will be described with reference to FIG. 3 showing a flow and FIG. 4 showing a signal change with time similar to FIG. Also in the case of this embodiment, the current value (uppermost stage 1 shown in FIG. 3) supplied from the inverter to the load device is constantly monitored by the comparator function during the inverter operation by the current limiting function similar to the conventional one. is doing. When the monitoring current exceeds the preset reference current value by the comparator function (time t1 in FIG. 4 and the next stage A shown in FIG. 3), the comparator function output activates the conventional current limiting function to operate. (Branch destination 2 shown in FIG. 3). Further, the timer function set to a predetermined time inhibits the comparator output interrupt for the processing function according to the present invention for a predetermined time. That is, the first timer function for delaying the signal input of the comparator function output for the processing function according to the present invention by a predetermined time is activated (the third stage B from the top in FIG. 3). When the timer function times out (time t2 in FIG. 4), a gate signal (time t2) having a time width corresponding to one cycle of the AC frequency of the inverter is generated.
To t4) are activated (the fourth stage from the top in FIG. 3). When the comparator output is input to the processing function according to the present invention during the activation of the gate signal (time t3 in FIG. 4, the fifth step C from the top in FIG. 3), the subsequent operation of the inverter is performed. The latch function for prohibiting is activated (the lowermost stage 4 shown in FIG. 3). That is, until the latch function is activated, the current limiting operation of the inverter is performed when the load current exceeds the set value, and the operation of the inverter is stopped when the latch function is activated, as in the conventional case. After time t3 in FIG. 4, the bottom row 4) shown in FIG. In order to cancel the latch function, the cause of the load current excess is removed by the operator as in the first embodiment, and then the predetermined reset function is operated. In the above description, the latch function is released by the operation of the operator, but it may be automatically released as appropriate in accordance with the condition of the electric power equipment to which the inverter is applied. . Although the second timer function has been described as functioning by the time-up of the first timer function, the second timer function is a timer longer by a predetermined time than the first timer function. The above-mentioned function can also be obtained by prohibiting the interrupt of the comparator function output for the gate function formed by the second timer function at the same time by the first timer function. Other than the above hardware or software configuration, means for realizing the technical idea based on the present invention are possible.

[0009]

As described above, according to the present invention, when the current larger than the predetermined value continuously flows through the inverter load, the operation of the inverter is continuously stopped. Therefore, there is an excellent effect that there is no possibility of damaging the semiconductor element forming the inverter.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a current limiting element function of an inverter for explaining an inverter current limiting method and a circuit thereof according to the present invention.

FIG. 2 is a timing diagram illustrating the operation of the block diagram shown in FIG.

FIG. 3 is a schematic flowchart illustrating a current limiting method of an inverter according to the present invention.

FIG. 4 is a timing diagram illustrating the operation of the flow chart shown in FIG.

FIG. 5 is a schematic block diagram illustrating a current limiting circuit of a conventional inverter.

[Explanation of symbols] 1: Load current 3: Comparator 4: Timer function (delay function) 5: Gate pulse generation function 6: Gate function 7: Latch function 8: Gate function 9: Gate function Signal creation function 11: Inverter 13: Current transformer for instrument

Claims (2)

[Claims] 1. A current limiting method for an inverter, wherein the operation of the inverter is stopped when a situation in which a time load current larger than a preset predetermined time continues to be larger than a preset value continues. When the comparator function detects a situation in which the load current flowing through the inverter exceeds a predetermined value, the timer function generates and outputs a signal delayed by a predetermined time from the detection signal generation, and outputs a signal delayed by a predetermined time. However, when the comparator detection signal is output during at least one AC cycle generated by the inverter after the delayed signal is output, the inverter detection signal is output.
The current limiting method for the inverter is characterized in that the operation of the inverter is stopped. 2. A comparator function for outputting a signal for limiting the output current of the inverter in a current limiting circuit of the inverter when detecting a situation where the load current flowing through the inverter exceeds a predetermined value. A timer function for generating and outputting a signal delayed for a predetermined time after the detection signal is output, and a gate signal generating function having a time width of at least one AC cycle generated by the inverter after the delay time by the timer function, A gate function for passing the comparator output signal by the gate signal after the delay signal output and a latch function activated by the gate function passing signal are provided, and the gate function outputs the latch function. An inverter current limiting circuit characterized in that the operation function of the inverter is stopped.