JPH06216339A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor storage device excellent in reliability wherein the surface condition on the lower surface side of a capacitor lower electrode and the interface with a dielectric film can be prevented form being deteriorated. CONSTITUTION:The title method includes the following steps; a step wherein after a polycrystalline silicon film is formed and doped with impurities, a polycrystalline silicon film fin to serve as the lower electrode 26 of a capacitor is formed, a step of exposing the lower side surface of the polycrystalline silicon film fin, and a step for heat-treating the polycrystalline silicon film fin. Further a step of forming a dielectric film 27 so as to cover the polycrystalline silicon film fin, and a step for forming a capacitor upper electrode 28 so as to cover the dielectric fim 27 are performed in order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to formation of a capacitor electrode of a memory cell of the semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, JP-A-4-30464 and JP-A-2-94.
There is one disclosed in Japanese Patent No. 561. FIG. 3 is a sectional view of a conventional stack type memory cell. As shown in this figure, a capacitor lower electrode 4 having a fin (Fin) extending through a contact hole in an insulating film 3 is connected to the source / drain of a MOS transistor 2 on a semiconductor substrate 1. A dielectric film 5 is formed on the surface of the capacitor lower electrode 4, and a capacitor upper electrode 6 is formed on the dielectric film 5, so that it can be used as a capacitor.

In this stack type memory cell structure, the back surface of the portion where the lower electrode of the capacitor extends in the horizontal direction and the side wall portion of the electrode formed along the contact are not used as the capacitor. FIG. 4 is a cross-sectional view of a memory cell having a conventional fin structure capacitor lower electrode.

As shown in this figure, the source / drain of the MOS transistor 12 on the semiconductor substrate 11 extends so as to project onto the stopper nitride film 14 on the insulating film 13 through the contact hole of the insulating film 13. The capacitor lower electrode 15 having a fin is connected. A dielectric film 16 is formed on the front surface, the side surface, and the back surface of the capacitor lower electrode 15, and a capacitor upper electrode 17 is formed on the dielectric film 16, thus forming a structure that can be used as a capacitor.

The manufacturing process will be described below. FIG. 5 is a diagram showing a manufacturing process of a memory cell having the capacitor lower electrode of the fin structure. As shown in this figure, first, an interlayer insulating film is formed in a first step S1, a stopper nitride film is formed in a second step S2, an oxide film is formed in a third step S3, and a contact is formed in a fourth step S4. Photolithography is performed, contact etching is performed in the fifth step S5, and
A lower electrode film is formed in step S6, impurities are implanted in the seventh step S7, and an eighth step S7 is performed.
8, heat treatment is performed, lower electrode photolithography is performed in the ninth step S9, the lower electrode is etched in the tenth step S10, the sacrificial oxide film is removed in the eleventh step S11, and the dielectric film is removed in the twelfth step S12. And heat treatment (oxidation) is performed in the 13th step S13, an upper electrode is generated in the 14th step S14, impurity diffusion is performed in the 15th step S15, and photolithography of the upper electrode is performed in the 16th step S16. In step S17, the upper electrode is etched.

In the normal stack type memory cell structure shown in FIG. 3, the back surface of the portion where the lower electrode of the capacitor extends in the horizontal direction and the side wall portion of the electrode formed along the contact are not used as the capacitor. As shown in FIG. 4, in a memory cell structure having a fin-structured lower electrode, these portions can also be used as capacitors.

Therefore, the area of the capacitor is increased and the electrostatic capacity is increased, so that the semiconductor memory device with reduced soft error can be obtained. In the memory cell having the capacitor lower electrode of the fin structure described above, as shown in FIG. ) And the sidewall portion of the electrode formed along the contact is used as a capacitor.

Therefore, in order to maintain the reliability of the capacitor (reduction of leak current, dielectric breakdown characteristics over time, etc.), the surface condition and the crystal grain size of these parts on the upper surface side and the lower surface side must be the same. I won't.

[0009]

However, in the conventional method for manufacturing a memory cell having a capacitor lower electrode having a fin structure, when the heat treatment after implanting impurities (hereinafter referred to as the first heat treatment for the lower electrode) is performed, the implant is performed. Impurities diffuse into the entire lower electrode of the capacitor, the upper surface recovers crystallinity from the amorphous state, and grains grow,
As shown in FIG. 6, since the sacrificial oxide film 20 is present in the lower layer on the lower surface side, there are ungrown grains 15a.
As shown in FIG. 3, if these grains grow due to thermal oxidation after the dielectric film 16 is formed, the surface state on the back surface side changes, and irregularities are generated at the interface with the dielectric film 16, which causes the capacitor However, there was a problem that it deteriorated the reliability.

In order to eliminate the above-mentioned problem that the reliability of the capacitor is deteriorated, the present invention can prevent deterioration of the surface condition of the lower surface of the capacitor lower electrode and the deterioration of the interface with the dielectric film. An object is to provide an excellent method for manufacturing a semiconductor memory device.

[0011]

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor memory device, wherein a polycrystalline silicon film is formed, the polycrystalline silicon film is doped with impurities, and a capacitor lower portion is formed. Forming a fin of a polycrystalline silicon film to be an electrode, exposing a lower surface of the fin of the polycrystalline silicon film, applying a heat treatment to the fin of the polycrystalline silicon film, and the polycrystalline silicon film Forming a dielectric film to cover the fins of
The step of forming a capacitor upper electrode so as to cover the dielectric film is sequentially performed.

[0012]

According to the present invention, as described above, the lower electrode of the capacitor is doped with impurities, and after heating, the sacrificial oxide film formed on the lower surface of the lower electrode of the capacitor is removed and then heat treatment is performed. Therefore, it is possible to prevent the deterioration of the surface state of the lower surface of the capacitor lower electrode and the interface with the dielectric film.

[0013]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a main part manufacturing process of a semiconductor memory device showing an embodiment of the present invention, and FIG. 2 is a schematic manufacturing process drawing of a semiconductor memory device showing an embodiment of the present invention. First, regarding the schematic manufacturing process of the semiconductor memory device of the present invention,
This will be described with reference to FIG.

First, the interlayer insulating film 23 is formed in the 21st step S21, the stopper nitride film 24 is formed in the 22nd step S22, the oxide film 25 is formed in the 23rd step S23, and the contact photo film is formed in the 24th step S24. And contact etching is performed in the 25th step S25, and the 26th step S25 is performed.
26, a lower electrode film made of polycrystal is formed at
7 In step S27, impurity implantation is performed and the second
8 In step S28, heat treatment is performed, in 29th step S29, lower electrode photolithography is performed, in 30th step S30, lower electrode 26 is etched [see FIG. 1A], and in 31st step S31, sacrificial oxide film is removed. Perform [see FIG. 1 (b)].

Next, when the lower surface of the lower electrode 26 is exposed, heat treatment is performed in the 32nd step S32 to sufficiently grow polycrystalline grains on the lower surface of the lower electrode 26 (see FIG. 1C). The dielectric film 27 is formed in the 33rd step S33, the heat treatment (oxidation) is performed in the 34th step S34, the upper electrode 28 is formed in the 35th step S35, the impurity diffusion is performed in the 36th step S36, and the 37th step. After photolithography of the upper electrode 28 in S37 and etching of the upper electrode 28 in the 38th step S38 to form the upper electrode 28, a protective film 29 is formed in a 39th step S39.
(Not shown in FIG. 2).

Next, a process of manufacturing a main part of a semiconductor memory device showing an embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 1A, the interlayer insulating film 23 is formed on the source / drain of the MOS transistor 22 of the semiconductor substrate 21,
A stopper nitride film 24, an oxide film 25, and a polycrystalline silicon film are formed on the stopper nitride film 24 and the oxide film 25. Impurities (As) are added to the polycrystalline silicon film.
^{After the +} ) is doped, a capacitor lower electrode 26 forming a fin of the polycrystalline silicon film is formed, and the capacitor lower electrode 26 is connected to the semiconductor substrate 21 via a contact hole.

Then, as shown in FIG. 1B, an oxide film (sacrificial oxide film) 25 on the lower surface of the capacitor lower electrode 26 is formed.
[See FIG. 1A] is entirely removed by isotropic etching using an aqueous solution of hydrofluoric acid to expose the lower side surface of the polycrystalline silicon of the capacitor lower electrode 26. Next, FIG. 1 (c)
As shown in FIG.
Heat treatment is performed for 0 minutes (second heat treatment of the capacitor lower electrode). As a result, the grains that have not completely grown on the lower surface side of the capacitor lower electrode 26 grow to the same size as the upper surface side. Note that generally, heat treatment can be performed at a temperature of 800 ° C. to 1000 ° C. in an inert gas atmosphere.

Next, as shown in FIG. 1 (d), a nitride film to be a dielectric film is formed by a low pressure CVD method at 50 to 100 liters. Further, since the nitride film alone has a weak withstand voltage against electric field stress, after the nitride film is formed, it is oxidized in an oxygen atmosphere to form the dielectric film 27. Next, as shown in FIG. 1E, a capacitor upper electrode 28 is then formed, and a protective film 29 is deposited thereon.

Next, a second embodiment of the present invention will be described. 8A to 8D are cross-sectional views of manufacturing steps of a semiconductor memory device showing another embodiment of the present invention. First, as shown in FIG. 8A, the interlayer insulating film 33 and the stopper nitride film 3 are formed on the source / drain of the MOS transistor 32 on the semiconductor substrate 31.
4. A capacitor lower electrode 36 having a fin extending to the oxide film is connected through the oxide film contact hole. Next, the oxide film (sacrificial oxide film) on the lower side surface of the capacitor lower electrode 36 is entirely removed by isotropic etching using an aqueous solution of hydrofluoric acid to expose the back surface of the polycrystalline silicon of the capacitor lower electrode 36.

Next, as shown in FIG. 8B, heat treatment is performed for 30 to 60 minutes in an oxygen atmosphere (second heat treatment of the lower electrode). As a result, the grains that have not completely grown on the lower surface side of the capacitor lower electrode 36 grow to the same size as the upper surface side. Next, after removing the oxide film on the polycrystalline silicon of the capacitor lower electrode 36, the surface of the capacitor lower electrode 36 is nitrided by annealing at 850 ° C. in an ammonia gas or laughing gas atmosphere for about 30 seconds for a short time. In this process, RTA (Rap
An id Thermal Annealing device is suitable. Generally, 800 in a laughing gas atmosphere
It can be annealed at a temperature of ℃ to 1000 ℃ for a short time.

Next, the reduced pressure C is applied to the nitride film 34 to be the dielectric film.
40 to 50Å is generated by the VD method. At this time, since the surface of the capacitor lower electrode 36 is nitrided, the dielectric film 37
The oxidation resistance of is improved. Further, since the nitride film 34 alone has a low withstand voltage against electric field stress, after the nitride film 34 is formed, it is oxidized in an oxygen atmosphere to form a dielectric film 37 as shown in FIG. 8C.

Thereafter, as shown in FIG. 8D, a capacitor upper electrode 38 is formed, and a protective film 39 is deposited thereon. A memory cell having a fin-structured capacitor lower electrode according to a conventional method for manufacturing a semiconductor memory device, and a fin-structured memory cell subjected to heat treatment after removing a sacrificial oxide film on the lower surface of the capacitor lower electrode according to the method for manufacturing a semiconductor memory device of the present invention. Further, FIG. 9 shows a Weibull plot diagram of the acceleration test under the stress of constant electric field. In this figure, the horizontal axis represents time (seconds) and the vertical axis represents cumulative defective rate (%).

As is apparent from this figure, the memory cell of the fin structure according to the present invention, that is, the capacitor lower electrode is removed by performing the second heat treatment after removing the oxide film on the lower surface side of the capacitor lower electrode of the fin structure. In the case of a dielectric film which is formed and is formed on the lower electrode of the capacitor (solid line b), a memory cell having a conventional fin structure (dashed line a)
It can be seen that the life is longer.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0025]

As described above in detail, according to the present invention, the sacrificial oxide film on the lower surface of the capacitor lower electrode is removed, and then the heat treatment is further performed. Since the oxide film existing in the lower layer of the lower electrode is removed in the heat treatment step of, the grains on the lower surface side of the capacitor lower electrode that could not be grown by the first heat treatment are equal to the upper surface side. grow up.

As a result, the surface state of the polycrystalline silicon on the upper surface side and the lower surface side of the capacitor lower electrode and the grain size of the grains of the polycrystalline silicon can be made equal. Therefore, the semiconductor memory device having the fin-structured capacitor lower electrode of the present invention can extend the life of the dielectric film as compared with the conventional semiconductor memory device having the fin-structured capacitor lower electrode.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part manufacturing process of a semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is a schematic manufacturing process diagram of a semiconductor memory device showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional stack type memory cell.

FIG. 4 is a cross-sectional view of a memory cell having a conventional fin structure capacitor lower electrode.

FIG. 5 is a schematic manufacturing process diagram of a memory cell having a conventional fin-structured capacitor lower electrode.

FIG. 6 is an enlarged partial sectional view showing a state after a step of forming a conventional capacitor lower electrode having a fin structure.

FIG. 7 is an enlarged partial sectional view of a conventional capacitor lower electrode having a fin structure.

FIG. 8 is a cross-sectional view of a main part manufacturing process of a semiconductor memory device showing another embodiment of the present invention.

FIG. 9 is a characteristic diagram showing the effect of the present invention.

[Explanation of symbols]

21, 31 Semiconductor substrate 22, 32 MOS transistor 23, 33 Interlayer insulating film 24, 34 Stopper nitride film 25 Oxide film 26, 36 Capacitor lower electrode 26a, Oxide film (sacrificial oxide film) on the lower side of the capacitor lower electrode 27, 37 Dielectric film 28,38 Capacitor upper electrode 29,39 Protective film

Claims (4)

[Claims] 1. A step of: (a) forming a polycrystalline silicon film, doping the polycrystalline silicon film with an impurity, and then forming a fin of the polycrystalline silicon film to be a capacitor lower electrode; Exposing the lower surface of the fin of the crystalline silicon film; (c) applying heat treatment to the fin of the polycrystalline silicon film; (d) forming a dielectric film so as to cover the fin of the polycrystalline silicon film. And a step of (e) forming a capacitor upper electrode so as to cover the dielectric film in this order, a method of manufacturing a semiconductor memory device. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the heat treatment is performed at 800 ° C. in an inert gas atmosphere.
A method of manufacturing a semiconductor memory device, which is performed at a temperature of 1000 to 1000 ° C. 3. The semiconductor memory device manufacturing method according to claim 1, further comprising a step of performing the heat treatment in an oxidizing atmosphere and then removing an oxide film on a fin surface of the polycrystalline silicon film. Storage device manufacturing method. 4. The method for manufacturing a semiconductor memory device according to claim 1, wherein the dielectric film is formed in an ammonia (NH ₃ ) or laughing gas (N ₂ O) atmosphere before forming the dielectric film.
A method for manufacturing a semiconductor memory device, which comprises performing a step of annealing at a temperature of 0 ° C. to 1000 ° C. for a short time to form a nitride film on the surface of a polycrystalline silicon film.