JPH06216302A - Semiconductor device sealed with resin and its manufacture - Google Patents
Semiconductor device sealed with resin and its manufactureInfo
- Publication number
- JPH06216302A JPH06216302A JP5007847A JP784793A JPH06216302A JP H06216302 A JPH06216302 A JP H06216302A JP 5007847 A JP5007847 A JP 5007847A JP 784793 A JP784793 A JP 784793A JP H06216302 A JPH06216302 A JP H06216302A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- adhesive layer
- resin
- stage
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置及
びその製造方法、特にリードフレームにおけるチップス
テージを改良した樹脂モールド型半導体装置及びその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device and a method for manufacturing the same, and more particularly to a resin-molded semiconductor device with an improved chip stage in a lead frame and a method for manufacturing the same.
【０００２】近年、半導体パッケージの薄型化の進行と
ともに、樹脂モールド型半導体装置においてはリードフ
レームの厚さが極度に薄くなってきている。そのため
に、リードフレーム材料と半導体チップとの線膨張係数
の違いによりパッケージ内に応力が発生し、それに起因
したパッケージクラックによる半導体装置の信頼性や寿
命の劣化が顕在化しており、対策が望まれている。In recent years, with the progress of thinner semiconductor packages, the lead frame of resin-molded semiconductor devices has become extremely thin. Therefore, stress is generated in the package due to the difference in linear expansion coefficient between the lead frame material and the semiconductor chip, and the deterioration of the reliability and life of the semiconductor device due to the package crack caused by it is becoming apparent. ing.
【０００３】[0003]
【従来の技術】図５は樹脂モールド型半導体装置の従来
例の模式断面図である。図において、１は半導体チッ
プ、２は接着剤、３は鉄・ニッケル合金等からなるリー
ドフレームのチップステージで、半導体チップ１は接着
剤２によりチップステージ３上に固着されている。ま
た、５はリードフレームのリード、６はボンディングワ
イヤで、図示しない半導体チップ１上のボンディングパ
ッドとリードフレームのリード５の内側端部とをボンデ
ィング接続している。そして、７は樹脂パッケージで、
半導体チップ１が固着されたチップステージ３と、ボン
ディングワイヤ６の配設部を覆うようにモールド成形さ
れている。2. Description of the Related Art FIG. 5 is a schematic sectional view of a conventional example of a resin mold type semiconductor device. In the figure, 1 is a semiconductor chip, 2 is an adhesive agent, 3 is a chip stage of a lead frame made of iron-nickel alloy or the like, and the semiconductor chip 1 is fixed onto a chip stage 3 with an adhesive agent 2. Further, 5 is a lead of the lead frame, and 6 is a bonding wire for bonding and connecting a bonding pad on the semiconductor chip 1 (not shown) and an inner end portion of the lead 5 of the lead frame. And 7 is a resin package,
It is molded so as to cover the chip stage 3 to which the semiconductor chip 1 is fixed and the portion where the bonding wire 6 is provided.
【０００４】[0004]
【発明が解決しようとする課題】上記図５に示されるよ
うに従来の樹脂モールド型半導体装置では、半導体チッ
プ１はリードフレーム材料（鉄・ニッケル合金等）から
なる平板状のチップステージ３上に接着剤２によって固
着された構造を有しており、金属材料からなるリードフ
レームと半導体チップとの線膨張係数の大きな違いによ
って、温度の上昇・下降に際して、チップステージ３と
半導体チップ１との間には大きな応力が発生していた。As shown in FIG. 5, in the conventional resin mold type semiconductor device, the semiconductor chip 1 is mounted on a flat chip stage 3 made of a lead frame material (iron / nickel alloy, etc.). It has a structure in which it is fixed by an adhesive agent 2, and due to a large difference in linear expansion coefficient between the lead frame made of a metal material and the semiconductor chip, when the temperature rises and falls, the chip stage 3 and the semiconductor chip 1 are separated from each other. A large amount of stress was generated in the.
【０００５】そのために、前述のようにパッケージの薄
型化によってリードフレームが極度に薄くなった場合、
組立工程内での熱ストレスで生ずるリードフレームの反
り等により、ダイス付け材にかかる応力がより一層厳し
くなり、ダイス付け部の劣化を生ずる。その結果、半導
体装置完成から基板実装までの時間経過の間に外部から
モールド樹脂を通って滲透した水分が、上記劣化を生じ
たダイス付け部近傍に蓄積し、基板実装の加熱により水
蒸気爆発を起こしてパッケージクラックを発生させると
いう経過をたどり、このパッケージクラックにより半導
体装置内部のワイヤ接続や、半導体装置自体の耐湿性が
損なわれて、当該半導体装置の信頼性及び寿命が劣化す
るという問題を生じていた。Therefore, when the lead frame is extremely thin due to the thinning of the package as described above,
Due to the warp of the lead frame and the like caused by the thermal stress in the assembly process, the stress applied to the die attaching material becomes more severe and the die attaching portion is deteriorated. As a result, moisture permeated from outside through the mold resin during the time from the completion of the semiconductor device to the board mounting accumulates in the vicinity of the die attachment part where the deterioration has occurred, causing a steam explosion due to the heating of the board mounting. And the package crack is generated, and this package crack causes a problem that wire connection inside the semiconductor device and moisture resistance of the semiconductor device itself are impaired, and reliability and life of the semiconductor device are deteriorated. It was
【０００６】そこで本発明は半導体チップとの間に発生
する応力が抑制されるチップステージ構造を有する樹脂
封止型半導体装置及びその製造方法を提供しパッケージ
クラックを防止して、樹脂封止型半導体装置の信頼性向
上及び長寿命化を図ることを目的とする。Therefore, the present invention provides a resin-sealed semiconductor device having a chip stage structure in which stress generated between the semiconductor chip and the semiconductor chip is suppressed, and a method for manufacturing the same, to prevent package cracks and to prevent resin-sealed semiconductors. The purpose is to improve the reliability of the device and extend its service life.
【０００７】[0007]
【課題を解決するための手段】上記課題の解決は、金属
からなり、中央部に貫通穴を有する枠状のチップステー
ジと、該枠状チップステージの貫通穴内に埋め込まれた
接着剤層と、該接着剤層上に固着された半導体チップ
と、少なくとも該枠状チップステージと接着剤層及び半
導体チップの表面を覆って成形された封止樹脂層を有す
る本発明による樹脂封止型半導体装置、若しくは、リー
ドフレームにおけるチップステージの中央部に貫通穴を
設ける工程と、該チップステージの裏面に該貫通穴を底
部から塞ぐように耐熱シートを貼りつける工程と、該貫
通穴内に接着剤層を埋込む工程と、該接着剤層上に半導
体チップを固着する工程と、該耐熱シートを剥離する工
程と、少なくとも該チップステージ、接着剤層及び半導
体チップの表面を覆って樹脂封止を行う工程とを含む本
発明による樹脂封止型半導体装置の製造方法によって達
成される。Means for Solving the Problems To solve the above-mentioned problems, a frame-shaped chip stage made of metal and having a through hole in a central portion, and an adhesive layer embedded in the through hole of the frame-shaped chip stage, A resin-encapsulated semiconductor device according to the present invention, comprising a semiconductor chip fixed on the adhesive layer, at least the frame-shaped chip stage, an adhesive layer, and an encapsulating resin layer formed to cover the surface of the semiconductor chip. Alternatively, a step of forming a through hole in the central portion of the chip stage in the lead frame, a step of attaching a heat-resistant sheet to the back surface of the chip stage so as to close the through hole from the bottom, and an adhesive layer embedded in the through hole. The step of inserting, the step of fixing the semiconductor chip on the adhesive layer, the step of peeling off the heat resistant sheet, and the step of covering at least the surface of the chip stage, the adhesive layer and the semiconductor chip. It is achieved by the method of manufacturing a resin-sealed semiconductor device according to the invention comprising a step of performing resin sealing Te.
【０００８】[0008]
【作用】図１は本発明の原理説明図で、(a) は斜視図、
(b) はＡ−Ａ′断面図である。この図に示すように本発
明によれば、樹脂封止型半導体装置におけるチップステ
ージは、リードフレーム材料（鉄・ニッケル合金等）か
らなるチップステージ３の中央部に設けた半導体チップ
１より大きい貫通穴８内に接着剤層９が埋め込まれた構
造に形成され、半導体チップ１は上記チップステージ３
の貫通穴８に埋め込まれた接着剤層９上にこの接着剤層
９自体若しくは更に追加塗布される他の接着剤層を介し
て接着固定される。接着剤層９の線膨張係数は半導体チ
ップ１の線膨張係数に充分に近づけることが可能であ
る。そのため上記構造にすれば、半導体装置実装時の熱
を受けた際に、半導体チップ１からチップステージ３に
及ぼされる応力を最小限に抑えることが可能になり、ス
テージ３詳しくは接着剤層９上からの半導体装置チップ
１の剥がれは防止されるので、主としてこの半導体チッ
プ１の剥がれに起因して発生するパッケージクラック障
害は大幅に減少される。従って本発明によれば、樹脂封
止型半導体装置の信頼性向上及び長寿命化を図ることが
できる。FIG. 1 is an explanatory view of the principle of the present invention, (a) is a perspective view,
(b) is an AA 'sectional view. As shown in this figure, according to the present invention, the chip stage in the resin-sealed semiconductor device is larger than the semiconductor chip 1 provided in the central portion of the chip stage 3 made of a lead frame material (iron / nickel alloy or the like). The semiconductor chip 1 is formed in a structure in which the adhesive layer 9 is embedded in the hole 8, and the semiconductor chip 1 is the chip stage 3 described above.
The adhesive layer 9 is embedded and fixed on the adhesive layer 9 embedded in the through hole 8 through the adhesive layer 9 itself or another adhesive layer additionally applied. The linear expansion coefficient of the adhesive layer 9 can be made sufficiently close to the linear expansion coefficient of the semiconductor chip 1. Therefore, with the above structure, it is possible to minimize the stress exerted on the chip stage 3 from the semiconductor chip 1 when receiving heat during mounting of the semiconductor device. Since the peeling of the semiconductor device chip 1 from the chip is prevented, the package crack failure mainly caused by the peeling of the semiconductor chip 1 is greatly reduced. Therefore, according to the present invention, it is possible to improve the reliability and extend the life of the resin-encapsulated semiconductor device.
【０００９】[0009]
【実施例】以下本発明を、図示実施例により具体的に説
明する。図２は本発明に係る構造の一実施例の模式断面
図、図３は本発明の方法の一実施例の工程斜視図、図４
は同一実施例の工程断面図である。全図を通じ同一対象
物は同一符合で示す。EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 2 is a schematic cross-sectional view of one embodiment of the structure according to the present invention, FIG. 3 is a perspective view of steps of one embodiment of the method of the present invention, and FIG.
[FIG. 3] is a process sectional view of the same embodiment. The same object is denoted by the same reference numeral throughout the drawings.
【００１０】本発明に係る樹脂モールド型半導体装置
は、例えば図２に示すように、鉄・ニッケル合金（４２
アロイ等）からなるリードフレームの一部として形成さ
れ封止後にリードフレームから切断分離された例えば厚
さ80μｍ程度のチップステージ13の中央部に、搭載され
る半導体チップ11より大きな角形の貫通穴18が設けら
れ、この貫通穴18の内部に、高熱伝導性を有する窒化ア
ルミニウム若しくはダイヤモンド粉末等のフィラーを含
んだエポキシ樹脂からなる接着剤層19が平坦に埋め込ま
れ、この接着剤層19上に例えばこの接着剤層19自体によ
って半導体チップ11が接着固定され、この半導体チップ
11上の図示されないボンディングパッドと上記リードフ
レームから切断されたリード15の内側端部とがボンディ
ングワイヤ16によってボンディング接続され、上記半導
体チップ11が固着された接着剤層19、接着剤層19が埋め
込まれたチップステージ13及びボンディングワイヤ16の
配設領域がモールド成形された樹脂パッケージ17内に封
入された構造を有する。The resin-molded semiconductor device according to the present invention is, for example, as shown in FIG.
A rectangular through hole 18 larger than the semiconductor chip 11 to be mounted in the central portion of a chip stage 13 having a thickness of, for example, about 80 μm which is formed as a part of a lead frame made of alloy or the like) and is cut and separated from the lead frame after sealing. Is provided, the adhesive layer 19 made of an epoxy resin containing a filler such as aluminum nitride or diamond powder having high thermal conductivity is flatly embedded inside the through hole 18, and, for example, on the adhesive layer 19. The semiconductor chip 11 is adhered and fixed by the adhesive layer 19 itself.
A bonding pad (not shown) on 11 and an inner end portion of the lead 15 cut from the lead frame are bonded and connected by a bonding wire 16, and an adhesive layer 19 to which the semiconductor chip 11 is fixed and an adhesive layer 19 are embedded. A region where the chip stage 13 and the bonding wire 16 are disposed is enclosed in a molded resin package 17.
【００１１】そして、上記構造を有する半導体装置は、
例えば以下に図３の工程斜視図及び図４の工程断面図を
参照して述べる方法により形成される。 図３(a) 及び図４(a) 参照 即ち本発明の方法においては、例えば前記厚さの鉄・ニ
ッケル合金板をリードフレーム形状に打ち抜く際に、同
時にチップステージ13の中央部に、搭載される半導体チ
ップ11より大きな角形の貫通穴18を打ち抜く。なお図中
の、15は図示しないリードフレームに形成されるリー
ド、20はチップステージの支持桟を示す。The semiconductor device having the above structure is
For example, it is formed by the method described below with reference to the process perspective view of FIG. 3 and the process sectional view of FIG. 3 (a) and 4 (a). That is, in the method of the present invention, for example, when the iron / nickel alloy plate having the above-mentioned thickness is punched into a lead frame shape, it is mounted on the central portion of the chip stage 13 at the same time. A rectangular through hole 18 larger than the semiconductor chip 11 is punched out. In the figure, 15 is a lead formed on a lead frame (not shown), and 20 is a support bar of the chip stage.
【００１２】図３(b) 及び図４(b) 参照 次いで、チップステージ13の裏面に前記貫通穴18の底部
を塞ぐように 200℃程度の温度には充分耐えるような例
えば厚さ50〜100 μｍ程度の耐熱テープ例えばポリイミ
ドテープ14を、このテープの片面に塗布されている図示
しない耐熱性接着剤によって貼りつける。Referring to FIGS. 3B and 4B, the bottom surface of the through hole 18 is covered with the back surface of the chip stage 13 so that it can withstand a temperature of about 200 ° C., for example, a thickness of 50 to 100. A heat resistant tape of about μm, for example, a polyimide tape 14 is attached by a heat resistant adhesive (not shown) applied to one surface of the tape.
【００１３】図３(c) 及び図４(c) 参照 次いで、上記底部がポリイミドテープ14で蓋されたチッ
プステージ13の貫通穴18内に、例えば窒化アルミニウ
ム、ダイヤモンド粉末等の熱伝導性に優れた材料からな
るフイラーを混入して放熱性を増したエポキシ樹脂を注
入し、例えば 120℃程度の所定のプリキュアーを行うこ
とにより、上記貫通穴18内に前記放熱性に優れたエポキ
シ樹脂からなる接着剤層19を平坦に埋込む。ここまで
で、本発明に係わる構造を有するチップステージが完成
する。3 (c) and 4 (c) Next, in the through hole 18 of the chip stage 13 whose bottom is covered with the polyimide tape 14, for example, aluminum nitride, diamond powder, etc. are excellent in thermal conductivity. A filler made of a different material is mixed in with an epoxy resin having improved heat dissipation, and a predetermined precure is performed at, for example, about 120 ° C. to bond the epoxy resin having excellent heat dissipation to the through hole 18. The agent layer 19 is embedded evenly. By this, the chip stage having the structure according to the present invention is completed.
【００１４】図３(d) 及び図４(d) 参照 次いで、上記チップステージ13の貫通穴18内に埋め込ま
れた接着剤層19上に半導体チップ11を圧接しながら例え
ば150 ℃程度の所定の温度により接着剤層19のアフター
キュアーを行い、この際同時に、接着剤層19自体の接着
性により半導体チップ11を接着剤層19上に接着固定す
る。Referring to FIGS. 3D and 4D, the semiconductor chip 11 is pressed onto the adhesive layer 19 embedded in the through hole 18 of the chip stage 13 while being pressed at a predetermined temperature of, for example, about 150.degree. After-curing of the adhesive layer 19 is performed by the temperature, and at the same time, the semiconductor chip 11 is adhesively fixed onto the adhesive layer 19 by the adhesive property of the adhesive layer 19 itself.
【００１５】図４(e) 参照 次いで、通常通り、半導体チップ11上の図示しないボン
ディングパッドとリード15の内側端部との間をボンディ
ングワイヤ16で接続した後、チップステージ13の裏面に
貼りつけたポリイミドテープ14を剥離する。Next, as shown in FIG. 4 (e), a bonding pad (not shown) on the semiconductor chip 11 and the inner end of the lead 15 are connected by a bonding wire 16 as usual, and then bonded to the back surface of the chip stage 13. The removed polyimide tape 14 is peeled off.
【００１６】図３(f) 及び図４(f) 参照 次いで、通常通り、例えばエポキシ樹脂等を用い、上記
半導体チップ11が固着された接着剤層19、接着剤層19が
埋め込まれたチップステージ13及びボンディングワイヤ
16の配設領域を樹脂モールドにより樹脂パッケージ17内
に封入し、次いで図示しないリードフレームの不要部分
を切断除去し、本発明に係る樹脂モールド型の半導体装
置が完成する。3 (f) and 4 (f). Then, as usual, an adhesive layer 19 to which the semiconductor chip 11 is fixed and a chip stage in which the adhesive layer 19 is embedded are formed by using, for example, an epoxy resin. 13 and bonding wire
The area where 16 is arranged is sealed in a resin package 17 by resin molding, and then unnecessary portions of a lead frame (not shown) are cut and removed to complete a resin-molded semiconductor device according to the present invention.
【００１７】上記実施例に示すような方法により形成さ
れる例えば図２に示される本発明に係る樹脂封止型半導
体装置においては、半導体チップ11と半導体チップ11が
固着されるチップステージ13の接着剤層19の線膨張係数
は非常に近い値に形成することが可能であるので、配線
基板等への実装時に半導体装置が熱を受けた際に、半導
体チップ11と上記接着剤層19の間に生ずる応力は極めて
小さくなり、チップステージの反りやチップ剥がれが発
生しなくなる。従って前記チップステージ13の反りや、
チップ剥がれによってチップステージ13と半導体チップ
11間に生ずる隙間に蓄積される水分の水蒸気爆発によっ
て従来発生していたパッケージクラック障害は防止さ
れ、樹脂封止型半導体装置の信頼性及び寿命が向上す
る。In the resin-sealed semiconductor device according to the present invention shown in FIG. 2, which is formed by the method shown in the above embodiment, the semiconductor chip 11 and the chip stage 13 to which the semiconductor chip 11 is fixed are bonded. Since the linear expansion coefficient of the agent layer 19 can be formed to a value very close to that between the semiconductor chip 11 and the adhesive layer 19 when the semiconductor device receives heat during mounting on a wiring board or the like. The stress generated in the chip becomes extremely small, and the chip stage does not warp or peel off. Therefore, the warp of the chip stage 13,
Chip stage 13 and semiconductor chip due to chip peeling
The package crack failure that has conventionally occurred due to the steam explosion of the water accumulated in the gap between 11 is prevented, and the reliability and life of the resin-sealed semiconductor device are improved.
【００１８】なお、上記実施例においては、チップステ
ージ13の貫通穴18内に埋込む接着剤層19に熱硬化性のエ
ポキシ樹脂を用いたが、この接着剤層19には熱可塑性の
樹脂を用いてもよい。その場合、接着剤層は実装時の熱
により可塑性を持つので、半導体チップと接着剤層及び
接着剤層とその周囲のチップステージとの間には殆ど応
力が生じなくなり、チップ剥離の防止効果は一層大きく
なる。また、接着剤層内にボイドが発生するのも防止さ
れるので、その効果は一層大きくなる。In the above embodiment, the thermosetting epoxy resin is used for the adhesive layer 19 embedded in the through hole 18 of the chip stage 13. However, the adhesive layer 19 is made of a thermoplastic resin. You may use. In that case, since the adhesive layer has plasticity due to heat during mounting, almost no stress is generated between the semiconductor chip and the adhesive layer and between the adhesive layer and the chip stage around it, and the chip peeling prevention effect is It gets even bigger. In addition, voids are prevented from being generated in the adhesive layer, so that the effect is further enhanced.
【００１９】また、接着剤層に混入されるフィラーは、
実施例に示された窒化アルミニウム及びダイヤモンドの
ように絶縁体に限られるものではなく、タングステン等
の電気伝導性を有する材料であってもよい。The filler mixed in the adhesive layer is
The material is not limited to an insulator such as aluminum nitride and diamond shown in the embodiments, but may be a material having electric conductivity such as tungsten.
【００２０】[0020]
【発明の効果】以上説明のように、本発明によれば樹脂
封止型半導体装置の内部に発生する応力の減少、及び耐
湿性の向上、パッケージクラックの防止がはかれる。従
って本発明は樹脂封止型半導体装置の信頼性の向上及び
長寿命化に寄与するところが大きい。As described above, according to the present invention, it is possible to reduce the stress generated inside the resin-encapsulated semiconductor device, improve the moisture resistance, and prevent package cracks. Therefore, the present invention greatly contributes to improvement of reliability and extension of life of the resin-encapsulated semiconductor device.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明に係る構造の一実施例の模式断面図FIG. 2 is a schematic cross-sectional view of an example of a structure according to the present invention.
【図３】 本発明の方法の一実施例の工程斜視図FIG. 3 is a process perspective view of an embodiment of the method of the present invention.
【図４】 本発明の方法の一実施例の工程断面図FIG. 4 is a process sectional view of an embodiment of the method of the present invention.
【図５】 従来例の模式断面図FIG. 5 is a schematic sectional view of a conventional example.
１、11 半導体チップ ２、12 接着剤層 ３、13 チップステージ 14 ポリイミドテープ ５、15 リード ６、16 ボンディングワイヤ 17 樹脂パッケージ 1, 11 Semiconductor chip 2, 12 Adhesive layer 3, 13 Chip stage 14 Polyimide tape 5, 15 Lead 6, 16 Bonding wire 17 Resin package
Claims (4)
枠状のチップステージと、該枠状チップステージの貫通
穴内に埋め込まれた接着剤層と、該接着剤層上に固着さ
れた半導体チップと、少なくとも該枠状チップステージ
と接着剤層及び半導体チップの表面を覆って成形された
封止樹脂層を有することを特徴とする樹脂封止型半導体
装置。1. A frame-shaped chip stage which is made of metal and has a through hole in its central portion, an adhesive layer embedded in the through hole of the frame-shaped chip stage, and a semiconductor fixed on the adhesive layer. A resin-encapsulated semiconductor device comprising: a chip, at least the frame-shaped chip stage, an adhesive layer, and an encapsulating resin layer formed so as to cover the surface of the semiconductor chip.
の中央部に貫通穴を設ける工程と、該チップステージの
裏面に該貫通穴の底部を塞ぐように耐熱シートを貼りつ
ける工程と、該貫通穴内に接着剤層を埋込む工程と、該
接着剤層上に半導体チップを固着する工程と、該耐熱シ
ートを剥離する工程と、少なくとも該チップステージ、
接着剤層及び半導体チップの表面を覆って樹脂封止を行
う工程とを含むことを特徴とする樹脂封止型半導体装置
の製造方法。2. A step of providing a through hole in a central portion of a chip stage in a lead frame, a step of attaching a heat resistant sheet to a back surface of the chip stage so as to close a bottom portion of the through hole, and an adhesive in the through hole. A step of embedding a layer, a step of fixing a semiconductor chip on the adhesive layer, a step of peeling the heat-resistant sheet, at least the chip stage,
And a step of covering the surfaces of the adhesive layer and the semiconductor chip to perform resin sealing, and a method of manufacturing a resin-sealed semiconductor device.
くはダイヤモンドよりなるフィラーを含んでいることを
特徴とする請求項１記載の樹脂封止型半導体装置。3. The resin-encapsulated semiconductor device according to claim 1, wherein the adhesive layer contains a filler made of aluminum nitride or diamond.
くはダイヤモンドよりなるフィラーを含んでいることを
特徴とする請求項２記載の樹脂封止型半導体装置の製造
方法。4. The method for manufacturing a resin-sealed semiconductor device according to claim 2, wherein the adhesive layer contains a filler made of aluminum nitride or diamond.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5007847A JPH06216302A (en) | 1993-01-20 | 1993-01-20 | Semiconductor device sealed with resin and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5007847A JPH06216302A (en) | 1993-01-20 | 1993-01-20 | Semiconductor device sealed with resin and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06216302A true JPH06216302A (en) | 1994-08-05 |
Family
ID=11677017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5007847A Withdrawn JPH06216302A (en) | 1993-01-20 | 1993-01-20 | Semiconductor device sealed with resin and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06216302A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729049A (en) * | 1996-03-19 | 1998-03-17 | Micron Technology, Inc. | Tape under frame for conventional-type IC package assembly |
-
1993
- 1993-01-20 JP JP5007847A patent/JPH06216302A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729049A (en) * | 1996-03-19 | 1998-03-17 | Micron Technology, Inc. | Tape under frame for conventional-type IC package assembly |
| US5915166A (en) * | 1996-03-19 | 1999-06-22 | Micron Technology, Inc. | Tape under frame for conventional-type IC package assembly |
| US6091133A (en) * | 1996-03-19 | 2000-07-18 | Corisis; David J. | Assembly of a semiconductor device and paddleless lead frame having tape extending between the lead fingers |
| US6143589A (en) * | 1996-03-19 | 2000-11-07 | Micron Technology, Inc. | Tape under frame for conventional-type IC package assembly |
| US6518650B2 (en) | 1996-03-19 | 2003-02-11 | Micron Technology, Inc. | Tape under frame for lead frame IC package assembly |
| US6894372B2 (en) | 1996-03-19 | 2005-05-17 | Micron Technology, Inc. | Tape under frame for lead frame IC package assembly |
| US6921966B2 (en) | 1996-03-19 | 2005-07-26 | Micron Technology, Inc. | Tape under frame for lead frame IC package assembly |
| US6979596B2 (en) | 1996-03-19 | 2005-12-27 | Micron Technology, Inc. | Method of fabricating a tape having apertures under a lead frame for conventional IC packages |
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|---|---|---|---|
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