JPH06216293A - Leadframe, and manufacture of lsi package using the same - Google Patents
Leadframe, and manufacture of lsi package using the sameInfo
- Publication number
- JPH06216293A JPH06216293A JP766393A JP766393A JPH06216293A JP H06216293 A JPH06216293 A JP H06216293A JP 766393 A JP766393 A JP 766393A JP 766393 A JP766393 A JP 766393A JP H06216293 A JPH06216293 A JP H06216293A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead portion
- semiconductor element
- lsi package
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、リ−ドフレ−ムおよ
びこのリ−ドフレ−ムを用いたＬＳＩパッケ−ジの製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a method for manufacturing an LSI package using the lead frame.
【０００２】[0002]
【従来の技術】いわゆるＬＳＩパッケ−ジは、半導体素
子をリ−ドフレ−ムと呼ばれる基板に搭載した後、これ
を樹脂封止することで製造される。2. Description of the Related Art A so-called LSI package is manufactured by mounting a semiconductor element on a substrate called a lead frame and then sealing it with a resin.
【０００３】このようなＬＳＩパッケ−ジに用いられる
リ−ドフレ−ム１は、一般に図５（ａ）に示すように、
半導体素子２が搭載（ダイボンディング）されるダイパ
ッド部３と、このダイパッド部３の側方に設けられたリ
−ド部４とを具備する。上記半導体素子２は、このリ−
ドフレ−ム１のダイパッド部３上に搭載（ダイボンディ
ング）された後、上記リ−ド部４にワイヤボンディング
される。A lead frame 1 used in such an LSI package generally has a structure as shown in FIG.
A die pad portion 3 on which the semiconductor element 2 is mounted (die bonding) and a lead portion 4 provided on the side of the die pad portion 3 are provided. The semiconductor element 2 is
After being mounted (die bonded) on the die pad portion 3 of the dframe 1, it is wire bonded to the lead portion 4.
【０００４】このようにして半導体素子２が搭載された
リ−ドフレ−ム１は、図に示すように、成形金型５のキ
ャビティ５ａ内に投入され、樹脂封止される。樹脂封止
が終了したならば、この成形金型５内から取り出され上
記リ−ド部４を切断、折曲することで、このＬＳＩパッ
ケ−ジは完成する。The lead frame 1 on which the semiconductor element 2 is mounted in this manner is put into the cavity 5a of the molding die 5 and resin-sealed, as shown in the figure. When the resin sealing is completed, the LSI package is completed by taking out from the molding die 5 and cutting and bending the lead portion 4.
【０００５】[0005]
【発明が解決しようとする課題】ところで、従来のＬＳ
Ｉパッケ−ジには、以下に説明するような欠点があっ
た。By the way, the conventional LS
The I package has the following drawbacks.
【０００６】すなわち、樹脂封止時には、図５（ｂ）に
Ａで示すように、上記成形金型５と上記リ−ド部４との
間に、このリ−ド部４の寸法精度や熱変形等および上記
金型５の熱変形に起因して若干の隙間が生じる。That is, at the time of resin sealing, as shown by A in FIG. 5B, between the molding die 5 and the lead portion 4, the dimensional accuracy and heat of the lead portion 4 are increased. A slight gap is generated due to deformation and the like and thermal deformation of the mold 5.
【０００７】この樹脂封止に使用するエポキシ樹脂は非
常に流動性の良いものであるから、上記成形金型５とリ
−ド部４の隙間Ａが０．００５ｍｍのように非常に狭い
場合であってもこの隙間Ａに流出し、成形終了後に固化
して「ばり」が生じることがある。Since the epoxy resin used for this resin encapsulation has a very good fluidity, it can be used when the gap A between the molding die 5 and the lead portion 4 is very narrow, such as 0.005 mm. Even if there is, it may flow out into the gap A and solidify after the completion of molding to cause "burrs".
【０００８】「ばり」が発生すると、第１に、この「ば
り」が上記成形金型５に付着し、変形磨耗の原因になる
他、リ−ド部４の変形など製造されるＬＳＩパッケ−ジ
の信頼性が低下する問題がある。When the "burr" is generated, firstly, the "burr" adheres to the molding die 5 to cause deformation and wear, and also the LSI package to be manufactured such as the deformation of the lead portion 4 is manufactured. There is a problem that the reliability of Ji decreases.
【０００９】また、第２に、「ばり」がリ−ド部４に付
着し、リ−ド部４の打ち抜きおよびこのリ−ド部４の曲
げを行う際に打ち抜き精度および曲げ精度を劣化させる
ということがある。また、このリ−ド部４の打ち抜きや
曲げを行う金型等の変形磨耗の原因となる問題もある。Secondly, "burrs" adhere to the lead portion 4 and deteriorate punching accuracy and bending accuracy when punching the lead portion 4 and bending the lead portion 4. There is a thing. Further, there is also a problem of causing deformation and wear of a die for punching or bending the lead portion 4.
【００１０】このような問題を解決するために、従来
は、ＬＳＩパッケ−ジの製造工程中にばり取り工程を設
けていた。しかし、このような工程を設けると、製造コ
ストが高くなると共に、ばり取りによって生じた粉塵の
問題により製造工程中の環境が悪化するということあ
る。In order to solve such a problem, conventionally, a deburring step has been provided during the manufacturing process of the LSI package. However, if such a process is provided, the manufacturing cost becomes high, and the environment during the manufacturing process is deteriorated due to the problem of dust generated by deburring.
【００１１】この発明は、このような事情に鑑みてなさ
れたもので、ＬＳＩパッケ−ジの製造において、ばりが
生じないようなリ−ドフレ−ムおよびこのリ−ドフレ−
ムを用いたＬＳＩパッケ−ジの製造方法を提供すること
を目的とするものである。The present invention has been made in view of the above circumstances, and a lead frame and a lead frame which do not cause burrs in the manufacture of an LSI package.
It is an object of the present invention to provide a method of manufacturing an LSI package using a film.
【００１２】[0012]
【課題を解決するための手段】この発明の第１の手段
は、半導体素子がダイボンディングされるダイパッド部
と、先端をこのダイパッド部に対向させて設けられ上記
半導体素子にワイヤを介して接続されるリ−ド部とを具
備するリ−ドフレ−ムにおいて、上記リ−ド部の先端部
に突起部を設けたことを特徴とするリ−ドフレ−ムであ
る。A first means of the present invention is to provide a die pad portion to which a semiconductor element is die-bonded, and a tip provided so as to face the die pad portion and connected to the semiconductor element via a wire. A lead frame comprising a lead portion and a lead portion provided with a protrusion at a tip portion of the lead portion.
【００１３】第２の手段は、リ−ドフレ−ム上に半導体
素子を搭載し、このリ−ドフレ−ムのリ−ド部と半導体
素子とをワイヤボンディングした後、樹脂封止すること
でＬＳＩパッケ−ジを製造するＬＳＩパッケ−ジの製造
方法において、上記リ−ド部の先端部に、樹脂封止用金
型とリ−ド部との間に生じる隙間を閉塞する突起部を設
けたことを特徴とするＬＳＩパッケ−ジの製造方法であ
る。A second means is to mount a semiconductor element on the lead frame, wire-bond the lead portion of the lead frame and the semiconductor element, and then resin-encapsulate the LSI. In a method for manufacturing an LSI package for manufacturing a package, a projection portion is provided at the tip of the lead portion to close a gap formed between the resin sealing mold and the lead portion. And a method for manufacturing an LSI package.
【００１４】[0014]
【作用】このような構成によれば、樹脂封止用金型とリ
−ド部との隙間から封止用樹脂がリ−ド部の後端側に流
出するのを有効に防止できる。With this structure, it is possible to effectively prevent the sealing resin from flowing out to the rear end side of the lead portion from the gap between the resin sealing mold and the lead portion.
【００１５】[0015]
【実施例】以下、この発明の一実施例を図１〜図４を参
照して説明する。なお、従来例で説明した構成要素と同
一の構成要素には同一符号を付してその説明は省略す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The same components as those described in the conventional example are designated by the same reference numerals, and the description thereof will be omitted.
【００１６】この発明のＬＳＩパッケ−ジの製造方法に
用いられるリ−ドフレ−ムは、図１に１０で示すような
もので、半導体素子２が搭載（ダイボンディング）され
るダイパッド部１２と、このダイパッド部１２を挟んで
設けられ上記半導体素子２の電極と接続される複数本の
リ−ド部１３…とからなる。これらダイパッド部１２お
よびリ−ド部１３は、このダイパッド部１２およびリ−
ド部１３の回りに形成されたフレ−ム部１４によってば
らばらにならないように保持されている。The lead frame used in the method for manufacturing an LSI package of the present invention is as shown by 10 in FIG. 1, and includes a die pad portion 12 on which a semiconductor element 2 is mounted (die bonding). It is composed of a plurality of lead portions 13 ... Between which the die pad portion 12 is sandwiched and which is connected to the electrodes of the semiconductor element 2. The die pad portion 12 and the lead portion 13 are the same as the die pad portion 12 and the lead portion, respectively.
It is held so as not to fall apart by a frame portion 14 formed around the window portion 13.
【００１７】また、このリ−ドフレ−ム１４の表面およ
び裏面には、それぞれ一対の絶縁テ−プ１６、１６が平
行に離間して貼着されている。この絶縁テ−プ１６は、
上記ダイパッド部１２の両側に設けられた各リ−ド部１
３…すべてに跨がるように貼着されたものであり、この
絶縁テ−プ１６によって上記リ−ド部１３の先端部には
突起部１７が形成されている。A pair of insulating tapes 16 and 16 are adhered to the front and back surfaces of the lead frame 14 in parallel with each other. This insulation tape 16
Lead portions 1 provided on both sides of the die pad portion 12
3 is attached so as to straddle all of them, and the insulating tape 16 forms a protrusion 17 at the tip of the lead portion 13.
【００１８】この突起部は、例えば約０．０５ｍｍ程度
で、かつ断面形状は後述する（図２に示す）上型１８お
よび下型１９により構成されるキャビティ２１内に容易
に入り込むように、上辺の長さが底辺の長さよりも短い
台形状となっている。The protrusion is, for example, about 0.05 mm, and the cross-sectional shape is such that the upper side of the protrusion easily enters into a cavity 21 constituted by an upper mold 18 and a lower mold 19 (shown in FIG. 2) described later. Has a trapezoidal shape whose length is shorter than the length of the base.
【００１９】次に、このリ−ドフレ−ム１０を用いたＬ
ＳＩパッケ−ジの製造方法について説明する。図１
（ｂ）に示すように、このリ−ドフレ−ム１０のダイパ
ッド部１２には、半導体素子２がダイボンディングされ
る。次に、ダイボンディングされた半導体素子２とリ−
ドフレ−ム１０のリ−ド部１３とは、ワイヤボンディン
グによりワイヤ２０を用いて接続される。なお、このと
き、上記リ−ド部１３にワイヤ２０が接続される位置
は、上記突起部１７の設けられた位置よりも先端側とす
る。Next, L using this lead frame 10
A method of manufacturing the SI package will be described. Figure 1
As shown in (b), the semiconductor element 2 is die-bonded to the die pad portion 12 of the lead frame 10. Next, the die-bonded semiconductor element 2 and the lead
The lead portion 13 of the dframe 10 is connected by the wire 20 by wire bonding. At this time, the position at which the wire 20 is connected to the lead portion 13 is at the tip side of the position at which the protrusion 17 is provided.
【００２０】ワイヤボンディングが終了したならば、上
記リ−ドフレ−ム１０および半導体素子２は、図２
（ａ）に示すように、上型１８および下型１９とで構成
されるキャビティ２１内に投入される。なお、このとき
上記リ−ド部１３に設けられた突起１７のリ−ド部１３
の他端部側の面は、上記キャビティ２１の内面に当接す
るようになっている。When the wire bonding is completed, the lead frame 10 and the semiconductor element 2 are connected to each other as shown in FIG.
As shown in (a), it is put into a cavity 21 composed of an upper mold 18 and a lower mold 19. At this time, the lead portion 13 of the protrusion 17 provided on the lead portion 13 is
The surface on the other end side of is contacted with the inner surface of the cavity 21.
【００２１】なお、上記突起部１７の形状は台形状で側
面の形状が上記キャビティ２１の内面の傾斜に沿うよう
に設けられているので、上記キャビティ２１内に容易に
入り込みかつ上記キャビティ２１の内面に当接しやすい
ようになっている。Since the shape of the protrusion 17 is trapezoidal and the shape of the side surface is provided along the inclination of the inner surface of the cavity 21, it easily enters the cavity 21 and the inner surface of the cavity 21. It is easy to contact with.
【００２２】次に、このキャビティ２１内には、エポキ
シ樹脂が射出される。このことで、上記半導体素子２は
樹脂封止される。このとき、図２（ｂ）に拡大して示す
ように、上記上記上型１８と下型１９とリ−ド部１３と
の間に生じた隙間Ａは上記突起部１７により閉塞され、
このキャビティ２１内に射出されたエポキシ樹脂が上記
リ−ド部１３の後端部側に流出しないようになってい
る。樹脂封止が終了したｌＳＩパッケ−ジは、このキャ
ビティ２１内から取り出されたあと、上記リ−ド部１３
を折曲されることで完成する。Next, epoxy resin is injected into the cavity 21. As a result, the semiconductor element 2 is resin-sealed. At this time, as shown in FIG. 2 (b) in an enlarged manner, the gap A formed between the upper die 18, the lower die 19 and the lead portion 13 is closed by the projection portion 17,
The epoxy resin injected into the cavity 21 is prevented from flowing out to the rear end side of the lead portion 13. The resin package which has been sealed is taken out of the cavity 21 and then the lead portion 13 is formed.
It is completed by being folded.
【００２３】このような構成よれば、上記リ−ド部１３
の先端部に樹脂封止時に上記上型１８、下型１９と、リ
−ド部１３との隙間Ａを閉塞する突起部１７を設けたの
で、キャビティ２１ａ内に充満されたエポキシ樹脂が流
出することが有効に防止される。したがって、上記リ−
ド部３あるいは上型１８、下型１９にばりが付着するこ
とが有効に防止される。According to this structure, the lead portion 13 is provided.
Since the projection 17 that closes the gap A between the upper mold 18, the lower mold 19 and the lead portion 13 at the time of resin sealing is provided at the tip end of the, the epoxy resin filled in the cavity 21a flows out. Is effectively prevented. Therefore, the above
It is possible to effectively prevent burrs from adhering to the window portion 3 or the upper mold 18 and the lower mold 19.
【００２４】このことにより、製造されるＬＳＩパッケ
−ジの品質が向上すると共に歩留まりが向上する。ま
た、ばり取りの工程が不要になるのでこのＬＳＩパッケ
−ジの製造が容易になる効果もある。なお、この発明は
上記一実施例に限定されるものではなく、発明の要旨を
変更しない範囲で種々変形可能である。As a result, the quality of the manufactured LSI package is improved and the yield is improved. Further, since the deburring step is unnecessary, there is an effect that the manufacturing of this LSI package is facilitated. It should be noted that the present invention is not limited to the above-mentioned embodiment, and can be variously modified without changing the gist of the invention.
【００２５】例えば、上記一実施例では、上記絶縁テ−
プ１６を貼着することで上記リ−ド部１３の先端部に突
起部１７を設けたが、これに限定されるものではない。
例えば、図３に示すように、リ−ド部１３のプレスある
いは打ち抜き時に、上記リ−ド部１３の先端部に、この
リ−ド部１３と一体的に突起部１７を成形するようにし
ても良い。For example, in the above embodiment, the insulating tape is
Although the protrusion 17 is provided at the tip of the lead portion 13 by attaching the cap 16, the present invention is not limited to this.
For example, as shown in FIG. 3, when the lead portion 13 is pressed or punched, a protrusion 17 is formed integrally with the lead portion 13 at the tip of the lead portion 13. Is also good.
【００２６】また、図４に示すように、上記突起部１７
を上記リ−ド部１３の表面および裏面だけでなく、側面
にも形成されるように鍔状に形成するようにしても良
い。この突起部１７は、上記プレス加工時に一体的に形
成するようにしても良いし、上述したように絶縁テ−プ
１６等で成形するようにしても良い。このような構成で
あっても上記一実施例と略同様の効果を得ることが可能
になる。Further, as shown in FIG.
May be formed in a brim shape so as to be formed not only on the front surface and the back surface of the lead portion 13 but also on the side surface. The protrusion 17 may be integrally formed at the time of the press working, or may be formed of the insulating tape 16 or the like as described above. Even with such a configuration, it is possible to obtain substantially the same effect as that of the above-described embodiment.
【００２７】また、上記一実施例では、２方向にのみリ
−ド部１３が突出するＬＳＩパッケ−ジであったが、こ
れに限定されるものでなく４方向にリ−ド部１３が突出
するＬＳＩパッケ−ジ（いわゆるＱＦＰ）であってもよ
い。この場合には、上記ダイパッド部１２を囲むように
設けられたすべてのリ−ド部１３に上記突起部１７を設
けるようにする必要がある。Further, in the above-mentioned one embodiment, the LSI package is one in which the lead portion 13 projects in only two directions. However, the present invention is not limited to this, and the lead portion 13 projects in four directions. The LSI package (so-called QFP) may be used. In this case, it is necessary to provide the protrusions 17 on all the lead portions 13 provided so as to surround the die pad portion 12.
【００２８】[0028]
【発明の効果】以上述べたように、この発明の第１の構
成は、半導体素子がダイボンディングされるダイパッド
部と、先端をこのダイパッド部に対向させて設けられ上
記半導体素子にワイヤを介して接続されるリ−ド部とを
具備するリ−ドフレ−ムにおいて、上記リ−ド部の先端
部に突起部を設けたリ−ドフレ−ムである。As described above, according to the first configuration of the present invention, the die pad portion to which the semiconductor element is die bonded and the tip end facing the die pad portion are provided and the semiconductor element is connected to the semiconductor element via the wire. A lead frame having a lead portion to be connected, wherein the lead portion is provided with a protrusion at a tip portion thereof.
【００２９】第２の構成は、リ−ドフレ−ム上に半導体
素子を搭載し、このリ−ドフレ−ムのリ−ド部と半導体
素子とをワイヤボンディングした後、樹脂封止すること
でＬＳＩパッケ−ジを製造するＬＳＩパッケ−ジの製造
方法において、上記リ−ド部の先端部に、樹脂封止用金
型とリ−ド部との間に生じる隙間を閉塞する突起部を設
けたＬＳＩパッケ−ジの製造方法である。In the second configuration, the semiconductor element is mounted on the lead frame, the lead portion of the lead frame and the semiconductor element are wire-bonded, and then the resin is sealed to form an LSI. In a method for manufacturing an LSI package for manufacturing a package, a projection portion is provided at the tip of the lead portion to close a gap formed between the resin sealing mold and the lead portion. This is a method of manufacturing an LSI package.
【００３０】このような構成によれば、上記リ−ド部の
先端部に樹脂封止時に樹脂封止用金型とリ−ド部との隙
間を閉塞する突起部を設けたので、封止用樹脂が上記リ
−ド部の後端側に流出することが防止される。したがっ
て、上記リ−ド部あるいは金型にばりが付着することが
有効に防止される。According to this structure, since the tip portion of the lead portion is provided with the protrusion for closing the gap between the resin-sealing mold and the lead portion at the time of resin sealing, the sealing is performed. The resin for use is prevented from flowing out to the rear end side of the lead portion. Therefore, it is possible to effectively prevent the flash from adhering to the lead portion or the mold.
【００３１】このことにより、製造されるＬＳＩパッケ
−ジの品質が向上すると共に製品製造の歩留まりが向上
する。また、ばり取りの工程が不要になるのでこのＬＳ
Ｉパッケ−ジの製造が容易になる効果もある。As a result, the quality of the manufactured LSI package is improved and the yield of product manufacturing is improved. Also, since the deburring process is unnecessary, this LS
It also has the effect of facilitating the manufacture of the I package.
【図１】（ａ）は、この発明の一実施例を示す平面図、
（ｂ）は、同じく、製造工程を示す平面図。FIG. 1A is a plan view showing an embodiment of the present invention,
Similarly, (b) is a plan view showing a manufacturing process.
【図２】（ａ）は、同じく製造工程を示す縦断面図、
（ｂ）は、同じく拡大縦断面図。FIG. 2A is a vertical sectional view showing the same manufacturing process,
(B) is an enlarged vertical sectional view of the same.
【図３】他の実施例を示す平面図。FIG. 3 is a plan view showing another embodiment.
【図４】同じく他の実施例を示す平面図。FIG. 4 is a plan view showing another embodiment of the present invention.
【図５】（ａ）は、従来例を示す縦断面図、（ｂ）は、
同じく拡大縦断面図。5A is a vertical cross-sectional view showing a conventional example, and FIG.
Similarly, an enlarged vertical sectional view.
２…半導体素子、１０…リ−ドフレ−ム、１２…ダイパ
ッド部、１３…リ−ド部、１７…突起部、Ａ…隙間。2 ... Semiconductor element, 10 ... Lead frame, 12 ... Die pad portion, 13 ... Lead portion, 17 ... Projection portion, A ... Gap.
Claims (2)
イパッド部と、先端をこのダイパッド部に対向させて設
けられ上記半導体素子にワイヤを介して接続されるリ−
ド部とを具備するリ−ドフレ−ムにおいて、上記リ−ド
部の先端部に突起部を設けたことを特徴とするリ−ドフ
レ−ム。1. A die pad portion to which a semiconductor element is die-bonded, and a reel provided with its tip facing the die pad portion and connected to the semiconductor element via a wire.
A lead frame comprising a lead portion and a lead portion, wherein a projection portion is provided at a tip portion of the lead portion.
し、このリ−ドフレ−ムのリ−ド部と半導体素子とをワ
イヤボンディングした後、樹脂封止することでＬＳＩパ
ッケ−ジを製造するＬＳＩパッケ−ジの製造方法におい
て、上記リ−ド部の先端部に、樹脂封止用金型とリ−ド
部との間に生じる隙間を閉塞する突起部を設けたことを
特徴とするＬＳＩパッケ−ジの製造方法。2. An LSI package is obtained by mounting a semiconductor element on a lead frame, wire-bonding the lead portion of the lead frame and the semiconductor element, and then sealing with a resin. A method for manufacturing an LSI package to be manufactured is characterized in that a projection portion for closing a gap generated between the resin sealing die and the lead portion is provided at a tip portion of the lead portion. LSI package manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP766393A JPH06216293A (en) | 1993-01-20 | 1993-01-20 | Leadframe, and manufacture of lsi package using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP766393A JPH06216293A (en) | 1993-01-20 | 1993-01-20 | Leadframe, and manufacture of lsi package using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06216293A true JPH06216293A (en) | 1994-08-05 |
Family
ID=11672056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP766393A Pending JPH06216293A (en) | 1993-01-20 | 1993-01-20 | Leadframe, and manufacture of lsi package using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06216293A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107086183A (en) * | 2016-02-16 | 2017-08-22 | 富士电机株式会社 | The manufacture method and semiconductor module of semiconductor module |
-
1993
- 1993-01-20 JP JP766393A patent/JPH06216293A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107086183A (en) * | 2016-02-16 | 2017-08-22 | 富士电机株式会社 | The manufacture method and semiconductor module of semiconductor module |
| US10262948B2 (en) | 2016-02-16 | 2019-04-16 | Fuji Electric Co., Ltd. | Semiconductor module having outflow prevention external terminals |
| CN107086183B (en) * | 2016-02-16 | 2021-12-28 | 富士电机株式会社 | Method for manufacturing semiconductor module and semiconductor module |
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