JPH0621624A - Base board for mounted circuit - Google Patents

Base board for mounted circuit

Info

Publication number
JPH0621624A
JPH0621624A JP4176376A JP17637692A JPH0621624A JP H0621624 A JPH0621624 A JP H0621624A JP 4176376 A JP4176376 A JP 4176376A JP 17637692 A JP17637692 A JP 17637692A JP H0621624 A JPH0621624 A JP H0621624A
Authority
JP
Japan
Prior art keywords
mold
resist layer
integrated circuit
base board
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4176376A
Other languages
Japanese (ja)
Inventor
Shiro Yamashita
士郎 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4176376A priority Critical patent/JPH0621624A/en
Publication of JPH0621624A publication Critical patent/JPH0621624A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To increase density for mounting by dividing a resist layer into two layers and providing a difference in height to the opening of the resist layer to offset the expansion of a mold and besides forming such a structure as to dam up a mold by a frame produced from outside silk printing. CONSTITUTION:A semiconductor integrated circuit substrate 102 is bonded on a mounted circuit base board with a die-bonding agent 103, and an Al pad 104, 105 is connected with the integrated circuit substrate 102 with use of a wiring pattern 106, 107 and an Au wire 105, 109 on the mounted circuit base board. In such a mounting structure, a first and a second resist layer 110, 111 for electrically insulating a wiring pattern provided on a base board 101 are concentrically formed, thereby making it feasible to limit the expansion of a mold agent 112 to a small degree. Also, a mold frame 113 formed on a silk- printed layer is provided outside the opening of the second resist layer 111, thereby damming up the mold agent 112.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】半導体集積回路基板を直接実装回
路基板上に実装するＣＯＢ（Ｃｈｉｐ ＯｎＢｏａｒ
ｄ）技術に関する。[Industrial application] COB (Chip OnBoar) for directly mounting a semiconductor integrated circuit board on a circuit board
d) Regarding technology.

【０００２】[0002]

【従来の技術】図３に従来技術による実装図を示す。図
３において（ｂ）は（ａ）のＡ−Ａ’上での断面図であ
る。実装回路基板３０１上の半導体集積回路基板３０２
はダイボンディング剤３０３によって接着されている。
半導体集積回路基板３０２上のＡｌパッド３０４、３０
５は実装回路基板上の配線パターン３０６、３０７とＡ
ｕ線３０８、３０９によってそれぞれ電気的に接続され
ている。３１０は実装基板上の配線パターンを電気的に
絶縁するためのレジスト層である。半導体集積回路基板
３０２は表面の保護および耐湿性を向上させるためにモ
ールド剤３１１によって覆われている。このモールド剤
は塗布時には流動性が高く、モールド範囲を小さくする
ためにシルク印刷によってモールド枠３１２を形成して
いた。2. Description of the Related Art FIG. 3 shows a mounting diagram according to a conventional technique. 3B is a cross-sectional view taken along the line AA ′ in FIG. Semiconductor integrated circuit board 302 on mounted circuit board 301
Are bonded by a die bonding agent 303.
Al pads 304, 30 on the semiconductor integrated circuit substrate 302
5 is a wiring pattern 306, 307 and A on the mounting circuit board
They are electrically connected by u-lines 308 and 309, respectively. Reference numeral 310 is a resist layer for electrically insulating the wiring pattern on the mounting substrate. The semiconductor integrated circuit substrate 302 is covered with a molding agent 311 to protect the surface and improve moisture resistance. This mold agent has high fluidity at the time of application, and the mold frame 312 was formed by silk printing in order to reduce the mold range.

【０００３】[0003]

【発明が解決しようとする課題】上記従来技術におい
て、モールド剤が多めに塗布された場合にモールド剤が
枠をはみ出してしまい実装禁止領域にまで広がる恐れが
あった。本発明が解決すべき課題は、モールド塗布時の
モールド剤の広がりを小さくすることにある。In the above-mentioned conventional technique, when a large amount of the molding agent is applied, the molding agent may overflow the frame and spread to the mounting prohibited area. The problem to be solved by the present invention is to reduce the spread of the molding agent when applying the mold.

【０００４】[0004]

【課題を解決するための手段】モールド枠の内側に実装
回路基板の配線パターン間の絶縁を保つことを目的とし
たレジスト層を２層に分け、レジスト層の開口部に段差
をつけることによってモールドの広がりを吸収し、さら
に外側のシルク印刷による枠によってモールドをせき止
めるような構造としたことを特徴とする。[MEANS FOR SOLVING THE PROBLEMS] A mold is formed by dividing a resist layer inside a mold frame into two layers for the purpose of maintaining insulation between wiring patterns of a mounting circuit board, and forming a step in an opening of the resist layer. The feature is that the structure absorbs the spread of the mold and further holds the mold by the outer frame of silk printing.

【０００５】またシルク印刷による枠を２重にして内側
の枠からはみでても外側の枠によってモールドをせき止
めるような構造としたことを特徴とする。Further, the present invention is characterized in that the frame formed by silk printing is doubled so that the mold is held by the outer frame even if it sticks out from the inner frame.

【０００６】[0006]

【実施例】（実施例１）図１に本発明の第一の実施例を
示す。図１において（ｂ）は（ａ）のＡ−Ａ’上での断
面図である。実装回路基板１０１上の半導体集積回路基
板１０２はダイボンディング剤１０３によって接着され
ている。半導体集積回路基板１０２上のＡｌパッド１０
４、１０５は実装回路基板上の配線パターン１０６、１
０７とＡｕ線１０８、１０９によってそれぞれ電気的に
接続されている。１１０は実装基板上の配線パターンを
電気的に絶縁するための第一のレジスト層、１１１は第
二のレジスト層である。半導体集積回路基板１０２は表
面の保護および耐湿性を向上させるためにモールド剤１
１２によって覆われている。１１３はシルク印刷層で形
成されたモールド枠である。(Embodiment 1) FIG. 1 shows a first embodiment of the present invention. 1B is a cross-sectional view taken along the line AA ′ of FIG. The semiconductor integrated circuit board 102 on the mounting circuit board 101 is adhered by a die bonding agent 103. Al pad 10 on semiconductor integrated circuit substrate 102
4, 105 are wiring patterns 106, 1 on the mounting circuit board
07 and Au wires 108 and 109 are electrically connected to each other. 110 is a first resist layer for electrically insulating the wiring pattern on the mounting substrate, and 111 is a second resist layer. The semiconductor integrated circuit substrate 102 has a molding agent 1 for protecting the surface and improving the moisture resistance.
Covered by 12. Reference numeral 113 is a mold frame formed of a silk printing layer.

【０００７】以上のような構造にすれば、第一と第二の
レジスト層の段差が２０〜３０μｍ程度あるため、モー
ルド剤自身の粘性によってモールド剤１１２の広がりが
抑えられる。さらに外側のモールド枠１１３によってそ
れ以上のモールドの広がりを阻止できる。このことによ
り、設計されたモールド範囲よりモールド剤がはみ出す
ことがなく、実装領域を精密に制御でき、外装体を含め
たより高密度の実装が期待できる。With the above structure, since the step difference between the first and second resist layers is about 20 to 30 μm, the spreading of the molding agent 112 is suppressed by the viscosity of the molding agent itself. Further, the outer mold frame 113 can prevent further expansion of the mold. As a result, the molding agent does not overflow from the designed molding range, the mounting area can be precisely controlled, and higher density mounting including the outer package can be expected.

【０００８】（実施例２）図２に本発明の第二の実施例
を示す。図２において（ｂ）は（ａ）のＡ−Ａ’上での
断面図である。実装回路基板２０１上の半導体集積回路
基板２０２はダイボンディング剤２０３によって接着さ
れている。半導体集積回路基板２０２上のＡｌパッド２
０４、２０５は実装回路基板上の配線パターン２０６、
２０７とＡｕ線２０８、２０９によってそれぞれ電気的
に接続されている。２１０は実装基板上の配線パターン
を電気的に絶縁するためのレジスト層である。半導体集
積回路基板２０２は表面の保護および耐湿性を向上させ
るためにモールド剤２１１によって覆われている。２１
２はシルク印刷層で形成された内側のモールド枠、２１
３は同様にシルク印刷層で形成された外側のモールド枠
である。(Embodiment 2) FIG. 2 shows a second embodiment of the present invention. 2B is a sectional view taken along the line AA ′ in FIG. The semiconductor integrated circuit board 202 on the mounting circuit board 201 is adhered by a die bonding agent 203. Al pad 2 on semiconductor integrated circuit substrate 202
04 and 205 are wiring patterns 206 on the mounting circuit board,
207 and Au wires 208 and 209 are electrically connected to each other. 210 is a resist layer for electrically insulating the wiring pattern on the mounting substrate. The semiconductor integrated circuit substrate 202 is covered with a molding agent 211 in order to protect the surface and improve the moisture resistance. 21
2 is an inner mold frame formed of a silk printing layer, 21
3 is an outer mold frame which is also formed of a silk printing layer.

【０００９】以上のような構造にすれば、塗布されたモ
ールド剤はまず内側のモールド枠によって広がりを抑え
られる。さらに内側のモールド枠をのりこえた場合で
も、外側のモールド枠によってそれ以上のモールド剤の
広がりを阻止できる。このことにより、上記第一の実施
例と同様に外装体を含めたより高密度の実装が期待でき
る。With the above-mentioned structure, the applied molding agent can be prevented from spreading by the inner molding frame. Even when the inner mold frame is overrun, the outer mold frame can prevent further spreading of the molding agent. As a result, higher density mounting including the outer package can be expected as in the first embodiment.

【００１０】[0010]

【発明の効果】本発明によれば、半導体集積回路基板を
保護するためのモールド剤の広がりを小さくすることが
可能になり、実装密度の向上が期待できる。また実装基
板上に段差を多く設けることにより、より流動性の高い
モールド剤においてもモールド剤の広がりを小さくする
ことが可能である。According to the present invention, it is possible to reduce the spread of the molding agent for protecting the semiconductor integrated circuit substrate, and it is expected that the packaging density is improved. Further, by providing a large number of steps on the mounting substrate, it is possible to reduce the spread of the molding agent even in the case of the molding agent having higher fluidity.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の第一の実施例を示す図。FIG. 1 is a diagram showing a first embodiment of the present invention.

【図２】 本発明の第二の実施例を示す図。FIG. 2 is a diagram showing a second embodiment of the present invention.

【図３】 従来の実施例を示す図。FIG. 3 is a diagram showing a conventional embodiment.

【符号の説明】 １０１、２０１、３０１ 実装回路基板 １０２、２０２、３０２ 半導体集積回路基板 １０３、２０３、３０３ ダイボンディング剤 １０４、１０５、２０４、２０５、３０４、 Ａｌパッド ３０５ １０６、１０７、２０６、２０７、３０６、 Ａｕ線 ３０７ １０８、１０９、２０８、２０９、３０８、 配線パターン ３０９ １１０、１１１、２１０、３１０ レジスト層 １１２、２１１、３１１ モールド剤 １１３、２１２、２１３、３１２ モールド枠[Description of Reference Signs] 101, 201, 301 Mounted Circuit Board 102, 202, 302 Semiconductor Integrated Circuit Board 103, 203, 303 Die Bonding Agent 104, 105, 204, 205, 304, Al Pad 305 106, 107, 206, 207 , 306, Au wire 307 108, 109, 208, 209, 308, Wiring pattern 309 110, 111, 210, 310 Resist layer 112, 211, 311 Molding agent 113, 212, 213, 312 Mold frame

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】第一のレジスト層、第二のレジスト層、シ
ルク印刷層を有し、半導体集積回路基板を搭載する部分
に第一のレジスト層の開口部を有し、前記第一のレジス
ト層の開口部の外側に第二のレジスト層の開口部を有
し、前記第二のレジスト層の開口部の外側にシルク印刷
層によって枠を設けたことを特徴とする実装回路基板。1. A first resist layer, a second resist layer, and a silk-printing layer, the opening of the first resist layer being provided in a portion where a semiconductor integrated circuit board is mounted, and the first resist. A mounting circuit board having an opening of a second resist layer outside the opening of the layer, wherein a frame is provided outside the opening of the second resist layer by a silk printing layer. 【請求項２】レジスト層、シルク印刷層を有し、半導体
集積回路基板を搭載する部分にレジスト層の開口部を有
し、前記レジスト層の開口部の外側にシルク印刷層によ
って２重の枠を設けたことを特徴とする実装回路基板。2. A resist frame and a silk-printed layer, an opening of the resist layer is provided in a portion where a semiconductor integrated circuit board is mounted, and a double frame is formed outside the opening of the resist layer by the silk-printed layer. A mounting circuit board comprising:
JP4176376A 1992-07-03 1992-07-03 Base board for mounted circuit Pending JPH0621624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4176376A JPH0621624A (en) 1992-07-03 1992-07-03 Base board for mounted circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4176376A JPH0621624A (en) 1992-07-03 1992-07-03 Base board for mounted circuit

Publications (1)

Publication Number Publication Date
JPH0621624A true JPH0621624A (en) 1994-01-28

Family

ID=16012554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4176376A Pending JPH0621624A (en) 1992-07-03 1992-07-03 Base board for mounted circuit

Country Status (1)

Country Link
JP (1) JPH0621624A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6409715B1 (en) 1999-06-09 2002-06-25 Uni-Charm Corporation Disposable absorbent article
US6497693B1 (en) 1999-03-05 2002-12-24 Uni-Charm Corporation Disposable undergarment
JP2004055847A (en) * 2002-07-19 2004-02-19 Matsushita Electric Works Ltd Circuit-sealing structure and fire detector
US8475427B2 (en) 2002-02-20 2013-07-02 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
US8563802B2 (en) 2008-03-04 2013-10-22 Unicharm Corporation Absorbent article with pattern
US8716548B2 (en) 2002-02-20 2014-05-06 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
JP2018182062A (en) * 2017-04-13 2018-11-15 ローム株式会社 Semiconductor light-emitting device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6497693B1 (en) 1999-03-05 2002-12-24 Uni-Charm Corporation Disposable undergarment
US6409715B1 (en) 1999-06-09 2002-06-25 Uni-Charm Corporation Disposable absorbent article
US8475427B2 (en) 2002-02-20 2013-07-02 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
US8716548B2 (en) 2002-02-20 2014-05-06 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
US9259367B2 (en) 2002-02-20 2016-02-16 The Procter & Gamble Disposable absorbent article designed to facilitate an easy change
US11083646B2 (en) 2002-02-20 2021-08-10 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
JP2004055847A (en) * 2002-07-19 2004-02-19 Matsushita Electric Works Ltd Circuit-sealing structure and fire detector
US8563802B2 (en) 2008-03-04 2013-10-22 Unicharm Corporation Absorbent article with pattern
JP2018182062A (en) * 2017-04-13 2018-11-15 ローム株式会社 Semiconductor light-emitting device

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