JPH0621624A - Base board for mounted circuit - Google Patents

Base board for mounted circuit

Info

Publication number
JPH0621624A
JPH0621624A JP17637692A JP17637692A JPH0621624A JP H0621624 A JPH0621624 A JP H0621624A JP 17637692 A JP17637692 A JP 17637692A JP 17637692 A JP17637692 A JP 17637692A JP H0621624 A JPH0621624 A JP H0621624A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
mold
resist layer
mounting
base board
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17637692A
Other languages
Japanese (ja)
Inventor
Shiro Yamashita
士郎 山下
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PURPOSE:To increase density for mounting by dividing a resist layer into two layers and providing a difference in height to the opening of the resist layer to offset the expansion of a mold and besides forming such a structure as to dam up a mold by a frame produced from outside silk printing. CONSTITUTION:A semiconductor integrated circuit substrate 102 is bonded on a mounted circuit base board with a die-bonding agent 103, and an Al pad 104, 105 is connected with the integrated circuit substrate 102 with use of a wiring pattern 106, 107 and an Au wire 105, 109 on the mounted circuit base board. In such a mounting structure, a first and a second resist layer 110, 111 for electrically insulating a wiring pattern provided on a base board 101 are concentrically formed, thereby making it feasible to limit the expansion of a mold agent 112 to a small degree. Also, a mold frame 113 formed on a silk- printed layer is provided outside the opening of the second resist layer 111, thereby damming up the mold agent 112.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】半導体集積回路基板を直接実装回路基板上に実装するCOB(Chip OnBoar BACKGROUND OF THE COB mounting the semiconductor integrated circuit board directly mounted on a circuit board (Chip OnBoar
d)技術に関する。 d) related to technology.

【0002】 [0002]

【従来の技術】図3に従来技術による実装図を示す。 It shows a mounting diagram according Conventional art Figure 3. 図3において(b)は(a)のA−A'上での断面図である。 In FIG. 3 (b) is a sectional view of the on A-A 'of (a). 実装回路基板301上の半導体集積回路基板302 Mounting circuit semiconductor integrated circuit substrate 302 on the substrate 301
はダイボンディング剤303によって接着されている。 They are bonded by die bonding agent 303.
半導体集積回路基板302上のAlパッド304、30 Al pads on the semiconductor integrated circuit substrate 302 304,30
5は実装回路基板上の配線パターン306、307とA 5 on the mounting circuit board wiring patterns 306, 307 and A
u線308、309によってそれぞれ電気的に接続されている。 Are electrically connected to each other by u line 308 and 309. 310は実装基板上の配線パターンを電気的に絶縁するためのレジスト層である。 310 is a resist layer for electrically insulating the wiring pattern on the mounting board. 半導体集積回路基板302は表面の保護および耐湿性を向上させるためにモールド剤311によって覆われている。 The semiconductor integrated circuit substrate 302 is covered by the mold agent 311 in order to improve protection and moisture resistance of the surface. このモールド剤は塗布時には流動性が高く、モールド範囲を小さくするためにシルク印刷によってモールド枠312を形成していた。 The mold agent has high flowability at the time of coating and to form a mold frame 312 by silk printing in order to reduce the mold ranges.

【0003】 [0003]

【発明が解決しようとする課題】上記従来技術において、モールド剤が多めに塗布された場合にモールド剤が枠をはみ出してしまい実装禁止領域にまで広がる恐れがあった。 In THE INVENTION to be solved INVENTION The above prior art, the mold material when the mold material is larger amount applied there is a risk that extends to the mounting prohibition areas will protrude a frame. 本発明が解決すべき課題は、モールド塗布時のモールド剤の広がりを小さくすることにある。 Problems to be solved by the present invention is is to reduce the spread of mold agent at the time of molding the coating.

【0004】 [0004]

【課題を解決するための手段】モールド枠の内側に実装回路基板の配線パターン間の絶縁を保つことを目的としたレジスト層を2層に分け、レジスト層の開口部に段差をつけることによってモールドの広がりを吸収し、さらに外側のシルク印刷による枠によってモールドをせき止めるような構造としたことを特徴とする。 Means for Solving the Problems] The resist layer for the purpose of keeping the insulation between the wiring pattern of the circuit board package inside the mold frame is divided into two layers, molded by placing a step in the opening of the resist layer absorbs spread, further characterized in that it has such a structure that damming the mold by the frame according to the outside of the silk printing.

【0005】またシルク印刷による枠を2重にして内側の枠からはみでても外側の枠によってモールドをせき止めるような構造としたことを特徴とする。 [0005] and wherein also protrudes from the inside of the frame to the frame by silk printing doubly and by an outer frame structure as damming the mold.

【0006】 [0006]

【実施例】(実施例1)図1に本発明の第一の実施例を示す。 EXAMPLES (Example 1) shows a first embodiment of the present invention in FIG. 図1において(b)は(a)のA−A'上での断面図である。 In FIG. 1 (b) is a sectional view of the on A-A 'of (a). 実装回路基板101上の半導体集積回路基板102はダイボンディング剤103によって接着されている。 The semiconductor integrated circuit substrate 102 on the mounting circuit board 101 is bonded by die bonding agent 103. 半導体集積回路基板102上のAlパッド10 Al pads 10 on the semiconductor integrated circuit substrate 102
4、105は実装回路基板上の配線パターン106、1 4,105 is on the mounting circuit board wiring patterns 106,
07とAu線108、109によってそれぞれ電気的に接続されている。 They are electrically connected to each other by 07 and the Au wire 108, 109. 110は実装基板上の配線パターンを電気的に絶縁するための第一のレジスト層、111は第二のレジスト層である。 110 The first resist layer for electrically insulating the wiring pattern on the mounting board, 111 is a second resist layer. 半導体集積回路基板102は表面の保護および耐湿性を向上させるためにモールド剤1 The semiconductor integrated circuit substrate 102 is molded agent 1 in order to improve protection and moisture resistance of the surface
12によって覆われている。 It is covered by 12. 113はシルク印刷層で形成されたモールド枠である。 113 is a mold frame formed by silk printing layer.

【0007】以上のような構造にすれば、第一と第二のレジスト層の段差が20〜30μm程度あるため、モールド剤自身の粘性によってモールド剤112の広がりが抑えられる。 If the [0007] above-described structure, the step of the first and second resist layer due to the order of 20 to 30 [mu] m, the spread of the molding material 112 is suppressed by the mold agent itself viscous. さらに外側のモールド枠113によってそれ以上のモールドの広がりを阻止できる。 Furthermore it prevents the spread of more mold by an outer mold frame 113. このことにより、設計されたモールド範囲よりモールド剤がはみ出すことがなく、実装領域を精密に制御でき、外装体を含めたより高密度の実装が期待できる。 Thus, without mold agent protrudes from the mold ranges designed, can precisely control the mounting area can be expected density mounting than including exterior body.

【0008】(実施例2)図2に本発明の第二の実施例を示す。 [0008] A second embodiment of the present invention (Embodiment 2) FIG. 図2において(b)は(a)のA−A'上での断面図である。 In FIG. 2 (b) is a sectional view of the on A-A 'of (a). 実装回路基板201上の半導体集積回路基板202はダイボンディング剤203によって接着されている。 The semiconductor integrated circuit substrate 202 on the mounting circuit board 201 is bonded by die bonding agent 203. 半導体集積回路基板202上のAlパッド2 Al pad 2 on the semiconductor integrated circuit substrate 202
04、205は実装回路基板上の配線パターン206、 04,205 is on the mounting circuit board wiring patterns 206,
207とAu線208、209によってそれぞれ電気的に接続されている。 They are electrically connected to each other by 207 and the Au wire 208 and 209. 210は実装基板上の配線パターンを電気的に絶縁するためのレジスト層である。 210 is a resist layer for electrically insulating the wiring pattern on the mounting board. 半導体集積回路基板202は表面の保護および耐湿性を向上させるためにモールド剤211によって覆われている。 The semiconductor integrated circuit substrate 202 is covered by the mold agent 211 in order to improve protection and moisture resistance of the surface. 21 21
2はシルク印刷層で形成された内側のモールド枠、21 2 the mold frame inside which is formed by silk printing layer, 21
3は同様にシルク印刷層で形成された外側のモールド枠である。 3 is a mold frame of the outer formed by silk printing layer as well.

【0009】以上のような構造にすれば、塗布されたモールド剤はまず内側のモールド枠によって広がりを抑えられる。 [0009] When the structure described above, the coated mold agent is first suppressed the spread by the inner mold frame. さらに内側のモールド枠をのりこえた場合でも、外側のモールド枠によってそれ以上のモールド剤の広がりを阻止できる。 Even when further survived inside the mold frame may prevent the spread of more mold agent by the outer mold frame. このことにより、上記第一の実施例と同様に外装体を含めたより高密度の実装が期待できる。 Thus, it can be expected that high-density mounting than including exterior body in the same manner as in the first embodiment.

【0010】 [0010]

【発明の効果】本発明によれば、半導体集積回路基板を保護するためのモールド剤の広がりを小さくすることが可能になり、実装密度の向上が期待できる。 According to the present invention, it is possible to reduce the spread of mold agents for protecting the semiconductor integrated circuit substrate, the improvement of the mounting density can be expected. また実装基板上に段差を多く設けることにより、より流動性の高いモールド剤においてもモールド剤の広がりを小さくすることが可能である。 In addition, by providing a lot of steps on a mounting substrate, it is possible also to reduce the spread of mold agent in a more highly liquid mold agent.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の第一の実施例を示す図。 It shows a first embodiment of the present invention; FIG.

【図2】 本発明の第二の実施例を示す図。 It shows a second embodiment of the present invention; FIG.

【図3】 従来の実施例を示す図。 FIG. 3 shows a conventional example.

【符号の説明】 101、201、301 実装回路基板 102、202、302 半導体集積回路基板 103、203、303 ダイボンディング剤 104、105、204、205、304、 Alパッド 305 106、107、206、207、306、 Au線 307 108、109、208、209、308、 配線パターン 309 110、111、210、310 レジスト層 112、211、311 モールド剤 113、212、213、312 モールド枠 [EXPLANATION OF SYMBOLS] 101, 201, 301 mounting the circuit board 102, 202, 302 a semiconductor integrated circuit substrate 103, 203, 303, die bonding agent 104,105,204,205,304, Al pad 305 106,107,206,207 , 306, Au wire 307 108,109,208,209,308, wiring patterns 309 110,111,210,310 resist layer 112,211,311 mold agent 113,212,213,312 mold frame

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】第一のレジスト層、第二のレジスト層、シルク印刷層を有し、半導体集積回路基板を搭載する部分に第一のレジスト層の開口部を有し、前記第一のレジスト層の開口部の外側に第二のレジスト層の開口部を有し、前記第二のレジスト層の開口部の外側にシルク印刷層によって枠を設けたことを特徴とする実装回路基板。 1. A first resist layer, the second resist layer has a silk printing layer, the portion for mounting a semiconductor integrated circuit board has an opening of the first resist layer, the first resist mounting the circuit board, characterized in that an opening of the outside second resist layer of the opening of the layer, provided the frame by silk printing layer outside the opening of the second resist layer.
  2. 【請求項2】レジスト層、シルク印刷層を有し、半導体集積回路基板を搭載する部分にレジスト層の開口部を有し、前記レジスト層の開口部の外側にシルク印刷層によって2重の枠を設けたことを特徴とする実装回路基板。 2. A resist layer has a silk print layer has an opening of the resist layer in the portion for mounting a semiconductor integrated circuit board, a double frame by serigraph layer outside the opening of the resist layer mounting the circuit board, characterized in that the provided.
JP17637692A 1992-07-03 1992-07-03 Base board for mounted circuit Pending JPH0621624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17637692A JPH0621624A (en) 1992-07-03 1992-07-03 Base board for mounted circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17637692A JPH0621624A (en) 1992-07-03 1992-07-03 Base board for mounted circuit

Publications (1)

Publication Number Publication Date
JPH0621624A true true JPH0621624A (en) 1994-01-28

Family

ID=16012554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17637692A Pending JPH0621624A (en) 1992-07-03 1992-07-03 Base board for mounted circuit

Country Status (1)

Country Link
JP (1) JPH0621624A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6409715B1 (en) 1999-06-09 2002-06-25 Uni-Charm Corporation Disposable absorbent article
US6497693B1 (en) 1999-03-05 2002-12-24 Uni-Charm Corporation Disposable undergarment
US8475427B2 (en) 2002-02-20 2013-07-02 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
US8563802B2 (en) 2008-03-04 2013-10-22 Unicharm Corporation Absorbent article with pattern
US8716548B2 (en) 2002-02-20 2014-05-06 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6497693B1 (en) 1999-03-05 2002-12-24 Uni-Charm Corporation Disposable undergarment
US6409715B1 (en) 1999-06-09 2002-06-25 Uni-Charm Corporation Disposable absorbent article
US8475427B2 (en) 2002-02-20 2013-07-02 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
US8716548B2 (en) 2002-02-20 2014-05-06 The Procter & Gamble Company Disposable absorbent article designed to facilitate an easy change
US9259367B2 (en) 2002-02-20 2016-02-16 The Procter & Gamble Disposable absorbent article designed to facilitate an easy change
US8563802B2 (en) 2008-03-04 2013-10-22 Unicharm Corporation Absorbent article with pattern

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