JPH06216190A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06216190A JPH06216190A JP50A JP2193393A JPH06216190A JP H06216190 A JPH06216190 A JP H06216190A JP 50 A JP50 A JP 50A JP 2193393 A JP2193393 A JP 2193393A JP H06216190 A JPH06216190 A JP H06216190A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- film
- semiconductor device
- wiring
- layer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
にボンディングパッドの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a bonding pad.
【０００２】[0002]
【従来の技術】ＬＳＩチップ上には、チップ上の端子と
パッケージのリードとの間をボンディングワイヤで接続
するために、ボンディングパッドが設けられている。図
８は、従来の半導体装置におけるボンディングパッドの
製造工程を説明するための断面図と平面図である。最上
層配線を形成するに先立って、通常の方法により下地工
程および下層配線層（例えば、３層配線の半導体装置の
場合であれば、２層の配線層まで）形成工程が実行され
る。2. Description of the Related Art Bonding pads are provided on an LSI chip for connecting terminals on the chip and leads of a package with bonding wires. FIG. 8 is a cross-sectional view and a plan view for explaining a manufacturing process of a bonding pad in a conventional semiconductor device. Prior to forming the uppermost layer wiring, an underlying step and a lower layer wiring layer (for example, in the case of a semiconductor device having three layer wiring, up to two wiring layers) are formed by a usual method.
【０００３】その後、さらに最上層配線と下層とを絶縁
するための層間絶縁膜１を形成し、層間絶縁膜１に下層
配線と上層配線とを接続するためのビアホールを形成す
る。続いて、最上層配線を形成するための金属膜をスパ
ッタ法により堆積する。その後、フォトリソグラフィ技
法により金属膜上に選択的にフォトレジスト５ｇを設
け、これをマスクにリアクティブイオンエッチング（Ｒ
ＩＥ）法により金属膜をパターニングして、最上層配線
２とボンディングパッド３とを形成する［図８の
（ａ）］。After that, an interlayer insulating film 1 for insulating the uppermost layer wiring and the lower layer is further formed, and a via hole for connecting the lower layer wiring and the upper layer wiring is formed in the interlayer insulating film 1. Then, a metal film for forming the uppermost wiring is deposited by the sputtering method. After that, a photoresist 5g is selectively provided on the metal film by a photolithography technique, and using this as a mask, reactive ion etching (R
The metal film is patterned by the IE) method to form the uppermost layer wiring 2 and the bonding pad 3 [(a) of FIG. 8].
【０００４】次に、化学気相成長（ＣＶＤ）法により全
面にＳｉ3 Ｎ4 を堆積してカバー絶縁膜４を形成し、そ
の後、図示されていないフォトレジストをマスクにボン
ディングパッド上のＳｉ3 Ｎ4 膜をＲＩＥ法により除去
して、カバー絶縁膜４にカバー開口部４ａを形成する
［図８の（ｂ）、（ｃ）］。Next, Si 3 N 4 is deposited on the entire surface by chemical vapor deposition (CVD) to form a cover insulating film 4, and then Si 3 on the bonding pad is masked with a photoresist (not shown) as a mask. The N 4 film is removed by the RIE method to form the cover opening 4a in the cover insulating film 4 [(b) and (c) of FIG. 8].
【０００５】[0005]
【発明が解決しようとする課題】半導体集積回路装置に
おいて、配線層の厚さは回路動作に必要な電流と品質保
障上配線材料が許容する電流密度により決定される。と
ころで、メーンフレームやＬＳＩテスタ、計測器等の高
速動作を要求される電子機器の実現に不可欠なＥＣＬ−
ＲＡＭ、ＥＣＬ−ゲートアレイ等の超高速ＬＳＩでは、
その高速動作のために大電流が要求され、２μｍ以下の
薄い配線では電位降下が問題となるため、電源線を構成
する最上層配線では２μｍを超える厚い配線が用いられ
ている。而して、従来例ではボンディングパッドは、最
上層配線の末端を大面積の島領域とすることにより形成
していたため、この場合ボンディングパッドの厚さは最
上層配線と等しい２μｍ以上となる。ところが、配線お
よびボンディングパッドの材料としてアルミニウムを用
いた場合、ボンディングパッドの膜厚が厚いとワイヤボ
ンディングを行うときにボンディングパッドの表面部分
が削られて、図９の（ａ）、（ｂ）に示されるように、
ウイスカ状のアルミニウムの屑７（以下、アルミ屑７と
いう）が発生し、これが不良発生の原因を与えていた。In the semiconductor integrated circuit device, the thickness of the wiring layer is determined by the current required for circuit operation and the current density allowed by the wiring material for quality assurance. By the way, the ECL- which is indispensable for the realization of electronic devices such as mainframes, LSI testers, and measuring instruments that require high-speed operation
In ultra high speed LSI such as RAM and ECL-gate array,
A large current is required for the high-speed operation, and a potential drop is a problem in a thin wiring of 2 μm or less. Therefore, a thick wiring exceeding 2 μm is used for the uppermost layer wiring constituting the power supply line. Thus, in the conventional example, the bonding pad is formed by forming the large-area island region at the end of the uppermost layer wiring, and in this case, the thickness of the bonding pad is 2 μm or more, which is equal to that of the uppermost layer wiring. However, when aluminum is used as the material of the wiring and the bonding pad, if the film thickness of the bonding pad is large, the surface portion of the bonding pad is scraped when wire bonding is performed, resulting in (a) and (b) of FIG. As shown
Whisker-like aluminum scraps 7 (hereinafter referred to as aluminum scraps 7) were generated, which caused the defects.
【０００６】本発明者等は、不良解析の過程において、
アルミ屑による不良率がボンディングパッドの膜厚と密
接な関係を持つことを見いだした。すなわち、図１０の
グラフに示されるように、ボンディングパッドの膜厚の
増加に伴いアルミ屑に起因する不良率が増加するのであ
る。ここで注目すべきことはボンディングパッドの膜厚
が２．０μｍを超えると急激に不良率が増加することで
あり、１．８μｍ以下では不良率がなだらかに減少する
ことである。In the process of failure analysis, the present inventors
It was found that the defective rate due to aluminum scrap has a close relationship with the film thickness of the bonding pad. That is, as shown in the graph of FIG. 10, as the film thickness of the bonding pad increases, the defective rate due to aluminum scrap increases. What should be noted here is that the defective rate rapidly increases when the thickness of the bonding pad exceeds 2.0 μm, and the defective rate gradually decreases when the thickness of the bonding pad is 1.8 μm or less.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置で
は、最上層配線が２μｍ以上の膜厚の金属膜により形成
され、これと接続されたボンディングパッドの全体もし
くは主要部の膜厚が、１．８μｍ以下になされている。In the semiconductor device of the present invention, the uppermost layer wiring is formed of a metal film having a thickness of 2 μm or more, and the bonding pad connected to the uppermost wiring has a thickness of 1 or less. It is less than 8 μm.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１の（ａ）は、本発明の第１の実施例を
示す断面図であり、図１の（ｂ）はその平面図である。
本実施例では、層間絶縁膜１上に配置される最上層配線
２は、故意に添加された不純物を有しないアルミニウム
（いわゆるピュアアルミ）を用いた膜厚２．４μｍの金
属膜により形成され、一方、ボンディングパッド３はそ
の全体が１．３μｍの厚さになされている。半導体装置
の表面はカバー絶縁膜４により覆われるが、ボンディン
グパッド３の一部の表面は、カバー絶縁膜４に形成され
たカバー開口部４ａにより露出している。図１の（ｃ）
は、本実施例のボンディングパッドにワイヤ６をボンデ
ィングした状態を示す断面図である。同図に示されるよ
うに、ボンディングパッドの膜厚が１．３μｍと薄いた
め、パッドが軟らかいピュアアルミによって形成されて
いてもアルミ屑が発生することはない。Embodiments of the present invention will now be described with reference to the drawings. 1A is a sectional view showing a first embodiment of the present invention, and FIG. 1B is a plan view thereof.
In this embodiment, the uppermost layer wiring 2 arranged on the interlayer insulating film 1 is formed of a metal film having a thickness of 2.4 μm using aluminum (so-called pure aluminum) that does not have impurities intentionally added, On the other hand, the entire bonding pad 3 has a thickness of 1.3 μm. The surface of the semiconductor device is covered with the cover insulating film 4, but a part of the surface of the bonding pad 3 is exposed by the cover opening 4 a formed in the cover insulating film 4. Figure 1 (c)
FIG. 4 is a cross-sectional view showing a state in which a wire 6 is bonded to the bonding pad of this embodiment. As shown in the figure, since the thickness of the bonding pad is as thin as 1.3 μm, aluminum scraps are not generated even if the pad is made of soft pure aluminum.
【０００９】図２の（ａ）は、本発明の第２の実施例を
示す断面図であり、図２の（ｂ）はその平面図である。
本実施例では、ボンディングパッド３のうち、カバー絶
縁膜４に形成されたカバー開口部４ａから露出している
部分だけが１．３μｍと薄くなされている（他の部分の
膜厚は２．４μｍ）。本実施例でも先の実施例の場合と
同様の効果を奏することができる。FIG. 2A is a sectional view showing a second embodiment of the present invention, and FIG. 2B is a plan view thereof.
In this embodiment, only the portion of the bonding pad 3 exposed from the cover opening 4a formed in the cover insulating film 4 is thinned to 1.3 μm (the film thickness of other portions is 2.4 μm). ). In this embodiment, the same effect as in the previous embodiment can be obtained.
【００１０】図３は、本発明の第１の実施例（図１の実
施例）の第１の製造方法を説明するための工程断面図で
ある。下地工程および下層配線形成工程の終了した半導
体基板にたいし、さらに上層配線と下層配線とを絶縁す
るための層間絶縁膜１を形成し、必要に応じて層間絶縁
膜１に上層配線と下層配線とを接続するためのビアホー
ルを形成した後、最上層配線およびボンディングパッド
を形成するためのアルミニウム膜をスパッタ法により膜
厚２．４μｍに堆積した。続いて、フォトリソグラフィ
法によりフォトレジスト５ａを形成しこれをマスクにＲ
ＩＥ法によりアルミニウム膜をパターニングして最上層
配線２とボンディングパッド３を形成した［図３の
（ａ）］。FIG. 3 is a process sectional view for explaining a first manufacturing method of the first embodiment (embodiment of FIG. 1) of the present invention. An interlayer insulating film 1 for insulating the upper layer wiring and the lower layer wiring from each other is formed on the semiconductor substrate on which the base process and the lower layer wiring forming process have been completed, and the upper layer wiring and the lower layer wiring are formed on the interlayer insulating film 1 as necessary. After forming a via hole for connecting to and, an aluminum film for forming an uppermost layer wiring and a bonding pad was deposited to a film thickness of 2.4 μm by a sputtering method. Then, a photoresist 5a is formed by photolithography and R is used as a mask.
The aluminum film was patterned by the IE method to form the uppermost wiring 2 and the bonding pad 3 [(a) of FIG. 3].
【００１１】その後、フォトレジスト５ａを除去し、新
たにボンディングパッド３上に開口を有するフォトレジ
スト５ｂを設け、これをマスクにＲＩＥ法によりボンデ
ィングパッドの上面を１．１μｍ程度エッチングしてそ
の膜厚を１．３μｍとした［図３の（ｂ）］。続いて、
プラズマＣＶＤ法により全面にＳｉ3 Ｎ4 を堆積してカ
バー絶縁膜４を形成し、ボンディングパッド上の窒化膜
をＲＩＥ法により除去してカバー絶縁膜４にカバー開口
部４ａを形成した［図３の（ｃ）］。After that, the photoresist 5a is removed, and a photoresist 5b having an opening is newly provided on the bonding pad 3. Using this as a mask, the upper surface of the bonding pad is etched by about 1.1 μm by the RIE method, and the film thickness thereof is formed. Was 1.3 μm [(b) of FIG. 3]. continue,
Si 3 N 4 was deposited on the entire surface by the plasma CVD method to form the cover insulating film 4, and the nitride film on the bonding pad was removed by the RIE method to form the cover opening 4a in the cover insulating film 4 [FIG. (C)].
【００１２】図４は、本発明の第１の実施例の第２の製
造方法を説明するための工程断面図である。図３の場合
と同様に、層間絶縁膜１上に膜厚２．４μｍのアルミニ
ウム膜２ａを堆積し、続いて、アルミニウム膜２ａのボ
ンディングパッド形成予定領域上に開口を有するフォト
レジスト５ｃを形成する。フォトレジスト５ｃをマスク
にＲＩＥ法によりアルミニウム膜２ａの表面をエッチン
グしてその膜厚を１．３μｍとする［図４の（ａ）］。
フォトレジスト５ｃを除去した後、新たに設けたフォト
レジスト５ｄをマスクにアルミニウム膜２ａを選択的に
エッチング除去して最上層配線２とボンディングパッド
３とを形成する［図４の（ｂ）］。続いて、全面を被覆
するカバー絶縁膜４を形成しボンディングパッド上のカ
バー絶縁膜を選択的に除去してカバー開口部４ａを形成
する［図４の（ｃ）］。FIG. 4 is a process sectional view for explaining a second manufacturing method of the first embodiment of the present invention. Similar to the case of FIG. 3, an aluminum film 2a having a film thickness of 2.4 μm is deposited on the interlayer insulating film 1, and subsequently, a photoresist 5c having an opening is formed on the bonding pad formation planned region of the aluminum film 2a. . The surface of the aluminum film 2a is etched by the RIE method using the photoresist 5c as a mask to make the film thickness 1.3 μm [(a) of FIG. 4].
After removing the photoresist 5c, the aluminum film 2a is selectively removed by etching using the newly provided photoresist 5d as a mask to form the uppermost layer wiring 2 and the bonding pad 3 [(b) of FIG. 4]. Then, the cover insulating film 4 covering the entire surface is formed, and the cover insulating film on the bonding pad is selectively removed to form the cover opening 4a [(c) of FIG. 4].
【００１３】図３、図４に示した製造方法では、ボンデ
ィングパッド部分の厚さを選択的に減じるためのフォト
リソグラフィ工程（マスク形成工程）とエッチング工程
とを必要とするが、リダンダンシ用のヒューズを最上層
配線層で形成する半導体装置では、ヒューズの溶断を容
易にするために最上層配線の一部（ヒューズ）の膜厚を
減じる工程が必要となるため、この工程においてボンデ
ィングパッドの膜厚を減じるようにすれば、特に新たな
工程を追加することなく、本発明の半導体装置を実現す
ることができる。Although the manufacturing method shown in FIGS. 3 and 4 requires a photolithography process (mask forming process) and an etching process for selectively reducing the thickness of the bonding pad portion, the redundancy fuse is used. In the semiconductor device in which the uppermost wiring layer is formed, a step of reducing the film thickness of a part of the uppermost wiring (fuse) is required to facilitate the blowout of the fuse. By reducing the above, the semiconductor device of the present invention can be realized without adding a new process.
【００１４】図５は、本発明の第２の実施例（図２の実
施例）の製造方法を説明するための工程断面図である。
この例でも、層間絶縁膜１上に膜厚２．４μｍのアルミ
ニウム膜を堆積し、これをパターニングして最上層配線
２とボンディングパッド３とを形成する。続いて、全面
をＳｉ3 Ｎ4 からなるカバー絶縁膜４で被覆し、ボンデ
ィングパッド上に開口を有するフォトレジスト５ｅを設
け、これをマスクにＲＩＥ法によりカバー絶縁膜４をエ
ッチングしてカバー開口部４ａを形成する［図５の
（ａ）］。FIG. 5 is a process sectional view for explaining a manufacturing method of the second embodiment (embodiment of FIG. 2) of the present invention.
Also in this example, an aluminum film having a thickness of 2.4 μm is deposited on the interlayer insulating film 1 and patterned to form the uppermost layer wiring 2 and the bonding pad 3. Subsequently, the entire surface is covered with a cover insulating film 4 made of Si 3 N 4 , and a photoresist 5e having an opening is provided on the bonding pad. Using this as a mask, the cover insulating film 4 is etched by the RIE method to form a cover opening. 4a is formed [(a) of FIG. 5].
【００１５】この状態でさらにＲＩＥ法のエッチングに
よりボンディングパッド部の膜厚を１．３μｍに減じ
［図５の（ｂ）］、続いて、フォトレジスト５ｅを除去
する［図５の（ｃ）］。最上層配線層に膜厚削減を必要
とするリダンダンシ用ヒューズを有しない一般の半導体
装置においては、先の図３、図４に示した製造方法では
新たなフォトリソグラフィ工程とエッチング工程とが必
要となるが、図５に示す製造方法によれば、新たなリソ
グラフィ工程を追加することなく、単にカバー絶縁膜の
エッチングに続けてアルミニウム膜のエッチングを行う
だけで本発明の半導体装置の構造を実現することができ
る。In this state, the film thickness of the bonding pad portion is further reduced to 1.3 μm by etching by RIE method [FIG. 5 (b)], and then the photoresist 5e is removed [FIG. 5 (c)]. . In a general semiconductor device that does not have a redundancy fuse that requires a film thickness reduction in the uppermost wiring layer, a new photolithography process and etching process are required in the manufacturing method shown in FIGS. However, according to the manufacturing method shown in FIG. 5, the structure of the semiconductor device of the present invention is realized by simply etching the cover insulating film and subsequently etching the aluminum film without adding a new lithography step. be able to.
【００１６】図６の（ａ）〜（ｃ）は、本発明の第３の
実施例の製造工程を説明するための工程断面図である。
この例でも、層間絶縁膜１上に膜厚２．４μｍのアルミ
ニウム膜を堆積し、これをパターニングして最上層配線
２とボンディングパッド３とを形成する。続いて、全面
をＳｉ3 Ｎ4 からなるカバー絶縁膜４で被覆し、その上
にボンディングパッド上に開口を有するフォトレジスト
５ｆを形成し、これをマスクにＲＩＥ法によりカバー絶
縁膜４をエッチングしてカバー開口部４ａを形成する
［図６の（ａ）］。6 (a) to 6 (c) are process sectional views for explaining the manufacturing process of the third embodiment of the present invention.
Also in this example, an aluminum film having a thickness of 2.4 μm is deposited on the interlayer insulating film 1 and patterned to form the uppermost layer wiring 2 and the bonding pad 3. Subsequently, the entire surface is covered with a cover insulating film 4 made of Si 3 N 4 , and a photoresist 5f having an opening on a bonding pad is formed thereon, and the cover insulating film 4 is etched by the RIE method using this as a mask. To form the cover opening 4a [(a) of FIG. 6].
【００１７】次に、フォトレジスト５ｆを除去し［図６
の（ｂ）］、続いて、カバー絶縁膜４をマスクとして４
０℃乃至６０℃に熱した燐酸によりボンディングパッド
部を約１．１μｍエッチングする［図６の（ｃ）］。こ
の製造方法でも新たなフォトリソグラフィ工程を追加す
ることなく本発明による半導体装置を実現することがで
きる。Next, the photoresist 5f is removed [see FIG.
(B)], and then 4 using the cover insulating film 4 as a mask
The bonding pad portion is etched by about 1.1 μm with phosphoric acid heated to 0 ° C. to 60 ° C. [FIG. 6 (c)]. Even with this manufacturing method, the semiconductor device according to the present invention can be realized without adding a new photolithography process.
【００１８】図７の（ａ）乃至（ｅ）は、本発明による
半導体装置のボンディングパッドの斜視図であり、図７
の（ｆ）は、従来例のボンディングパッドの斜視図であ
る。図７の（ａ）は、本発明の第１の実施例（図１の実
施例）の、また図７の（ｂ）は、本発明の第２の実施例
（図２の実施例）のボンディングパッドを示している。
図７の（ｃ）、（ｄ）は、図７の（ａ）の例を改変して
ボンディングパッドの一部のみを薄くした例を示してお
り、図７の（ｅ）は、ボンディングパッドおよびそれに
続く配線部の一部を薄くした例を示している。FIGS. 7A to 7E are perspective views of the bonding pad of the semiconductor device according to the present invention.
(F) is a perspective view of a conventional bonding pad. FIG. 7A shows the first embodiment of the present invention (the embodiment of FIG. 1), and FIG. 7B shows the second embodiment of the present invention (the embodiment of FIG. 2). The bonding pad is shown.
7C and 7D show an example in which only a part of the bonding pad is thinned by modifying the example of FIG. 7A, and FIG. 7E shows the bonding pad and the bonding pad. An example is shown in which a part of the subsequent wiring portion is thinned.
【００１９】上記各実施例では、配線の膜厚を２．４μ
ｍ、ボンディングパッドの膜厚を１．３μｍとしたが、
本発明はこれに限定されるものではなく、特許請求の範
囲に記載された範囲内においてこれ以外の値を採用する
ことができる。またカバー絶縁膜の形成方法やその材質
についても他のものに変更しうる。さらに各エッチング
工程におけるエッチャントやエッチング方法についても
他の通常用いられている手段で代替しうる。なお、本発
明における最上層配線とは、多層配線の最上層に限定さ
れるものではなく、一層配線の一層目の配線をも含むも
のである。In each of the above embodiments, the wiring film thickness is 2.4 μm.
m, and the thickness of the bonding pad was 1.3 μm,
The present invention is not limited to this, and other values can be adopted within the scope described in the claims. Further, the method of forming the cover insulating film and the material thereof can be changed to other ones. Furthermore, the etchant and etching method in each etching step can be replaced by other commonly used means. In addition, the uppermost layer wiring in the present invention is not limited to the uppermost layer of the multilayer wiring, and includes the wiring of the first layer of the single layer wiring.
【００２０】[0020]
【発明の効果】以上説明したように、本発明は、２μｍ
を超える厚い最上層配線を用いる半導体装置において、
最上層配線と同一層の金属膜で形成されるボンディング
パッドの膜厚を１．８μｍ以下としたものであるので、
本発明によれば、最上層配線に回路動作に必要な十分の
電流容量を確保しつつ、ワイヤボンディング時における
アルミ屑の発生を抑止することができる。従って、本発
明によれば、高速動作が可能な半導体装置を高歩留りで
製造することが可能になる。As described above, the present invention is 2 μm.
In a semiconductor device using a thick uppermost layer wiring exceeding
Since the thickness of the bonding pad formed of the metal film of the same layer as the uppermost layer wiring is 1.8 μm or less,
According to the present invention, it is possible to suppress the generation of aluminum scraps during wire bonding while securing a sufficient current capacity necessary for circuit operation in the uppermost layer wiring. Therefore, according to the present invention, a semiconductor device capable of high-speed operation can be manufactured with high yield.
【図１】本発明の第１の実施例を示す断面図と平面図。FIG. 1 is a sectional view and a plan view showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す断面図と平面図。FIG. 2 is a sectional view and a plan view showing a second embodiment of the present invention.
【図３】本発明の第１の実施例の第１の製造方法を説明
するための工程断面図。FIG. 3 is a process cross-sectional view for explaining the first manufacturing method of the first embodiment of the present invention.
【図４】本発明の第１の実施例の第２の製造方法を説明
するための工程断面図。FIG. 4 is a process cross-sectional view for explaining the second manufacturing method of the first embodiment of the present invention.
【図５】本発明の第２の実施例の製造方法を説明するた
めの工程断面図。FIG. 5 is a process cross-sectional view for explaining the manufacturing method of the second embodiment of the present invention.
【図６】本発明の第３の実施例の製造方法を説明するた
めの工程断面図。FIG. 6 is a process cross-sectional view for explaining the manufacturing method of the third embodiment of the present invention.
【図７】本発明および従来例におけるボンディングパッ
ドの斜視図。FIG. 7 is a perspective view of a bonding pad according to the present invention and a conventional example.
【図８】従来例の製造方法を説明するための工程断面
図。FIG. 8 is a process sectional view for explaining a manufacturing method of a conventional example.
【図９】従来例の問題点を説明するための断面図と平面
図。9A and 9B are a sectional view and a plan view for explaining the problems of the conventional example.
【図１０】ボンディングパッドの膜厚と不良率との関係
を示すグラフ。FIG. 10 is a graph showing the relationship between the film thickness of the bonding pad and the defect rate.
１ 層間絶縁膜 ２ 最上層配線 ２ａ アルミニウム膜 ３ ボンディングパッド ４ カバー絶縁膜 ４ａ カバー開口部 ５ａ〜５ｇ フォトレジスト ６ ワイヤ ７ アルミ屑 1 Interlayer Insulation Film 2 Top Layer Wiring 2a Aluminum Film 3 Bonding Pad 4 Cover Insulation Film 4a Cover Opening 5a-5g Photoresist 6 Wire 7 Aluminum Scrap
Claims (4)
一層の金属膜によって形成されている半導体装置におい
て、前記最上層配線の主要な部分の膜厚が２．０μｍ以
上であり、前記ボンディングパッドの全部または主要部
の膜厚が１．８μｍ以下であることを特徴とする半導体
装置。1. In a semiconductor device in which the uppermost layer wiring and the bonding pad are formed of the same layer metal film, the film thickness of the main portion of the uppermost layer wiring is 2.0 μm or more, and the bonding pad A semiconductor device characterized in that the film thickness of all or main parts is 1.8 μm or less.
パッドが、故意に添加された不純物を含まないアルミニ
ウムによって形成されていることを特徴とする請求項１
記載の半導体装置。2. The uppermost wiring and the bonding pad are formed of aluminum containing no intentionally added impurities.
The semiconductor device described.
金属膜によって形成され、前記ボンディングパッドの主
要部の膜厚と前記ヒューズの主要部の膜厚とがほぼ等し
いことを特徴とする請求項１または２記載の半導体装
置。3. The uppermost wiring and the fuse are formed of a metal film in the same layer, and the film thickness of the main part of the bonding pad and the film thickness of the main part of the fuse are substantially equal to each other. Item 2. The semiconductor device according to item 1 or 2.
ド上に開口部を有するカバー絶縁膜で覆われ、前記ボン
ディングパッドの薄膜部が前記開口部に整合されて形成
されていることを特徴とする請求項１または２記載の半
導体装置。4. The uppermost layer wiring is covered with a cover insulating film having an opening on the bonding pad, and a thin film portion of the bonding pad is formed in alignment with the opening. Item 2. The semiconductor device according to item 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5021933A JPH088277B2 (en) | 1993-01-14 | 1993-01-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5021933A JPH088277B2 (en) | 1993-01-14 | 1993-01-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06216190A true JPH06216190A (en) | 1994-08-05 |
| JPH088277B2 JPH088277B2 (en) | 1996-01-29 |
Family
ID=12068855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5021933A Expired - Lifetime JPH088277B2 (en) | 1993-01-14 | 1993-01-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088277B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02177451A (en) * | 1988-12-28 | 1990-07-10 | Nec Corp | Semiconductor integrated circuit device |
-
1993
- 1993-01-14 JP JP5021933A patent/JPH088277B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02177451A (en) * | 1988-12-28 | 1990-07-10 | Nec Corp | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH088277B2 (en) | 1996-01-29 |
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