JPH06215566A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To sufficiently secure signal potential by setting the nonselection potential of a word line lower than the 0 write potential of a bit line. CONSTITUTION:A memory cell array is constituted so that the bit lines BLk, the inverse of BLk (k=0, 1,...) and the word lines WLj (j=0, 1,...) are intersected each other and arranged, and memory cells consisting of n channel MOS transistors and capacitors are arranged on these intersection parts. A decoder 3 selecting the word line and a circuit 2 driving the selected word line are provided on the end part of the word line WLj, and on the other hand, bit line amplifiers 1 amplifying the signal potential read out from the cells MC to the bit lines respectively are provided on the end parts of respective bit lines BLk, the inverse of BLk. By a 0 write potential generation circuit 4, the 0 write potential is imparted to the bit line through the amplifier 1. Since the nonselection potential of the word line is set lower than the 0 write potential, the lower limit value of a threshold value voltage is lowered by the potential difference between both potentials, and the signal potential becomes large by the value that the lower limit value becomes low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated dynamic semiconductor memory device (DRAM).

[0002]

2. Description of the Related Art There has been remarkable progress in the integration of DRAM, which is a type of RAM in LSI memory. DRAM
Unit memory cell is, for example, one n connected in series.
It is composed of a channel MOS transistor and one capacitor, and the high integration of DRAM is realized by miniaturizing these elements according to the scaling rule.

As a problem associated with high integration, a decrease in reliability due to a gate oxide film of a MOS transistor is mentioned. That is, the thinning of the gate oxide film increases the electric field applied to the gate oxide film, which causes a breakdown over time (TDD).
B: The problem of Time Dependent Dioxiside Breakdown) has become apparent.

Therefore, the maximum electric field applied to the gate oxide film must be reduced to such an extent that TDDB does not become a problem. For this purpose, it is necessary to lower the selection potential of the word line (potential when turning on the MOS transistor of the memory cell) according to the degree of thinning of the gate oxide film. FIG. 15 shows the level relation of the potentials applied to the bit lines and word lines in the conventional DRAM.

Bit line "0" write potential (potential when "0" data is written to the memory cell capacitor)
V _bL and non-selected potential of word line (MOS of memory cell
The potential when the transistor is turned off) V _wL is also equal to the ground source potential V _ss, and the upper limit of the selection potential V _wH is the source and gate of the MOS transistor of the memory cell when "0" data is written in the capacitor. _Is equal to the upper limit of the voltage applied between and (maximum allowable voltage V _GSmax ).

In the conventional method, the thickness of the gate oxide film is changed to _Tox.
And the flat band voltage is V _FB , V _wHmax = V _GSmax = E _max · T _ox between the upper limit V _{wHmax of the} selection potential and the maximum electric field (maximum allowable electric field) E _max applied to the gate oxide film. There is a relationship of + V _FB (1).

By the way, the threshold voltage of the MOS transistor needs to be large enough to obtain sufficient current cutoff characteristics so that data is not lost when the MOS transistor is not selected. That is, the threshold voltage of the MOS transistor has a lower limit. This lower limit is determined by the allowable leak current when not selected and the subthreshold swing (S factor).

Here, the threshold voltage of the MOS transistor is defined as the potential difference between the gate potential and the source potential when the drain current = 10 ⁻⁶ A, and the allowable leak current = 10.
Using a typical value of ⁻¹⁵ A and S factor = 80 m / decade (room temperature 300 K), the lower limit V _{THmin of the} threshold voltage is as follows. V _THmin =-(log ₁₀ 10 ^-15 -Log ₁₀ 10 ^-6 ) ・
It becomes 80 to 720 mV.

Further, the signal potential V _{SIG conv} that can be held in the memory cell (capacitor) is the above V when the change in the threshold voltage due to the back bias effect is ΔV _THconv.
It can be expressed as follows using _wHmax and V _THmin . V _SIGconv = V _wHmax- (V _THmin + ΔV _THconv ) (2)

It is desirable to reduce the S factor in _order to increase the signal potential V _SIGconv , but as miniaturization progresses, S
In order to obtain a MOS transistor having a small factor, it is necessary to form a MOS transistor having a complicated structure, which results in a problem that the number of steps is increased and the manufacturing cost is increased.

Further, although in order to increase the signal potential V _SIGconv from equation (2) it can be seen that it is sufficient to increase the V _WHmax, the V _WHmax is more than the size determined by the of the expression (1) as described above I can't. Since _Tox in the formula (1) generally becomes smaller as miniaturization progresses, V _wHmax also becomes smaller with miniaturization. Therefore, as the _{degree of} integration increases, the signal potential V _SIGconv decreases, and it becomes difficult to ensure stable operation of the sense amplifier.

[0012]

As described above, the conventional D
In the RAM, the upper limit of the selection potential and the lower limit of the threshold voltage are limited from the viewpoints of preventing TDDB and ensuring good current cutoff characteristics, respectively. For this reason, there is a problem that the signal potential decreases with the miniaturization (high integration) of the element, and it is difficult to ensure stable operation of the sense amplifier.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a dynamic semiconductor memory device which can secure a sufficient signal potential even when the integration is advanced.

[0014]

[Means for Solving the Problems]
Therefore, the dynamic semiconductor memory device of the present invention is
The gate is preceded by the bit and word lines arranged in a lix
Connected to the word line and the drain is connected to the bit line
MOS transistor and this MOS transistor
And a capacitor connected to the source of
Of the dynamics provided at the intersection of the word line and the word line.
Dynamic semiconductor including a memory cell
In the memory device, the non-selection potential of the word line is
Is set lower than the "0" write potential of the input line, and
Select potential of word line and write "0" to bit line
The potential difference from the potential is the source of the MOS transistor
It is set to the upper limit of the voltage that can be applied to the gate
It is characterized by

It is preferable that the impurity concentration of the drain region of the gate overlap portion of the MOS transistor is not more than a predetermined value. Here, the predetermined value is an impurity concentration that can prevent the maximum electric field applied to the gate insulating film when the MOS transistor is in the off state from exceeding that in the on state.

The upper limit of the voltage applied between the source and the gate of the MOS transistor when writing "0" data to the capacitor is, for example, M.
It is the maximum voltage at which the gate insulating film of the OS transistor is not destroyed.

[0017]

In the dynamic semiconductor memory device of the present invention,
The non-selection potential of the word line is set lower than the "0" write potential of the bit line. Therefore, the lower limit value of the threshold voltage can be made lower than the conventional value by the potential difference between the non-selection potential and the "0" write potential. The lower the lower limit of the threshold voltage, the higher the signal potential.

Therefore, if the lower limit value of the threshold voltage is selected as the threshold voltage, the signal potential can be increased. Moreover, since the potential difference between the selection potential and the "0" write potential is set to the upper limit of the voltage that can be applied between the source and the gate of the MOS transistor, the signal potential is M
This is the maximum level that does not reduce the reliability of the OS transistor.

If the threshold voltage is made the same as the conventional one without lowering the threshold voltage as described above, "0" is obtained.
Since the current cutoff characteristic is improved by the amount that the write potential is higher than that of the conventional one, the S factor can be increased. The larger the S factor, the easier the production of the MOS transistor.

Therefore, if the threshold voltage is set to be the same as that of the conventional DRAM, the S factor can be increased. Therefore, even if the degree of integration advances, a fine MOS transistor can be easily formed correspondingly. Therefore, it is possible to prevent an increase in manufacturing cost. Moreover, since the potential difference between the selection potential and the "0" write potential is selected as the upper limit, there is no problem that the signal potential decreases.

[0021]

Embodiments will be described below with reference to the drawings. FIG. 1 is a diagram showing a main part configuration of a DRAM according to an embodiment of the present invention.

A plurality of bit lines BLk, / BLk (k =
0,1, ...) and a plurality of word lines WLj (j = 0,1, ...
..) are arranged so as to intersect with each other, and memory cells MC each composed of an n-channel MOS transistor and a capacitor are arranged at the intersections thereof to form a memory cell array. The gate and drain of the MOS transistor,
Sources are word line WLj and bit line bit line B, respectively.
Lk is connected to the capacitor.

A decoder 3 for selecting a word line and a word line driving circuit 2 for driving the word line selected by the decoder 3 are provided at the end of each word line WLj, while each bit line BLk, / A bit line sense amplifier 1 for amplifying the signal potential read from the memory cell MC to the bit line is provided at each end of BLk.
The “0” write potential generation circuit 4 gives the “0” write potential to the bit line via the bit line sense amplifier 1.
FIG. 2 is a diagram showing the relationship between the potential of the word line (non-selection potential V _wL , selection potential V _wH ) and the potential of the bit line (“0” write potential V _bL ) of the DRAM according to this embodiment.

The potential of the word line and the potential of the bit line of this embodiment are different from those of the prior art of FIG. 16 in that the non-selection potential V _wL is lower than the “0” write potential V _bL and the selection potential is the same. The V _wH is higher than that of the conventional one. For this reason, the "0" write potential generation circuit 4 which is not available in the prior art is provided. The potential relationship will be described below.

The electric field applied to the gate oxide film of the n-channel MOS transistor at the time of selection becomes maximum when the potential of the word line is V _wH and the potential of the bit line is V _bL , that is, "0" in the memory cell. It's time to write the data.
In order to prevent the reliability of the gate oxide film from decreasing due to TDDB or the like, there is an upper limit in the potential difference between the selection potential V _wH and the “0” write potential V _bL . This upper limit is determined by the thickness of the gate oxide film and the maximum allowable electric field (usually 4 to 5 MV / cm).

Non-selection potential V _wL and "0" write potential V _bL
In the conventional DRAM, where and are equal to the ground potential V _ss ,
In order to _{maximize the} potential difference (signal potential) between the “0” write potential V _bL and the “1” write potential V _bH , the selection potential V _wH and the “0” write potential V _bL are set as shown in FIG. The maximum potential difference is within the allowable range (V _GSmax ).
Has become.

If the "0" write potential V _bL is made higher than the ground potential V _ss without changing the potential amplitude of the word line (potential _difference between the selected potential V _wH and the non-selected potential V _wL ) and the threshold potential V _wH. , in other words, "0" when the write voltage V _bL higher than the non-selection potential V _wL, "0" by boosting many write potential V _bL, the potential difference between the selection potential V _wH "0" write potential V _bL Since it becomes smaller, there is a disadvantage that the signal potential decreases.

Therefore, as shown in FIG. 2, the selection potential V
_{By increasing} the selection potential V _wH so that the potential difference between _wH and the “0” write potential V _bL becomes equal to the maximum allowable voltage V _GSmax , the same signal potential and reliability of the gate oxide film as in the conventional case can be secured.

That is, in the present embodiment, the upper limit V _{wHmax of the} selection potential is _increased by ΔV _{bL in comparison} with the conventional one, corresponding to the increase of the “0” write potential V _bL by ΔV _{bL in comparison} with the conventional one. Therefore, the lower limit of the threshold voltage is set to V _TH −Δ
It can be reduced to V _bL .

Therefore, the threshold voltage is set to V _TH −ΔV _bL
If set to, the signal potential can be maximized without lowering the reliability of the gate oxide film. Therefore, even if the degree of integration progresses, the signal potential can be suppressed from decreasing, and Stable operation can be secured.

If the threshold voltage is made the same (V _TH ) as that of the conventional one without lowering the threshold voltage, the source potential V _S is increased by ΔV _bL as compared with the conventional one. Since the current cutoff characteristic is improved, the S factor can be increased. The larger the S factor, the more the MOS
The transistor can be easily created.

Therefore, the S factor can be increased without lowering the reliability of the gate oxide film.
Even if the degree of integration progresses, a fine MOS transistor can be easily formed correspondingly, so that an increase in manufacturing cost can be prevented.

As described above, according to this embodiment, the threshold voltage of the MOS transistor and the selection range of the S factor can be widened without lowering the reliability of the gate oxide film. The DRAM can be easily realized. The setting of the threshold voltage is not limited to the above level, but may be in the range of V _wH −ΔV _bL or more.

FIG. 3 shows M of the peripheral circuit in the case of this embodiment.
An example of how to take the potential amplitude of the OS transistor is shown. This is an example of how to make the reliability of the MOS transistor of the memory cell equal to the reliability of the MOS transistor of the peripheral circuit. That is, the potential amplitudes V _{peri1 to} V _peri4 of the MOS transistors in the peripheral circuit are all equal to the allowable maximum voltage V _GSmax .

Like the potential amplitudes V _peri3 and V _peri4 , the "H" level potential of the potential amplitude of the MOS transistor of the peripheral circuit is the selection potential V of the MOS transistor of the memory cell.
If it is lower than _wH, the "H" level potential of the potential amplitude of the MOS transistor of the peripheral circuit is made equal to the "1" write potential V _bH which is lower than the selection potential V _wH by the threshold voltage of the MOS transistor of the memory cell. Alternatively, if the bit line precharge potential is equalized, the internal potential generation circuit of the DRAM can be simplified.

Similarly, the internal potential generating circuit is constructed by taking the potential amplitude of the MOS transistor of the peripheral circuit between the selection potential V _wH and the "0" write potential V _bL like the potential amplitude V _peri2. Can be simplified.

Further, as the potential amplitude V _Peri4, if "L" level potential of the potential amplitude of the MOS transistor of the peripheral circuit is equal to the ground potential V _ss is the ground potential V _ss is an external power supply potential in the DRAM Considering that it is more stable than any generated internal potential, the most stable peripheral circuit operation can be obtained.

FIG. 4 shows M of the peripheral circuit in the case of this embodiment.
An example of another method of taking the potential amplitude of the OS transistor is shown. This is an example of a method in which the reliability of the MOS transistor of the peripheral circuit is higher than the reliability of the MOS transistor of the memory cell.

That is, the potential amplitudes V _{peri5 to} V _peri9 of the MOS transistors of the peripheral circuits are all smaller than the maximum allowable voltage V _GSmax . These potential amplitudes V
_{The peri5 to Vperi9} have the same advantages as the potential amplitudes _{Vperi1 to Vperi4} .

The maximum electric field is applied to the MOS transistor of the memory cell when it is active, and moreover, when "0" data is written in the memory cell. On the other hand, the maximum electric field is applied to the MOS transistor of the peripheral circuit during the standby period or the active period, and
The period in which the maximum electric field is applied is much longer than that of the OS transistor.

Therefore, as shown in FIG. 4, the potential amplitude of the MOS transistor in the peripheral circuit is set to the allowable maximum voltage V.
_Making it smaller than _GSmax is advantageous in improving the reliability of the MOS transistor of the entire DRAM.

FIG. 5 shows M of the peripheral circuit in the case of this embodiment.
An example of another way of taking the potential amplitude of the OS transistor is shown. This is an example in which the “H” level potential of the potential amplitude V _peri10 is unified to be equal to the “0” write potential V _bL . Also in this method, the structure of the internal potential generating circuit of the DRAM can be simplified as in the previous embodiment. Figure 6
FIG. 9 is a diagram showing a relationship between a potential of a bit line (“0” write potential V _bL ) and a potential of a word line (selection potential V _wH ) of a DRAM according to another embodiment of the present invention.

The present embodiment is different from the previous embodiments in that the non-selection potential V _wL is a negative potential lower than the ground potential V _ss , and the ground potential V _ss is "0".
It is equal to the write potential V _bL .

Even with such a potential relationship, the non-selection potential V _wL
Becomes lower than the ground potential V _ss , the non-selection potential V _wL
Becomes lower than the “0” write potential V _bL, and the same effect as that of the previous embodiment can be obtained.

FIG. 7 shows M of the peripheral circuit in the case of this embodiment.
An example of how to take the potential amplitude of the OS transistor is shown. This is an example of a method of making the reliability of the MOS transistor of the memory cell equal to the reliability of the MOS transistor of the peripheral circuit as in FIG.

That is, the potential amplitudes V _peri11 and V _peri12 of the MOS transistors of the peripheral circuit are both equal to the maximum allowable voltage V _GSmax . It is more preferable to set the potential amplitude of the MOS transistor of the peripheral circuit between the selection potential V _wH and the “0” write potential V _bL like the potential amplitude V _peri12 .
Compared with the case of the potential amplitude V _peri11 , the structure of the internal potential generating circuit of the DRAM can be further simplified.

FIG. 8 shows M of the peripheral circuit in the case of this embodiment.
An example of another method of taking the potential amplitude of the OS transistor is shown. This is an example of a method in which the reliability of the MOS transistor of the peripheral circuit is higher than the reliability of the MOS transistor of the memory cell.

That is, as in FIG. 4, the maximum allowable voltage V
Than _GSmax, the potential amplitude _V peri13 ~V peri17 of MOS transistors of the peripheral circuit is smaller, the same advantages as described in the FIG. Next, the threshold voltage of the MOS transistor of the memory cell will be described in more detail.

The present invention, as described above, uses the non-selection potential V _wL.
Is made lower than the “0” write potential V _bL , and the selection potential V is set so as not to reduce the reliability of the gate oxide film.
_wHnew is selected as shown in the following formula (3). V _wHnew = V _GSmax + V _bL (3)

Then, the same S as in the conventional method (V _bL = V _wL ) is used.
If the factor is the lower limit V _THnew of the threshold voltage of the MOS transistor of the present invention, when the lower limit of the threshold voltage of the conventional method and _{V THconv, V THnew = V THconv} -V bL ... (4) As shown, the lower limit of the threshold voltage is lower than in the conventional case, and the signal potential can be increased.

Here, V _THnew is a gate voltage when a source potential is V _{bL and} a drain current of 10 ⁻⁶ A is obtained.
It is defined as the potential difference between the sources. To reduce the threshold voltage, the impurity concentration in the channel region may be lowered. Further, in the case of the present invention, the signal potential (V _bH −
V _bL ) is expressed as V _SIGnew = (V _wHnew −ΔV _THnew −V _THnew ) −V _bL (5), where ΔV _THnew is the change in the threshold voltage due to the back bias effect. Using equations (1) to (4), equation (5) can be rewritten as follows. V _SIGnew = ΔV _SIGconv + V _bL + (ΔV _THconv −ΔV _THnew ) (6)

In the case of the present invention, V _bH corresponding to the back bias voltage increases, but the value of ΔV _TH itself becomes rather small due to the decrease of the impurity concentration in the channel region. From the equation (6), the signal potential V _SIGnew is decreased by the threshold voltage (V _bL ).
It can be seen that it increases by the sum of the sum of the above and the reduction of the back bias effect. Therefore, according to the present invention, even if the MOS transistor of the memory cell is further miniaturized in the future,
Stable sense amplifier operation can be guaranteed

FIG. 8 is a diagram showing the relationship between the "0" write potential V _bL , the selection potential V _wH and the "1" write potential V _bH .
When the “0” write potential V _bL is made higher than the ground potential V _ss , the selection potential V _wH and the “1” write potential V _bH
Shows how changes occur.

[0054] It should be understood that the film thickness T _OX of the gate oxide film of the MOS transistor of the memory cell is calculated for 256DRAM of 7 nm, the MOS transistor is intended n-channel type formed in the p-well, the p-well The potential is fixed to the ground potential V _ss , and the gate electrode material is n ⁺ The maximum electric field applied to polysilicon and the gate oxide film is 4 MV / cm, and the S factor is 80 mV / deca.
I'm assuming de.

[0055] When the 9 "0" is increased write voltage V _bL, as described above, "0" write potential V _bL
And the signal potential V that is the potential difference between the "1" write potential V _bH
You can see that _SIG is increasing

In the 256 DRAM, the external power supply potential V _CC is considered to be 3.3 V. In this case, if the "0" write potential V _bL is set to 0.55 V or less, the selection potential V _wH.
Does not exceed the external power supply potential V _CC , the word line boosting circuit which has been conventionally required is not necessary. Also, "0"
Compared with the case of the conventional method in which the write potential V _bL is 0 V,
The signal potential V _SIG can be increased by 50% or more.

When the "0" write potential V _bL is set to 0.55 V, the external power supply potential V _CC can be used as it is as the selection potential V _wH , so that no special step-up circuit or step-down circuit for word lines is required. Become. Therefore, the internal circuit configuration of the DRAM can be further simplified and the chip size can be reduced.

The signal potential V _SIG decreases when the “0” write potential V _bL becomes 0.7 V or more because the “1” write potential V _bH must be equal to the external power supply potential V _CC. . This is because when a bit line potential is restored to the "1" write potential _VbH , a large current instantaneously flows through the "1" write potential (generation) circuit, so that the "1" write potential _VbH is externally applied. Set higher than the power supply potential V _CC (use the charge pump circuit to write "1" potential V
It is difficult to generate _bH ).

Considering these _points , setting the "0" write potential V _bL to 0.7 or more and setting the "1" write potential V _bH to the external power supply potential V _CC is _equivalent to the "1" write potential. special high performance step-down circuit for generating the stability and "1" write potential V _bH of V _bH is advantageously unnecessary.

In the case of the conventional system, the "H" level (internal power supply voltage) of the potential amplitude of the peripheral circuit is "1" write potential V.
_Although it is often equal to _bH , for example, when each potential behaves as shown in FIG. 9, the peripheral circuit is connected to the ground potential V _SS -2.5.
By operating with a voltage in the range of V, the “H” level of the potential amplitude of the peripheral circuit and the “1” write potential V _bH can be electrically separated. Therefore, the fluctuation of the internal power supply voltage can be suppressed, and the operation of the peripheral circuit can be stabilized.

FIG. 10 shows "0" when the potential relationship is as shown in FIG.
FIG. 6 is a diagram showing a relationship between a write potential V _bL and a lower limit of threshold voltage of a memory cell (hereinafter, also simply referred to as threshold voltage) V _THmin . The threshold voltage V _THmin here is converted into a normal threshold voltage of the source potential of the ground potential V _SS .

When the "0" write potential V _{bL is set} to _0.65 V or more, the threshold voltage V _THmin becomes negative. By the way, the leak current when the MOS transistor of the peripheral circuit is off is 10 ^−10. The threshold voltage V _THmin needs to be 0.32 V or more when the S factor is 80 mV / decade, although it needs to be about A or less. It can be seen from FIG. 10 that the threshold voltage V _THmin of the MOS transistor of the memory cell is 0.32 V or more when the “0” write potential V _bL is 0.3 V or less.
Therefore, the "0" write potential V _bL is, for example, 0.3 V
If set to, the same MOS transistor can be used for the MOS transistor of the memory cell and the MOS transistor of the peripheral circuit. FIG. 11 is a view similar to FIG. 9, and relates to a 1G DRAM in which the thickness T _OX of the gate oxide film is 5 nm.

In this case, the "0" write potential V _{bL is set} to 0.
When it is set to 8 V or more, the "1" write potential V _bH can be set to the selection potential V _wH or more, and the so-called "1" write potential threshold drop can be prevented.

If the external power supply potential V _CC is 3.3 V, the "0" write potential V _bL is raised to about 1 V,
"1" if the write potential V _bH to 3.3V, "1" can be omitted a circuit for generating a write potential V _bH, also, 3V selection potential V _wH and "1" write potential V _bH to Ban By doing so, the write margin of the "1" write potential can be increased. This is because 3.3V can actually be written. Further, the "0" write potential V _{bL is set} to 0.8 V and the selection potential V _wH and "1" are set.
If the write potential _VbH is unified, the internal potential generating circuit can be simplified.

Although FIG. 11 and FIG. 9 are for the cases where the gate oxide film thickness is 5 nm and 7 nm, respectively, if the gate oxide film thickness is set between 5 nm and 7 nm, Select potential V _wH and “1” write potential V _bH
Both can be made equal to the external power supply potential V _CC .
In this case, the structure of the internal circuit of the DRAM can be remarkably simplified, and the chip size can be further reduced.

[0066] Further, if the external power supply potential V _CC is 2.5V, "0" by setting the write potential V _bL example, 0.55 V, it is possible to use an external power supply potential V _CC as the selective voltage V _wH And, the signal potential can be made 70% or more higher than that of the conventional method.

In this case, since the potential _difference between the selection potential V _wH and the “1” write potential V _bH is much smaller than in the conventional case, the restore level on the “H” level side of the bit line is set to the external power supply potential. It is possible to raise it to V _CC . Even if the restore level is raised, the potential that can be written in the memory cell does not change to the "1" write potential _VbH , and the power consumption due to the charging / discharging of the bit line rather increases. However, the internal circuit can be simplified, and the potential of the bit line does not need to be completely raised to the external power supply potential V _{CC at the} time of writing, and the point is that it is sufficient to rise to the "1" write potential V _bH . The time required for restoration can be shortened considerably. Next, the S factor of the MOS transistor of the memory cell will be described in more detail.

As described above, the non-selection potential V _wL is _set to "0".
Since lowering the write potential V _bL has the effect of improving the cut-off characteristic of the MOS transistor, increasing the “0” write potential V _bL even in a MOS transistor having a larger S factor provides sufficient cut. Off characteristics can be obtained.

In the future, as miniaturization progresses, it will become more difficult to design a MOS transistor having a good S factor, and the structure of the MOS transistor will become more and more complicated. Therefore, the use of a MOS transistor having a large S factor for the memory cell leads to simplification of the manufacturing process and cost reduction.

FIG. 12 is a diagram showing how the relationship between the "0" write potential V _bL and the threshold voltage V _THmin changes with changes in the parameters of the S factor and the signal potential V _SIG .

This is calculated for 256 DRAM in which the thickness T _OX of the gate oxide film of the MOS transistor of the memory cell is 7 nm, and it is assumed that the maximum electric field applied to the gate oxide film is 4 MV / cm.

In the figure, the solid line shows the change in the threshold voltage V _THmin when the parameter is the S factor, and
The alternate _{long and short} dash line shows the change in the threshold voltage V _THmin when the parameter is the signal potential V _SIG . There is a physical lower limit to the S factor, which is, for example, 59 mM / decade at room temperature (300K).

[0073] "0" and continue to be higher than the write potential V _bL the ground potential V _SS, "1" when the write potential V _bH once reach to the external power supply potential V _CC (3.3V), signal potential V
_SIG is determined by the value of "0" write potential _VbL regardless of the S factor. That is, the relationship of V _SIG = V _CC −V _bL is established. The chain line in the figure represents the boundary where the situation changes in this way. In the case of the conventional method, the MOS transistor of the memory cell had to be designed with the threshold voltage V _THmin and the S factor on the vertical axis of FIG.

On the other hand, in the case of the present invention, S = 59 mV / deca
MOS of memory cell at any point above the solid line of de
Since the transistor can be designed, the degree of freedom in design is dramatically increased.

In the above description, the method of setting the "0" write potential V _bL higher than the ground potential V _SS has been mainly described.
Similar effects can be obtained by a method in which the non-selection potential V _wL is lower than the ground potential V _SS as shown in FIG.

By the way, as in the present invention, the non-selection potential V
_{In the method in} which _wL is made lower than the “0” write potential V _bL ,
The following can be considered as the potential difference between the non-selection potential V _wL and the “0” write potential V _bL increases. In addition,
Here, the potential difference between the selection potential V _wH and the “0” write potential V _bL is kept at the maximum allowable gate-source voltage (hereinafter, also referred to as the maximum gate-source voltage) V _GSmax , and the “0” write is performed. Consider a case where the potential V _bL is gradually increased from the ground potential V _SS .

The electric field applied to the gate oxide film of the MOS transistor of the memory cell is maximized when the memory cell is not selected, when the bit line connected to the memory cell is restored to the "1" write potential V _bH or when the memory cell has " This is an overlap portion between the gate region and the drain region when the 1 ″ write potential V _bH is written.

As shown in FIG. 13A, in the conventional method, the maximum gate-source voltage V _GSmax at the time of selection is M
Since only the threshold voltage of the OS transistor is higher than the maximum voltage between the gate and the drain when not selected (hereinafter, also referred to as the maximum voltage between the gate and drain) V _GDmax , the maximum electric field E _max (off) when not selected is Maximum electric field E _max (on) when selected
Never exceeds.

On the other hand, in the case of the present invention, as shown in FIG. 13B, when the “0” write potential V _bL is made higher than the ground potential V _SS , the maximum gate-source voltage V _GSmax is constant. The maximum voltage V _GDmax between the gate and drain increases. Therefore, the maximum electric field E _max (of
f) may exceed the maximum electric field E _max (on) at the time of selection, and the maximum electric field E _max (off) and the maximum gate-drain voltage V _GDmax have the following relationship. Here _{V GDmax + V FB = E max} (off) · T OX + φ s ... (8), φ s denotes the surface potential of the drain region, is approximated as follows. φ _s = ε _s・ (ε _ox・ E _max (off) / ε _s ) ² / (2q · N _d ) ... (9) Here, N _d represents the impurity concentration in the drain region under the gate electrode (gate region). Substituting equation (9) into equation (8), V _GDmax + V _FB = E _max (off) · T _OX

+ Ε _s · (ε _ox · E _max (off) / ε _s ) ² / (2q · N _d ) ... (10)

From the equation (10), it can be seen that the maximum electric field E _max (off) can be reduced by decreasing the impurity concentration N _d .
Therefore, even when the maximum voltage V _GDmax between the gate and the drain is larger than the maximum voltage V _GSmax between the gate and the source, the maximum electric field E can be controlled by controlling the impurity concentration N _d.
It is possible to prevent _max (off) from _{exceeding the} maximum electric field E _max (on).

FIG. 14 shows a 256 DRAM in which the thickness T _OX of the gate oxide film of the MOS transistor of the memory cell is 7 nm.
, The maximum electric field E _max (off) is the maximum electric field E _max (o
FIG. 9 is a diagram showing a relationship between an upper limit N _dmax of an impurity concentration and “0” write potential V _bL so as not to exceed n) (= 4 MV / cm). Based on this, by setting the impurity concentration of the drain region of the gate overlap portion to a predetermined value or less, the maximum electric field E _max (off) when not selected exceeds the maximum electric field E _max (on) when selected. A DRAM that can be prevented and has a higher reliability than the conventional one can be obtained reliably.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case of an n-channel MOS transistor has been described, but the present invention can also be applied to a p-channel MOS transistor.

The precharge potential of the bit line and the potential of the plate electrode connected to the cell capacitor can be set to any level, but both of these potentials are "0" write potential V _bL and "1" write potential. It is preferable to take an intermediate potential between the potential _VbH and the potential _{VbH from} the viewpoint of reducing current consumption and improving reliability. Further, although the precharge potential of the dummy cell can be set to an arbitrary level, it is preferable to set it to the intermediate potential for the same reason. In addition, various modifications can be made without departing from the scope of the present invention.

[0085]

As described above in detail, according to the present invention, the selection range of the threshold voltage and the S factor of the MOS transistor can be widened without lowering the reliability of the gate insulating film, so that the high integration can be achieved. Real-time DRAM becomes easy.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a level relationship of potentials applied to a word line and a bit line of a DRAM according to an embodiment of the present invention.
The figure for demonstrating the effect of this invention.

FIG. 3 is a diagram showing how to take a potential amplitude of a MOS transistor of a peripheral circuit in the case of the potential relation of FIG.

FIG. 4 is a diagram showing another method of taking the potential amplitude of the MOS transistor of the peripheral circuit in the case of the potential relation of FIG.

FIG. 5 is a diagram showing another way of obtaining the potential amplitude of the MOS transistor of the peripheral circuit in the case of the potential relation of FIG.

FIG. 6 is a diagram showing a level relationship of potentials applied to word lines and bit lines of a DRAM according to another embodiment of the present invention.

FIG. 7 is a diagram showing how to take a potential amplitude of a MOS transistor of a peripheral circuit in the case of the potential relation of FIG.

FIG. 8 is a diagram showing another method of taking the potential amplitude of the MOS transistor of the peripheral circuit in the case of the potential relation of FIG.

FIG. 9 is a diagram showing a relationship among a “0” write potential, a selection potential, and a “1” write potential.

FIG. 10 is a diagram showing a relationship between a “0” write potential and a lower limit of a threshold voltage of a memory cell.

FIG. 11 is a diagram showing a relationship among a “0” write potential, a selection potential, and a “1” write potential.

FIG. 12 is a diagram showing how the relationship between the “0” write potential and the threshold voltage changes with changes in the S factor and the signal potential.

FIG. 13 is a diagram showing a potential relationship of a DRAM of the present invention in comparison with that of a conventional one.

FIG. 14 is a diagram showing the relationship between the upper limit of the impurity concentration and the “0” write potential.

FIG. 15 is a diagram showing a level relationship of potentials applied to bit lines and word lines in a conventional DRAM.

[Explanation of symbols]

1 ... bit line sense amplifier 2 ... word line driving circuit 3 ... decoder 4 ... "0" write potential generating circuit MC ... memory cell V _wL ... non-selection potential V _wH ... selection potential V _bL ... "0" write potential V _bH ... "1" write potential V _G ... gate potential V _S ... source potential V _TH, the allowable maximum voltage between V _TH '... threshold voltage V _ss ... ground potential V _SIG ... signal potential V _GSmax ... gate source V _GDmax ... Maximum allowable voltage between gate and drain ΔV _GS ... Gate-drain fluctuation potential V _{peri1 to} V _peri17 ... Potential amplitude of peripheral circuits

Claims (1)

[Claims] 1. A MOS transistor having a gate connected to a word line and a drain connected to a bit line, and an MO transistor of the same.
In a dynamic semiconductor memory device including a dynamic memory cell including a capacitor connected to a source of an S transistor, a non-selection potential of the word line is set lower than a "0" write potential of the bit line. And the potential difference between the selection potential of the word line and the “0” write potential of the bit line is
A dynamic semiconductor memory device, wherein an upper limit of a voltage that can be applied between a source and a gate of the MOS transistor is set.