JPH04356791A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate a malfunction and to enable a high speed operation by supplying a word line activation signal to a word line when the word line selection signal is supplied to a gate electrode. CONSTITUTION:When the word line selection signal is supplied to the gate electrode, the word line activation signal is supplied to word lines L1-Ln. When a voltage is applied to a word line selection signal terminalD1, a transistorQ11 turns ON and the activation signal is transmitted to a word line L1. Hence a transistorQ31 starts to turn ON and when it is over a threshold voltage VrH3, a transistorQ21 starts to turn OFF due to fall of potential of a reset line N. Next when a reset signal is inputted to a reset signal terminal R, a transistorQ4 becomes an ON state and a potential of the reset line N in raised. TransistorsQ31, Q32 become an ON state and a potential of the word line L1 is decreased. Transistors Q31, Q32 turn OFF. Thus since a lead electric current due to a short channel effect is suppressed, a malfunction is eliminated.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to semiconductor memory devices, and particularly to dynamic random access memories (hereinafter referred to as D-
(referred to as RAM).

0002

2. Description of the Related Art In order to realize a highly integrated MOS type D-RAM with a large storage capacity and a fast access time, it is necessary to reduce the size of the MOS transistors that are its constituent elements. As a result, the gate length becomes short, and leakage current between the drain and source may increase due to the so-called short channel effect. Therefore, the word line signal drive circuit in the D-RAM may malfunction due to this leakage current. That is, switch to page mode, select a word line, apply an activation signal, and set it to a high level (hereinafter referred to as “
In the process of sequentially selecting bit lines and writing to memory cells, the "H" potential of the selected word line drops due to the leakage current mentioned above. In some cases, a situation occurred in which writing could not be performed completely.When designing a D-RAM, the gate length is shortened to the extent that the short channel effect described above does not occur.
Because it depends largely on the magnitude of the voltage applied between the drain and source of the transistor, the memory cell section where the applied voltage is relatively low and the peripheral circuit section such as the word line signal drive circuit where the applied voltage is relatively high are connected to the transistor with the same specifications. When this design was carried out, the above-mentioned disadvantages often occurred.

0003

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can satisfy the short channel requirement for higher speed while also eliminating the occurrence of malfunctions due to short channel effects.

0004

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a semiconductor memory device with a plurality of memory cells each having a transistor and a capacitor, and a gate electrode of each transistor of the plurality of memory cells. A connected word line, a plurality of bit lines corresponding to the plurality of memory cells, each of which writes to the corresponding memory cell, and a word line activation level sufficiently higher than the power supply voltage. When the activation signal is applied to one electrode and the other electrode is connected to the word line, and the word line selection signal is applied to the gate electrode, the word line activation signal is applied to the word line. The first transistor turns on all the transistors of the plurality of memory cells, the first transistor continues the ON state until writing to all the memory cells by the plurality of bit lines is completed, and the first transistor turns on all the transistors of the plurality of memory cells. a first transistor having a gate length longer than each gate length of the transistor;
a second transistor that sets the word line to a level at which all transistors of the plurality of memory cells are turned off in response to a power supply voltage level reset signal applied after completion of writing to the memory cell; A second transistor having a gate length longer than each gate length of the transistors of the memory cell is provided.

[0005]

[Operation] According to the present invention, when a D-RAM operates in page mode, after a predetermined word line is selected and an activation signal is applied, writing to a memory cell is performed by sequentially selecting bit lines. Until this is completed, it is possible to effectively prevent a potential drop from occurring on the selected word line due to leakage current.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a D-RAM including a word line signal driving circuit to which the present invention is applied.

The word line signal drive circuit has one end connected to the word line activation signal terminal P, and activates the word lines L1, L2...Ln in response to word line selection signals D1, D2...Dn supplied to the gates. It is composed of transistors Q11, Q12,...Q1n that transmit signals, and a reset circuit 10 that resets the activation signals on the word lines L1, L2...Ln. Reference numeral 20 denotes a memory section in which memory cells each consisting of a combination of a transistor T and a capacitor C are arranged in a matrix. Each memory cell has word lines L1, L2...Ln and bit lines B1, B
2,...Bn, and storage is performed by selectively accumulating charge in the capacitor C.

In the conventional circuit, all transistors including the transistor T constituting the memory were designed to have the same gate length, but in the circuit shown in FIG. Q11, Q12,
...Q1n, Q21, Q22...The threshold voltages of Q2n are set higher than those of other transistors. In order to increase the threshold voltage of some transistors without increasing the manufacturing process, the gate length can be made longer than that of other transistors, and this can be done simply by changing some of the photolithography masks. It can be realized.

Next, the operation of the circuit shown in FIG. 1 will be described. For the sake of simplicity, the explanation will be limited to word lines L1 and L2, but the same applies to the other circuits. FIG. 2 is a timing chart for explaining the operation. Word line activation signal terminal P
potential VCC+VTH+α (here, VCC is the power supply voltage,
VTH is the threshold voltage of the transistors Q11 and Q12, and α is the margin voltage. ), and then when the power supply voltage VCC is applied to the word line selection signal terminal D1, the transistor Q11 is turned on and transmits the activation signal to the word line L1. At this time, the potential of word line L1 is V
It becomes CC and becomes “H”. As the potential of the word line L1 rises, the transistor Q31 starts to turn on, and when the potential of the word line L1 exceeds the threshold voltage VTH3 of the transistor Q31, the potential of the reset line N becomes VC.
C-VTH4 (Here, VTH4 is transistor Q4
threshold voltage) to 0V. As the potential of the reset line N drops, the transistor Q21 begins to turn off, and becomes completely off when its potential falls below VTH2 (here, VTH2 is the threshold voltage of the transistors Q21 and Q22). Since the unselected word line selection signal terminal D2 is maintained at 0V, the transistor Q12 is not turned on, and the potential of the word line L2 is 0V.

Next, when a reset signal having a potential of VCC is input to the reset signal terminal R, the transistor Q4 is turned on, and the potential of the reset line N becomes VCC-VTH.
The pressure is increased to 4. And the potential of the reset line N is VT
When the voltage exceeds H2, transistors Q21 and Q2
2 is turned on, and the potential of the word line L1 is reduced to 0V. At the same time, transistors Q31 and Q32
is turned off, and the potential of the reset line N settles to VCC-VTH4. In such an operation, the word lines L1, L
2 is “H” only when selected by the word line selection signal.
” and remains “H” until reset by the reset signal.
” must be maintained.

In the conventional circuit, transistors Q11 and Q1
However, the short channel effect of Q21, Q22 causes a leakage current, which causes the "H" potential of the word lines L1 and L2 to drop, and the potential of the word line activation signal to drop. As shown in FIG. 1, transistors Q11, Q12...Q1n, Q21, Q22,...
This drawback can be overcome by increasing the threshold voltage of Q2n to prevent leakage current from occurring due to the short channel effect. (In FIG. 2, a waveform diagram with a potential drop is shown by a dotted line.) Therefore, normal memory write operation will not be inhibited.

0012

As described above in detail based on the embodiments, according to the present invention, it is possible to realize a short channel for increasing the speed of a semiconductor memory device operating in page mode, and to reduce the short channel effect, i.e. It is possible to provide a semiconductor device that eliminates malfunctions due to punch-through, and further, by using a high-level word line activation signal, it is possible to provide a semiconductor device that can operate at higher speed.

[Brief explanation of drawings]

FIG. 1 is a D-RAM circuit diagram according to an embodiment of the present invention.

FIG. 2 is a time chart explaining the circuit operation of FIG. 1;

[Explanation of symbols]

10 Reset circuit 20 Memory section P Word line activation signal terminal L1 ~ Ln Word line B1 ~ Bn Bit line R Word line reset signal terminal

Claims (1)

[Claims] 1. A plurality of memory cells each having a transistor and a capacitor, a word line connected to a gate electrode of each transistor of the plurality of memory cells, and a plurality of bit lines corresponding to the plurality of memory cells. A plurality of bit lines each write to a corresponding memory cell, and a word line activation signal at a level sufficiently higher than the power supply voltage is applied to one electrode, and the other electrode is connected to the word line. , the first transistor turns on all transistors of the plurality of memory cells by applying the word line activation signal to the word line when the word line selection signal is applied to the gate electrode; ,
a first transistor having a gate length longer than each gate length of the transistors of the plurality of memory cells; a second transistor that sets the word line to a level at which all transistors of the plurality of memory cells are turned off in response to a power supply voltage level reset signal applied after completion of writing to the plurality of memory cells; a second transistor having a gate length longer than each gate length of the transistors of the cell.