JPH06214595A - Voice recognition method - Google Patents

Abstract

PURPOSE:To eliminate waiting time of each operation processor and to reduce a frame length by repeatedly executing a third operation process for every frame with a new first operation process. CONSTITUTION:After a first operation process of a first operation processor 10, a second operation processor 20 repeatedly executes a second operation process for every frame with at least more than one frame time delay, the processor 10 repeatedly executes a third operation process, which is at least more than one frame time delayed than the second operation process, with the first operation process. Thus, a series of processes, i.e., the first to the third operation processes, which are related to one data and executed by two operation processors, are executed in plural frame time. However, each operation processor executes the process assigned to itself for every frame and performs an operation process against the data which are time sequentially inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voice recognition method for executing voice recognition processing in a fixed cycle such as a frame, and more particularly to a voice recognition method in which a plurality of digital processing processors share the processing.

[0002]

2. Description of the Related Art Conventionally, in a general speech recognition method, speech is converted into an electric signal, the characteristics of the signal waveform are extracted, and the characteristics are compared with a predetermined standard pattern. An identification label (identification number for phoneme or phoneme) added to the most similar standard pattern is output as a speech recognition result.

In such a voice recognition method, a feature is extracted from a voice signal at regular intervals (called a frame period), and voice recognition is performed based on the result. Since a complicated calculation process is involved in the extraction of the characteristic of the signal waveform and the calculation of the similarity of the standard pattern (distance calculation), the calculation process takes time. Therefore, recently, a voice recognition apparatus has been proposed in which a plurality of digital processors share the arithmetic processing and shorten the frame period to improve the voice recognition accuracy.

FIG. 2 shows a partial circuit configuration of a speech recognition apparatus of this type conventionally. In FIG. 2, a first digital (arithmetic) processor (DSP) 10 and a second DSP 20
A buffer 15 is provided between them.

In such a configuration, the first DSP 1
When 0 executes the first calculation process for voice recognition using the characteristic parameter extracted from the voice signal, 0 transfers the calculation result P (t) to the buffer 15. Buffer 15
Temporarily stores the operation result P (t) for adjusting the transfer timing, and delivers the operation result P ′ (t) after the temporary storage to the second DSP 20.

The second DSP 20 outputs the calculation result P '.
The second arithmetic processing relating to voice recognition is performed using (t). The calculation result Q (t) is temporarily stored in the buffer 15 and then delivered to the first DSP 10 as Q ′ (t).
The first DSP 10 uses the second calculation result Q ′ (t) to perform a third calculation process and output a voice recognition result.

Such a series of processing is executed in one frame. For reference, the execution timing of the above process is shown in FIG. As is clear from FIG. 3, the processing executed in one frame is as follows: operation of the first DSP 10 → transfer to the buffer 15 → second DS
P20 operation → transfer to buffer 15 → first DSP1
Since there is a calculation operation of 0, one frame length is the total of the above processing times.

[0008]

Further, while one of the first and second DSPs 10 and 20 described above is executing the arithmetic processing, the other DSP becomes a waiting time (see FIG. 3). In addition, since the processing speed of the DSP is limited, even if the maximum processing speed of the DSP is used, there is a limit to the length of one frame and it is difficult to reduce the length of one frame.

Therefore, in view of the above points, an object of the present invention is to reduce the waiting time of the DSP and shorten the length of one frame when the voice recognition processing is shared by a plurality of DSPs. It is to provide a possible voice recognition method.

[0010]

In order to achieve such an object, the present invention provides a first arithmetic processor which provides a first operation processor.
The second arithmetic processor executes the second arithmetic processing using the first arithmetic result, and the second arithmetic processor executes the second arithmetic processing using the second arithmetic processing result. In the speech recognition method of executing the arithmetic processing of No. 3, and repeatedly executing the processing related to the speech recognition for each frame, the second arithmetic processor is at least after the first arithmetic processing of the first arithmetic processor. The second arithmetic processing is repeatedly executed for each frame with a delay of one frame or more, and the first arithmetic processor is
The third arithmetic process delayed from the second arithmetic process by at least one frame or more is newly added to the first arithmetic process.
It is characterized in that it is repeatedly executed for each frame together with the calculation processing of.

[0011]

In the present invention, one data is related to two
A series of processing from the first arithmetic processing to the third arithmetic processing, which is executed by one arithmetic processing processor, is executed in a plurality of frame times, but each arithmetic processor executes the processing assigned to itself for each frame. Then, arithmetic processing is performed on the data input in time series.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the processing sequence of the embodiment of the present invention.

The circuit configuration of this embodiment is the same as that of the conventional example shown in FIG. 2, and the processing contents of the configuration circuit are also the same as those of the conventional example. In the present embodiment, the waiting time of the DSP is eliminated by changing the processing order so that a plurality of processes that were conventionally executed in one frame are sequentially delayed by one frame and then executed, and voice recognition is performed in frame units. Output the result. The processing order of this embodiment will be described below.

In FIG. 1, when the first DSP 10 inputs the characteristic parameter used for voice recognition at time t, the first arithmetic processing is executed and the arithmetic result P (t) is delivered to the buffer 15. At the next time t + 1, the calculation result at time t is delivered to the second DSP 20 as P ′ (t). The second DSP 20 performs the second calculation at time t + 2 using the calculation result of the first DSP 10 at time t. The calculation result Q (t) is transferred to the buffer 15 and is transferred from the buffer 15 to the first DSP 10 at time t + 3. The first DSP executes the third arithmetic processing on the second arithmetic result Q ′ (t) at time t + 4 and outputs the voice recognition result.
Although the first DSP also performs the first arithmetic processing at time t + 4 as in the conventional case, the characteristic parameter used for the first arithmetic processing at this time is the data input at time t + 4. The above is the processing order until the characteristic parameter at time t is converted to the voice recognition result at time t + 4.

The first DSP 10 repeats the first arithmetic processing and the third arithmetic processing at each time. Therefore, the first DSP can output the voice recognition result at regular intervals.

In this embodiment, since the data transfer between the respective structures is synchronized for each frame, the first DSP 10 and the second DSP 10 are different from the conventional example in which the data transfer is performed within one frame.
The DSP 20 eliminates the waiting time during data transfer with the other party. Therefore, the length of one frame can be shortened by the shortened waiting time.

More specifically, the conventional one frame length is the time of the first and third arithmetic processing of the first DSP 10 + the data transfer time of the buffer 15 + the second arithmetic processing time of the second DSP 20. is there. In the present embodiment, the time for the first and third arithmetic processing, the data transfer time of the buffer 15, or the second
The maximum time of any one of the second arithmetic processing times of the DSP 20 is 1 frame length.

In addition to this embodiment, the following example can be carried out.

(1) In this embodiment, the first DSP 10
Although an example in which a data transfer buffer is provided between the second DSP 20 and the second DSP 20 is shown, it is not necessary to provide a buffer in particular, and data can be directly transferred between the first DSP 10 and the second DSP 20. it can. In this case, communication control signals for data transfer are exchanged between the two processors. Further, in this embodiment, the buffer 15 is the first DSP.
It is used for both input and output of 10 data,
Two buffers may be used for input and output.

(2) In this embodiment, the case where the voice recognition processing is executed by two DSPs is taken as an example, but two or more DSPs are connected in series and the processing result of the most downstream DSP is used. The present invention can also be applied to a case where a DSP other than the most downstream one executes the arithmetic processing again.

(3) In this embodiment, three DSP-related processes are executed by two DSPs.
The number of processes executed by one DSP may be three or more. In this case, the frame timings of the processes executed by the two DSPs for the related data to be exchanged will be different.

[0023]

As described above, according to the present invention, the waiting time of each arithmetic processing processor is eliminated and the frame length can be shortened, which can contribute to the improvement of the voice recognition accuracy.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a processing order of an embodiment of the present invention.

FIG. 2 is a block diagram showing a partial configuration of a voice recognition device.

FIG. 3 is an explanatory diagram showing a processing order of a conventional example.

[Explanation of symbols]

 10 First Digital Processor (First DSP) 15 Buffer 20 Second Digital Processor (Second DSP)

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kazuya Takeda 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (72) Inventor Shingo Kuroiwa 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo No. International Telegraph and Telephone Corporation

Claims (1)

[Claims] 1. A first arithmetic processor executes a first arithmetic processing, a second arithmetic processor executes a second arithmetic processing using the first arithmetic result, and a second arithmetic processing is executed.
In the speech recognition method, wherein the third arithmetic processing is executed by the first arithmetic processor by using the arithmetic processing result of 1., and the processing related to the speech recognition is repeatedly executed for each frame, wherein the second arithmetic processor is After the first arithmetic processing of the first arithmetic processor, the second arithmetic processing is repeatedly executed for each frame with a delay of at least one frame or more, and the first arithmetic processor is configured to execute the second arithmetic processing. A speech recognition method, characterized in that the third arithmetic processing delayed from the arithmetic processing by at least one frame or more is repeatedly executed for each frame together with the new first arithmetic processing.