JPH0621389A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce area occupied by a gate electrode in a plane and to contract unit cell area, for realizing the miniaturization of a device, by forming the gate electrode, isolated by the bottom part of a groove formed on the surface of a semiconductor substrate, on the side walls of the groove through the medium of gate insulating films. CONSTITUTION:A groove is formed by etching the surface of a semiconductor substrate 1 of one conductivity type, and gate oxide films 6 are formed by thermal oxidation. After that, n<->-type impurity regions 7 and 8 are formed in the bottom part of the groove and on the surface of the substrate 1 near the groove, by implanting n-type impurity ions. Next a polycrystalline silicon film 9 are deposited, and transfer gate electrodes 10 are formed on the side walls of the groove by etching. Following this, gate oxide films 6 are wet-etched using these electrodes 10 as masks, and CVD oxide films are deposited and etched back. On this occasion, parts of the films are left unremoved so as to cover the gate electrodes 10, and interlayer insulating films 14 are formed. Following this, thermally oxidized films 15 and polycrystalline silicon films 16 are formed, and capacitor electrodes 17 are formed by etching these selectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a MOS dynamic RAM and its manufacturing method.

[0002]

2. Description of the Related Art An example of the structure of a conventional MOS dynamic RAM will be described with reference to FIGS.
Incidentally, FIG. 17 is a sectional view taken along the line AA of FIG.

Reference numeral 41 in the drawing is, for example, a p-type silicon substrate, and a field oxide film 42 is formed on the surface of the substrate 41. An n-type impurity region 43 to be a substrate-side electrode of the capacitor is formed on a part of the surface of the substrate 41 surrounded by the field oxide film 42. A capacitor electrode 45 is formed on the n-type impurity region 43 via a capacitor oxide film 44, and an interlayer insulating film 46 is formed on the surface of the capacitor electrode 45. A transfer gate electrode 48 ₁ is formed on the surface of the substrate 41 other than the cell capacitors via a gate oxide film 47 and extends to an adjacent memory cell (not shown). In addition, the transfer gate electrode 4 extended from an adjacent memory cell (not shown) on the interlayer insulating film 46.
8 ₂ are formed. The transfer gate electrode 4
N ⁺ -type impurity regions 49 and 50 serving as source and drain regions are formed on the surface of the substrate 41 on both sides of 8 ₁ .

The above-mentioned MOS DRAM is called a one-transistor one-capacitor type, and its operation is as follows. That is, at the time of writing, information charges are applied to the n ⁺ -type impurity region 50, and the transfer gate electrode 4
When 8 ₁ is selected, the information charges are transmitted to the n-type impurity region 43 via the n ⁺ -type impurity region 49. n
The type impurity region 43 faces the capacitor electrode 45 via the capacitor oxide film 44, and, for example, a certain capacitance exists between the capacitor electrode 45 fixed to the ground potential and the n-type impurity region 43. Therefore, charges are accumulated.
In this state, if the transfer gate electrode 48 _{1 is set} to the non-selected state, the data is retained. Further, when the transfer gate electrode 48 ₁ is brought into a selected state during reading, the charges accumulated in the n-type impurity region 43 are transferred to the n ⁺ -type impurity region 50.

[0005]

DISCLOSURE OF THE INVENTION The conventional MOS described above
In the DRAM, the n-type impurity region 43 and the capacitor oxide film 4
4 and a cell capacitor composed of a capacitor electrode 45,
The transfer transistor including the transfer gate electrode 48 ₁ , the gate oxide film 47 and the n ⁺ type impurity regions 49 and 50 is on the same plane. Therefore, the area per unit cell is taken up by the cell capacitor and the transfer transistor. Therefore, such a structure has a problem in that it cannot cope with the reduction in the unit cell area which accompanies the recent trend of increase in storage capacity.

In addition, with the miniaturization of the device, electric field concentration occurs in the channel regions near the n ⁺ type impurity regions 49 and 50, which are the source and drain regions, and the threshold voltage of the transistor caused by the generation of hot carriers occurs. Problems such as fluctuations occur.

The present invention has been made in view of the above circumstances, and has a large capacity and good device characteristics capable of reducing the area per unit cell and preventing electric field concentration in the channel region near the source and drain regions. Another object of the present invention is to provide a simple semiconductor device and a method capable of manufacturing such a semiconductor device by a simple method.

[0008]

In order to achieve the above object, according to the present invention, the gate insulating film is formed on both side walls of a groove formed on the surface of a semiconductor substrate of one conductivity type, and is separated at the groove bottom. A plurality of independently controllable gate electrodes, a low-concentration impurity region near the gate electrode and a high-concentration impurity region adjacent to the low-concentration impurity region formed in a plurality of regions on the substrate surface around the groove bottom and the groove A semiconductor device comprising: an impurity region having a conductivity type opposite to that of a substrate; and a capacitor electrode formed on the impurity region of the substrate surface at the bottom of the groove with a capacitor insulating film interposed therebetween.

Further, a step of etching the surface of the semiconductor substrate of one conductivity type by anisotropic etching to form a groove,
A step of forming a gate insulating film on the surface of the substrate, a step of ion-implanting impurities of a conductivity type opposite to that of the substrate at a low dose, and a gate electrode material is deposited on the entire surface, and then the gate electrode material is etched by anisotropic etching. Then, a step of forming a plurality of independently controllable gate electrodes on the sidewalls of the trench via the gate insulating film, and using the gate electrodes as a mask, impurities of the opposite conductivity type to the substrate are ion-implanted at a high dose, and the trench bottom and A step of forming an impurity region of a conductivity type opposite to that of the substrate, which is composed of a low-concentration impurity region near the gate electrode and a high-concentration impurity region adjacent to the low-concentration impurity region in a plurality of regions around the trench, and an insulating film is deposited on the entire surface. After that, a step of etching the insulating film by anisotropic etching to leave the insulating film so as to cover the gate electrode and the capacitor on the substrate surface other than the region where the gate electrode is formed A step of forming an edge film and a step of depositing a capacitor electrode material on the entire surface and then etching a part thereof to form a capacitor electrode on the impurity region of the substrate surface at the bottom of the groove via the capacitor insulating film. Provided is a method for manufacturing a semiconductor device characterized by the above.

[0010]

In the semiconductor device of the present invention, since the gate electrode is formed on the side wall of the groove, the area occupied by the gate electrode on the plane can be reduced and the unit cell area can be reduced. Further, since the impurity regions serving as the source and drain regions have a so-called LDD structure, good device characteristics can be maintained even if the device is miniaturized. Further, according to the manufacturing method of the present invention, the semiconductor device can be manufactured by extremely simple steps.

[0011]

Embodiments of the present invention will be described below with reference to FIGS.

First, for example, a part of the surface of the p-type silicon substrate 1 is selectively etched by reactive ion etching (hereinafter abbreviated as RIE) to have, for example, a width of 1.8 μm.
A groove 2 having a depth of m and a depth of 1.5 μm is formed (FIG. 1). next,
After etching a part of the surface of the substrate 1 by isotropic etching or anisotropic etching with slightly isotropic etching, for example, to form a device isolation groove 3 having a width of 0.8 μm and a depth of 0.8 μm, Ion implantation is performed to prevent field inversion. Subsequently, a CVD oxide film 4 having a thickness of 5000 Å, for example, is deposited on the entire surface. As a result, since the element isolation trench 3 has a narrow width, it is in a state of being filled with the CVD oxide film 4. However, in the trench 2, the bottom surface and the side wall have a thickness of 5000.
The CVD oxide film 4 of Angstrom is deposited (FIG. 2). Then, CVD oxide film 4 is formed by RIE.
Is etched back to bury the CVD oxide film 4 only in the element isolation trench 3 to form a field oxide film 5 (FIG. 3). A plan view after the steps up to FIG. 3 is shown in FIG. That is, the region surrounded by the field oxide film 5 is a memory cell region for 2 bits, and the central portion thereof is in a state in which the trench 2 is extended in parallel over many adjacent memory cells.

Next, a gate oxide film 6 having a thickness of, for example, 120 Å is formed on the exposed surface of the substrate 1 by thermal oxidation.
To form. Then, add n-type impurities such as As ⁺ to 1
Ion implantation is performed at a relatively low dose of about 0 ¹³ cm ^-2 .
As a result, n ⁻ type impurity regions 7 and 8 are formed after the heat treatment on the surface substantially perpendicular to the ion flux, that is, on the bottom of the groove 2 and the surface of the substrate 1 around the groove 2. Subsequently, a polycrystalline silicon film 9 having a thickness of 3000 angstrom, for example, is deposited on the entire surface (FIG. 4). After that, the polycrystalline silicon film 9 is RI
The transfer gate electrode 10 is formed by etching with E so that the side wall of the groove 2 remains at a height of 1.2 μm, for example. These transfer gate electrodes 10 extend along the sidewalls of the trench 2 over a large number of memory cells and serve as word lines. Next, the transfer gate electrode 10
Is used as a mask to remove n-type impurities such as As ⁺ from 10 ¹⁵ cm ^-2.
Ion implantation is performed at a relatively high dose amount. As a result,
After the heat treatment, diffusion of impurities from the n ⁻ -type impurity regions 7 and 8 or diffusion of impurities that may be regarded as being low-dose ion-implanted obliquely to the sidewall of the upper end portion of the groove 2 during high-dose ion implantation causes On the surface of the substrate 1, an n ⁻ -type impurity region 11a near the transfer gate electrode 10 is formed.
And an n-type impurity region 11 composed of an n ⁺ -type impurity region 11b adjacent to these regions is adjacent to the n ⁻ -type impurity region 12a near the transfer gate electrode 10 and these regions on the surface of the substrate 1 around the trench 2. n ⁺ type impurity region 1
The n-type impurity regions 12 made of 2b are formed (FIG. 5). Then, after the gate oxide film 6 is wet-etched using the transfer gate electrode 10 as a mask, a CV having a thickness of 3000 angstrom is formed on the entire surface.
A D oxide film 13 is deposited (FIG. 6). Subsequently, the CVD oxide film 13 is etched back by RIE and left so as to cover the transfer gate electrode 10, and the interlayer insulating film 14 is formed.
Are formed (FIG. 7).

Then, a thermal oxide film (capacitor oxide film) 15 having a thickness of 100 angstrom, for example, is formed on the surface of the substrate 1 exposed by thermal oxidation, and then, for example, a thickness of 3 is applied on the entire surface.
A polycrystal silicon film 16 of 000 angstrom is deposited (FIG. 8). Subsequently, the polycrystalline silicon film 16 is selectively etched using a photoresist pattern (not shown) as a mask to form a capacitor electrode 17 on the n-type impurity region 12 around the trench 2 via a capacitor oxide film 15. Subsequently, after removing the photoresist pattern, thermal oxidation is performed to form an interlayer insulating film 18 on the surface of the capacitor electrode 17. Next, using the photoresist pattern (not shown) as a mask, the n-type impurity region 11 at the bottom of the groove 2 is formed.
After etching the thermal oxide film on the surface, the photoresist pattern is removed (FIG. 9). Then, for example, Al on the entire surface
After depositing the film, patterning is performed to form a bit line 19 extending in a direction orthogonal to the transfer gate electrode 10 to manufacture a MOSDRAM (FIG. 10).

Therefore, the MOSDRAM shown in FIG.
Is the gate oxide film 6 on the sidewall of the groove 2 formed on the surface of the substrate 1.
Since the transfer gate electrode 10 is formed through the transfer gate electrode 10, the area occupied by the transfer transistor in the unit cell area on the plane can be made extremely small, and the unit cell area itself can be reduced. Also,
N-type impurity regions 11 and 12 serving as source and drain regions
Is a so-called LDD (Lightly Doped Drain) composed of an n ⁻ type impurity region near the transfer gate electrode 10 and an n ⁺ type impurity region adjacent to the n ⁻ type impurity region.
Since it has an and source structure, electric field concentration in the channel region in the vicinity of the drain region can be mitigated, and deterioration in reliability of the transistor due to generation of hot carriers can be prevented.

Further, according to the method of the above embodiment, only the low dose ion implantation in the step of FIG. 4 and the high dose ion implantation using the transfer gate electrode 10 as a mask in the step of FIG. It is possible to form the n-type impurity regions 11 and 12 to be the source and drain regions of the structure, and LD
Unlike the case of forming the source and drain regions of the D structure, there is no need to form a spacer on the sidewall of the gate electrode, which is a mask of high dose ion implantation made of, for example, a CVD oxide film. The channel length of the transfer transistor is shown in FIG.
Is determined by the depth of the groove 2 formed in the step of
Since the unit cell area on the plane does not increase even if the channel length is made long (that is, the groove 2 is made deep), it is possible to prevent the leakage of charges due to the deterioration of the subthreshold characteristics due to the shortening of the channel, and the reliability of the DRAM is deteriorated. Can be prevented. Further, in order to make contact between the n ⁺ type impurity region 11b and the bit line 19 in the process of FIG. 10, the oxide film on the n ⁺ type impurity region 11b is removed using a photoresist pattern (not shown) as a mask. Since the mask alignment accuracy in the process is not so required, the self alignment connection (Self Align Contact) between the bit line 19 and the n ⁺ type impurity region 11b is possible. As described above, the cell area can be greatly reduced and the reliability of the DRAM can be improved by an extremely simple process.

In the above embodiment, n on the substrate surface around the groove is
Although the cell capacitor was formed using the type impurity region and the n-type impurity region on the substrate surface at the bottom of the groove was connected to the bit line, this configuration is reversed, and the n-type impurity region on the substrate surface around the groove is changed to the bit line. And the cell capacitor may be formed by using the n-type impurity region on the substrate surface at the bottom of the groove. Such a MOS DRAM will be described with the manufacturing method shown in FIGS.

First, after forming the groove 22 and the element isolation groove 23 on the surface of the p-type silicon substrate 21 in a step corresponding to FIGS. 1 to 3, for example, a CVD oxide film is buried only in the element isolation groove 23. A field oxide film 24 is formed. At this stage, the peripheral portion of the groove 22 (protruding portion between the groove 22)
Is located in the center of the memory cell area for 2 bits surrounded by the field oxide film 24 (FIG. 12). Next, in steps corresponding to FIGS. 4 to 7, formation of the gate oxide film 25, low-dose ion implantation of n-type impurities, formation of the transfer gate electrode 26 on the sidewall of the groove 22, high-dose ion implantation of n-type impurities, etc. By the process of
An n-type impurity region 27 composed of an n ⁻ -type impurity region 27a near the transfer gate electrode 26 and an n ⁺ -type impurity region 27b adjacent to these regions is formed on one surface, and the transfer gate electrode 26 is formed on the surface of the substrate 21 around the groove 22. Neighborhood n
^The n-type impurity regions 28 each including the −-type impurity regions 28a and the n ⁺ -type impurity regions 28b adjacent to these regions are formed. Then, the transfer gate electrode 26
An interlayer insulating film 29 is formed so as to cover (FIG. 13). Next, after forming a capacitor oxide film 30 in a process corresponding to FIGS. 8 and 9, for example, a polycrystalline silicon film is deposited on the entire surface and is patterned to form a capacitor on the n-type impurity region 27 at the bottom of the groove 22. A capacitor electrode 31 is formed via the oxide film 30. Next, the capacitor electrode 31
After forming the interlayer insulating film 32 on the surface, the oxide film on the surface of the n-type impurity region 28 around the groove 22 is selectively etched to expose the n-type impurity region 28 (FIG. 14). Then
In the process corresponding to FIG. 10, for example, an Al film is vapor-deposited on the entire surface and then patterned to form an n-type impurity region 28 around the groove 22.
A bit line 33 connected to is formed and a MOSDRAM is manufactured (FIG. 15).

Therefore, the MOSDRAM shown in FIG.
Also, the method shown in FIGS. 12 to 15 can obtain the same effect as that of the above embodiment. However, the MO shown in FIG.
In the SDRAM, it is desirable to widen the lateral width of the n-type impurity region 28 around the groove 22 in order to prevent mutual interference between the two transfer transistors.

In the above description, the method of burying the insulating film in the element isolation groove is used to form the field insulating film. However, if it is a fine element isolation method having a good surface flatness, a selective oxidation method may be used. Good.

Further, in the embodiment, high dose ion implantation of As.sup. ⁺ Was performed in the state of the gate oxide film 6 on the entire surface of the substrate 1 in the process of FIG. 5, but this high dose ion implantation was performed on the transfer gate electrode 10. It may be performed after etching the exposed portion of the gate oxide film 6 as a mask.

Further, although polycrystalline silicon is used as the material of the transfer gate electrode and the material of the capacitor electrode in the embodiment, the material is not limited to this, and metal or metal silicide may be used.

[0023]

As described in detail above, according to the present invention, it is possible to provide a semiconductor device having a large capacity and good element characteristics, and a method capable of manufacturing such a semiconductor device in a simple process.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a plan view of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 13 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 14 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 15 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 16 is a sectional view of a conventional semiconductor device.

FIG. 17 is a sectional view of a conventional semiconductor device.

[Explanation of symbols]

1, 21 p-type silicon substrate 2, 22 groove 3, 13 CVD oxide film 4, 23 element isolation groove 5, 24 field oxide film 6, 25 gate oxide film 7, 8 n ^- type impurity region 9 polycrystalline silicon film 10 , 26 transfer gate electrodes 11a, 12a, 27a, 28a n ⁻ type impurity regions 11b, 12b, 27b, 28b n ⁺ type impurity regions 11, 12, 27, 28 n type impurity regions 14, 18, 29, 32 interlayer insulating film 15, 30 Capacitor oxide film 16 Polycrystalline silicon film 17, 31 Capacitor electrode 19, 33 Bit line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7377-4M H01L 29/78 301 M

Claims (3)

[Claims] 1. A plurality of independently controllable gate electrodes formed on both side walls of a groove formed on a surface of a semiconductor substrate of one conductivity type with a gate insulating film interposed therebetween, and independently controllable. And an impurity region of a conductivity type opposite to that of the substrate, which is formed in a plurality of regions on the surface of the substrate around the trench, the impurity region having a low concentration impurity region near the gate electrode and a high concentration impurity region adjacent to the low concentration impurity region, and the trench. A semiconductor device comprising: a capacitor electrode formed on the impurity region of the substrate surface at the bottom via a capacitor insulating film. 2. A step of forming a groove by etching the surface of a semiconductor substrate of one conductivity type by anisotropic etching, a step of forming a gate insulating film on the surface of the substrate, and a low dose of impurities of a conductivity type opposite to that of the substrate. A step of implanting a large amount of ions, and after the gate electrode material is deposited on the entire surface, the gate electrode material is etched by anisotropic etching, and a plurality of gate electrodes that can be independently controlled on the sidewalls of the trench via a gate insulating film. And a low-concentration impurity region near the gate electrode and the low-concentration impurity region near the gate electrode in a plurality of regions near the groove bottom and around the groove by ion-implanting impurities of a conductivity type opposite to that of the substrate with the gate electrode as a mask. A step of forming an impurity region of a conductivity type opposite to that of the substrate composed of a high-concentration impurity region adjacent to the high-concentration impurity region; and, after depositing an insulating film on the entire surface, anisotropically etching the insulating film. Etching, leaving an insulating film to cover the gate electrode, forming a capacitor insulating film on the substrate surface other than the region where the gate electrode is formed, and after depositing a capacitor electrode material on the entire surface, And a step of etching a part thereof to form a capacitor electrode on the impurity region on the substrate surface at the bottom of the groove with a capacitor insulating film interposed therebetween. 3. After forming the groove, a part of the substrate is further selectively etched to form a groove for element isolation, and an insulating film is embedded in the groove for element isolation. A method for manufacturing a semiconductor device as described above.