JPH0621339A - Manufacture of semiconductor memory and recording method for semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the decrease of capacitance after reading/writing of 10<15> time without the generation of a space charge due to polarization and inversion by forming a ferroelectric film on an electrode on a semiconductor substrate and applying an electric field between a surface and an electrode and polarizing the ferroelectric film at a temperature below a transition temperature. CONSTITUTION:A silicon dioxide film 102 is formed as a layer insulating film on a silicon substrate 101, and then Pt 104 of a lower electrode is formed through Ti 103 of a contact layer, and polycrystalline PZT 105 polycrystalline/ showing a ferroelectric characteristic is laminated thereon, and after that, heat treatment is applied to the PZT film 105 with a corona discharge in air, and an external voltage 106 is controlled so that a voltage applied to the PZT film becomes 5 volts. Consequently, a dipole moment in each divided region is oriented in the direction of a bias voltage, and the PZT film 105 is polarized. After that, the succeeding processes are carried out in the temperature below the transition temperature of the PZT film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method and a recording method of a ferroelectric capacitor mainly used in a dynamic random access memory (DRAM).

[0002]

2. Description of the Related Art Conventionally, for example, eye triple e-electron device letters (IEEE ELEC)
TRON DEVICE LETTERS) 1990
As described in Vol. 11, No. 10, Item 454 to Item 456, the read / write characteristics of a DRAM using a ferroelectric as a charge storage capacitor had a problem in reliability. .

That is, in the conventional manufacturing method, since the ferroelectric film is made of polycrystal and is not subjected to the polarization treatment (poling) during the manufacturing, each domain (domain) in the ferroelectric film immediately after the manufacturing. Has a dipole moment, but
Since they are oriented randomly with respect to each other, the total polarization, that is, the spontaneous polarization is zero.

After that, when used as a DRAM, an electric field is applied to the ferroelectric film, so that the directions of the dipole moments are aligned in each domain, and polarization occurs in the entire ferroelectric film.

[0005]

However, when the semiconductor memory device manufactured by the conventional manufacturing method is operated as a DRAM, there are the following problems.

In the case of a ferroelectric substance, the above-mentioned polarization is caused by displacement of relative positions between constituent atoms having different polarities,
Due to this, there is a problem that space charge is generated in the PZT and a non-volatile memory using polarization reversal causes deterioration of remanent polarization. On the other hand, even in the case of a DRAM not using polarization reversal. However, there is a problem that the capacitance is deteriorated.

A conventional example will be described based on the graph of capacitance against bias voltage in FIG.

The solid line in FIG. 2 shows the voltage dependence of the capacitance per unit area at the initial stage, and the broken line shows the voltage dependence of the capacitance per unit area after 10 ¹⁰ read / write operations.

The arrows in the figure correspond to when the voltage is raised and when the voltage is lowered.

In this way, for example, when the voltage is boosted and compared at 3 V, it is changed from 100 fC / μm ² to 80 fC / μm ² by 20.
A decrease in% capacitance is seen.

Therefore, the present invention is intended to solve such a conventional problem, and an object of the present invention is to perform a polarization process during the manufacture of a semiconductor memory device and to perform the process after the polarization process. By not reversing the dipole moment of each domain, and by never reversing the dipole moment of each domain even during DRAM operation, that is, by not displacing between constituent atoms having different polarities, To provide a method for manufacturing a ferroelectric memory device that suppresses the generation of space charges in a ferroelectric thin film and shows almost no decrease in capacitance even when reading / writing is performed 10 ¹⁵ times, and a recording method. is there.

[0012]

A method of manufacturing a semiconductor memory device according to the present invention comprises: (1) forming an electrode on a semiconductor substrate; forming a ferroelectric film on the electrode; A step of polarizing the ferroelectric film by applying an electric field between the surface of the ferroelectric film and the electrode, and polarizing the ferroelectric film at a temperature lower than the transition temperature of the ferroelectric film. It is characterized in that the process after the process is performed.

(2) A step of forming a first electrode on a semiconductor substrate, a step of forming a ferroelectric film on the first electrode, and a step of forming a second electrode on the ferroelectric film. A step of polarizing the ferroelectric film by applying an electric field between the first electrode and the second electrode, and a step of removing the second electrode, the temperature being less than a transition temperature of the ferroelectric film. It is characterized in that the steps after the step of removing the second electrode at a temperature are performed.

According to another aspect of the present invention, there is provided a recording method for a semiconductor memory device, wherein the ferroelectric film is applied by applying an electric field in the same direction as a polarization direction of the ferroelectric film of the semiconductor memory device. Is operated as a charge storage capacitor.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIGS.
A description will be given based on the sectional view of the manufacturing step in (c).

As shown in FIG. 1A, a silicon substrate 10
On top of which a silicon dioxide film (SiO ₂ ) 1 is formed as an interlayer insulating film.
02 is formed, then Pt104 of the lower electrode is formed through Ti103 of the adhesion layer, and polycrystalline lead zirconate titanate Pb (Zr _0.5 Ti _0.5 ) showing ferroelectric characteristics is formed thereon.
O _3, laminating the PZT105 for short.

The SiO ₂ 102 was formed by the plasma chemical vapor deposition method of tetra ethyl ortho silicate (TEOS), and its film thickness was 5000 Å.

Ti and Pt were formed by a DC sputtering method, and the film thickness was set to 200 Å and 5000 Å, respectively.

The PZT 105 is deposited, for example, by a high frequency magnetron sputtering method using Pb _1.1 (Zr _0.5 Ti _0.5 ) O _3.1 containing 10% excess of PbO as a target,
Then, in order to obtain the ferroelectric characteristics, in an oxygen atmosphere, 50
Heat treatment at 0 ° C. for 1 hour.

By this heat treatment, a polycrystalline PZT having a perovskite crystal structure with a film thickness of 5000 Å could be obtained.

FIG. 1 (a) shows the direction of polycrystal grains and their dipole moments.

The particle size is about 2000Å.

Here, for simplicity, it is assumed that one grain has one domain.

Since the domains crystallized by the heat treatment are oriented in various directions, the polarization value of the entire PZT thin film is 0.

Next, as shown in FIG. 1B, an electric field is applied to the PZT film 105 by using corona discharge in air.

The external voltage 106 is applied to the needle 107 facing the Pt 104, and the voltmeter 108 controls the external voltage 106 so that the voltage applied to the PZT film 105 becomes 5V.

5V is the same as the voltage applied to the PZT capacitor after the semiconductor memory device is manufactured. Where the needle 10
The distance between 7 and the surface of the PZT film 105 was set to 20 mm.

As a result, as shown in FIG. 1 (c), the dipole moments in each domain are aligned in the bias voltage direction,
The PZT film 105 is polarized.

Then, the subsequent steps are performed at a temperature lower than the transition temperature of the PZT film to manufacture a semiconductor memory device.

The transition temperature referred to here is the temperature at which the crystal structure changes from a ferroelectric substance to a paraelectric substance, and if the temperature is raised above the transition temperature, the dipole moment in each domain will be oriented. It returns to various directions, and the remanent polarization becomes zero.

Here, for example, the transition temperature of PZT is 42.
Since the temperature is 0 ° C., the process after polarization treatment, for example, SiO ₂
It is necessary to perform the formation of an interlayer insulating film such as the above, the sputtering of aluminum for wiring, the etching, the formation of a passivation film such as SiO ₂ , a silicon nitride film (Si ₃ N ₄ ) and the like at less than 420 ° C.

Desirably, the temperature should be low, 300
It is even more preferable that the temperature is ℃ or less.

In the above embodiment, the number of the needles 107 is one, but the number of the needles may be any number and the PZT film 1 may be used.
The needle 107 may be scanned within the wafer surface while maintaining a constant distance from 05.

Next, a second embodiment of the present invention will be described based on the manufacturing process sectional views of FIGS. 3 (a) to 3 (d).

FIG. 3A is a sectional structural view after the Pt upper electrode 109 is formed on the PZT film 105 after the step shown in FIG. 1A.

The Pt upper electrode 109 was formed by the DC sputtering method and had a film thickness of 5000 Å.

Next, as shown in FIG. 3B, the upper electrode 1
09 and the lower electrode 104, by applying a voltage of 5V,
The PZT film 105 is polarized, and the result is shown in FIG.
As shown in (c), the dipole moment of each domain aligns with the direction of the bias voltage.

Next, as shown in FIG. 3D, the Pt upper electrode 109 is removed by, for example, ion milling using argon as a gas.

At this time, it should be noted that the temperature of the substrate does not rise above the transition temperature while cooling the substrate.

Here, the reason why the upper electrode 109 is once removed is to release the stress due to the polarization of the PZT film 105.

After that, the Pt upper electrode 109 is again made into PZT.
After forming by the DC sputtering method below the transition temperature of the film,
Similar to the first embodiment, the semiconductor memory device is manufactured by subsequently performing the subsequent steps at a temperature equal to or lower than the transition temperature of the PZT film.

Next, FIG. 4 is a sectional structural view of a semiconductor memory device in which PZT is integrated on a semiconductor substrate on which active elements are actually formed by using the manufacturing process of the first and second embodiments of the present invention. Show.

101 is a silicon substrate, 401 is a diffusion layer formed by ion implantation and heat treatment, 402 is a gate oxide film made of SiO ₂ , and 403 is a gate formed of polycrystalline silicon and tungsten silicide (WSi). It is an electrode and forms the main part of the field effect transistor.

404 is an interlayer insulating film made of SiO ₂ .
Reference numeral 405 is an aluminum wiring, which is used for the upper electrode 109 and the diffusion layer 4.
01 is connected.

In the case of this embodiment, as the process after the polarization treatment, it is necessary to perform the following process at a temperature lower than the transition temperature of the PZT film 105.

Step of depositing upper electrode 109, upper electrode 10
9, PZT film 105, lower electrode 104 and Ti 103 etching step, SiO ₂ 404 deposition step, SiO ₂ 4
04 and 102 etching process, aluminum wiring 405 deposition process, and etching process.

Next, a recording method of a semiconductor memory device manufactured by using the manufacturing method shown in the first and second embodiments of the present invention will be described with reference to the sectional structural views of FIGS. 5A and 5B. .

FIG. 5A shows the direction of the dipole moment in the domain of the PZT film before the operation of the DRAM.

Now, the dipole moment points downward.

This dipole moment is due to the spontaneous polarization of the ferroelectric substance.

Next, during the DRAM operation, as shown in FIG. 5B, data is written by applying a bias voltage of 5 V in the direction of polarization, that is, downward.

The plus (+) / minus (-) written between the PZT film 105 and the upper and lower electrodes 109 and 104 in FIG. 5B is electronic polarization, which is short-circuited after removing the bias voltage. Then, the electric charge disappears, and D
It becomes the data at the time of RAM operation.

On the other hand, the spontaneous polarization of the ferroelectric substance is not inverted and is maintained regardless of the DRAM operation, so that the PZ
Since there is no displacement of the relative position between the constituent atoms of T having different polarities, the reliability characteristics are excellent.

In the present embodiment, the direction of the dipole moment has been described as downward, but it is obvious that the bias voltage during DRAM operation may be upward even when the direction of dipole moment is upward. .

FIG. 6 shows a graph of the capacitance against the bias voltage of the semiconductor memory device manufactured in this embodiment.

The solid line shows the voltage dependence of the capacitance per unit area in the initial stage, and the broken line shows 10 ¹⁰ readings / reading.
The voltage dependence of the capacitance per unit area after writing is shown.

As described above, by using the manufacturing method and the recording method of the present invention, when the semiconductor memory device is actually used, the relative position between the constituent atoms of the ferroelectric substance having different polarities is never displaced. Therefore, even after 10 ¹⁰ times of reading / writing, the capacitance was hardly reduced.

As described above, in this embodiment, PZ is used as the ferroelectric film.
Although described using T, PbTiO ₃ , KNbO ₃ , Pb
It may be an oxide ferroelectric having another perovskite crystal structure such as (MnNb) O ₃ .

In addition, lanthanum (La), neodymium (Nd), bismuth (Bi), niobium (N
b), antimony (Sb), tantalum (Ta) or the like may be used as a dopant.

[0060]

As described above, the semiconductor memory device manufacturing method and the recording method according to the present invention have no displacement of the relative position between the constituent atoms of the ferroelectric substance having different polarities in actual use. The space charge that is normally observed due to polarization inversion does not occur, and even after 10 ¹⁵ times of reading / writing,
There is almost no reduction in capacitance, and it has the effect of providing a highly reliable semiconductor memory device. Furthermore, the ferroelectric film used in the method for manufacturing a semiconductor memory device of the present invention has a dielectric constant of 1000 or more. Since it is large, it is very effective for a highly integrated DRAM having 256 Mbits or more.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a graph of capacitance versus bias voltage of a capacitor used in a conventional semiconductor memory device.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 4 is a sectional structural view of a semiconductor memory device of the present invention.

FIG. 5 is a sectional structural view showing a recording method of the semiconductor memory device of the present invention.

FIG. 6 is a graph of a capacitance versus a bias voltage of a capacitor used in the semiconductor memory device of the present invention.

[Explanation of symbols]

101 Silicon Substrate 102 SiO ₂ 103 Ti 104 Pt 105 PZT 106 External Voltage 107 Needle 108 Voltmeter 109 Upper Electrode 401 Diffusion Layer 402 Gate Oxide Film 403 Gate Electrode 404 SiO ₂ 405 Aluminum Wiring

Claims (3)

[Claims] 1. A method of forming an electrode on a semiconductor substrate, a step of forming a ferroelectric film on the electrode, and applying an electric field between the surface of the ferroelectric film and the electrode, A method of manufacturing a semiconductor memory device, comprising the step of polarizing a ferroelectric film, and performing the steps after the step of polarizing the ferroelectric film at a temperature lower than the transition temperature of the ferroelectric film. 2. A step of forming a first electrode on a semiconductor substrate, a step of forming a ferroelectric film on the first electrode, and a step of forming a second electrode on the ferroelectric film. The first
A step of polarizing the ferroelectric film by applying an electric field between the electrode and the second electrode; and a step of removing the second electrode, wherein the temperature is lower than the transition temperature of the ferroelectric film. A method of manufacturing a semiconductor memory device, comprising performing the steps after the step of removing the two electrodes. 3. The ferroelectric film of the semiconductor memory device according to claim 1, wherein the ferroelectric film is operated as a charge storage capacitor by applying an electric field in the same direction as the polarization direction of the ferroelectric film. Recording method for semiconductor memory device.