JPH06209242A - Clock pulse shaping circuit - Google Patents

Abstract

PURPOSE:To obtain a clock pulse shaping circuit which outputs a clock whose pulse widths at a high level and a low level are stable after the elapse of time more than a fixed time even when an input clock whose pulse width is not constant is changed at any time. CONSTITUTION:A delay clock synthesizing means 9 synthesizes an output (g) of a first output clock delay means 7 with an output (h) of a second output clock delay means 8 which delays an output clock (f) from the delay time of the first output clock delay means 7 by an appropriately shorter time. An output (i) of the means 9 inhibits a rising detection pulse (b) from a rise detecting means 2 detected just before the rise of the output (g) of the first output clock delay means being the clock input to a flip-flop circuit 6 by a rise detection pulse inhibiting means 4, and the simultaneous change of the set input and clock input to the flip-flop circuit 6 is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock shaping circuit for generating a clock having a low-level pulse width and a high-level pulse width both being equal to or longer than a fixed time from a clock having a non-uniform pulse width.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional clock shaping circuit disclosed in Japanese Patent Publication No. 2-56853. In the figure, 1 is a clock input terminal for inputting a clock whose pulse width is not constant, 2 is a rising edge detecting means for detecting a rising edge of the input clock a, 3 is a falling edge detecting means for detecting a falling edge of the input clock a, and 4 is a falling edge detecting means. The rising edge detection pulse inhibiting means 5 for controlling the output b of the rising edge detecting means 2 by the output g of the output clock delaying means 7 which will be described later and the output c of the falling edge detecting means 3 for the rising detection pulse prohibiting means 5 which are controlled by the output g of the output clock delaying means 7 which will be described later. Falling detection pulse prohibiting means 6 has a set input S, a reset input R, a clock input T and a data input D, and the output d of the rising detection pulse prohibiting means 4 is connected to the set input S to generate a falling detection pulse. The output e of the prohibiting means 5 is connected to the reset input R,
An output clock delay means 7 to be described later is connected to a clock input T and a data input D is fixed to a low level, a flip-flop, 7 is an output clock delay means for delaying an output clock f by T1 time, and 10 is a shaping. It is a clock output terminal that outputs the generated clock f.

Next, the operation of the conventional example will be described with reference to FIG. 4, which is an example of the operation timing chart of FIG. The input clock a having a non-uniform pulse width input from the clock input terminal 1 is input to the rising edge detecting means 2, the rising edge detecting means 2 detects the rising edge of the input clock a, and outputs the rising edge detecting pulse b. Further, the input clock a is input to the falling edge detecting means 3, the falling edge detecting means 3 detects the falling edge of the input clock a, and outputs the falling edge detecting pulse c.

The rising edge detection pulse inhibiting means 4 allows the rising edge detection pulse b from the rising edge detecting means 2 to pass when the delay clock g from the output clock delaying means 7 which will be described later is at a low level, and the flip-flop 6 as a set pulse d. To the set input S of. Further, the fall detection pulse inhibiting means 5 is provided for the fall detection means 3 when the delay clock g from the output clock delay means 7 described later is at a high level.
The trailing edge detection pulse c from is passed and is output to the reset input R of the flip-flop 6 as the reset pulse f.

The flip-flop 6 is set by the set pulse d from the rising detection pulse inhibiting means 4 and reset by the reset pulse e from the falling detection pulse inhibiting means 5 and is output from the output clock delay means 7 described later. At the rising edge of the delay clock g, the low-level signal input to the data input D is always taken in, and the shaped output clock f whose high-level and low-level pulse widths are both equal to or longer than a fixed time is output.

The output clock delay circuit 7 delays the output clock f from the flip-flop 6 by a time T1 corresponding to the minimum required pulse width of low level and high level, and outputs it as a delayed clock g.

Next, as an initial state, the flip-flop 6
The specific operation will be described by setting the output clock f output by the output clock f and the delay clock g output by the output clock delay unit 7 to the high level. The change from the high level to the low level of the input clock a at the time t1 is detected by the falling edge detecting means 3, and the falling edge detecting means 3 outputs the falling edge detecting pulse c. The delay clock g that is the output of the output clock delay means 7 at time t1
Is a high level, the fall detection pulse inhibiting means 5
Passes the falling detection pulse c from the falling detection means 3, resets the flip-flop 6 as a reset pulse e, and outputs the output clock f from the flip-flop 6.
To low level.

The delayed clock g which is the output of the output clock delay means 7 has a time t1 at which time T1 elapses from time t1
Since it is at a high level until 4, the rising detection pulse b detected by the rising detection means 2 at the time t2 between the times t1 and t4 is prohibited by the rising detection pulse prohibiting means 4. Therefore, the set pulse d that sets the flip-flop 6 is not output, and the output clock f that is the output of the flip-flop 6 is held at the low level.
Further, the fall detection pulse c detected by the fall detection means 3 at the time t3 between the times t1 and t4 passes through the fall detection pulse prohibition means 5 and resets the flip-flop 6 again as a reset pulse e. However, the output clock f, which is the output of the flip-flop 6, does not change at a low level.

As described above, the output clock f of the flip-flop 6 is maintained at the low level for at least the time T1 after changing to the low level. In other words, the output clock f whose low-level pulse width is equal to or longer than the constant time T1 is obtained.

The change from the low level to the high level of the input clock a at the time t5 is detected by the rising edge detecting means 2 and the rising edge detecting means 3 is detected by the rising edge detecting pulse b.
Is output. Time t4 when time T1 has elapsed from time t1
At the time t5, the delay clock g output from the output clock delay means 7 changes from the high level to the low level.
Is low level, the rising edge detection pulse prohibiting means 4 causes the rising edge detection pulse b from the rising edge detecting means 2 to rise.
Through the flip-flop 6 as a set pulse d.
To set the output clock f, which is the output of the flip-flop 6, to the high level.

The delayed clock g output from the output clock delay means 7 is time t7 when time T1 elapses from time t5.
Since it is at a low level until t6, the falling detection pulse c detected by the falling detection means 3 at time t6 between times t5 and t7 is prohibited by the falling detection pulse prohibiting means 5. Therefore, the reset pulse e that resets the flip-flop 6 is not output, and the output clock f that is the output of the flip-flop 6 is held at the high level. Further, the rising edge detection pulse b detected by the rising edge detecting means 2 between the times t5 and t7 passes through the rising edge detecting pulse prohibiting means 4 and sets the flip-flop 6 again as a set pulse d.
The output clock f, which is the output of, remains unchanged at the high level.

As described above, the output clock f which is the output of the flip-flop 6 is maintained at the high level for at least the time T1 after changing to the high level.
In other words, if the high-level pulse width is T
An output clock f of 1 or more is obtained.

[0013]

Since the conventional clock shaping circuit is configured as described above, time t8 in FIG.
As shown in FIG. 5, when the change of the delay clock g from the output clock delay means 7 from the low level to the high level and the change of the input clock a from the low level to the high level occur at the same time, the set pulse is set to the flip-flop 6. Since d and the delay clock g are input at the same time, the output clock f, which is the output of the flip-flop 6, becomes indefinite.

The present invention has been made in order to solve the above problems, and the pulse widths of the high level and the low level are both constant or longer at any time when the input clock a changes. The purpose is to obtain a clock shaping circuit that outputs a stable clock.

[0015]

A clock shaping circuit according to the present invention delays an output clock by a time T1.
Output clock delaying means, second output clock delaying means for delaying the output clock by a time T2 which is appropriately shorter than time T1, and outputs of the first output clock delaying means and the second output clock delaying means. And a delay clock synthesizing means for performing the same.

[0016]

The second output clock delaying means and the delayed clock synthesizing means in the present invention inhibit the rising edge detecting pulse from the rising edge detecting means detected immediately before the clock input of the flip-flop changes from the low level to the high level. Therefore, the set input of the flip-flop and the clock input are prevented from changing at the same time, and the clock output which is the output of the flip-flop is prevented from becoming indefinite.

[0017]

1 is a block diagram of a clock shaping circuit showing an embodiment of the present invention, in which 1 is a clock input terminal for inputting a clock having a non-constant pulse width,
Reference numeral 2 is a rising edge detecting means for detecting a rising edge of the input clock a, 3 is a falling edge detecting means for detecting a falling edge of the input clock a, and 4 is an output b of the rising edge detecting means 2 by an output i of a delayed clock synthesizing means 9 described later. Rising detection pulse prohibiting means 5 for controlling the rising edge detection pulse inhibiting means 5 for controlling the output c of the falling edge detecting means 3 by the output g of the first output clock delay means 7 which will be described later, and 6 for the set input S and reset. It has an input R, a clock input T and a data input D, the output d of the rising detection pulse inhibiting means 4 is connected to the set input S, the output e of the falling detection pulse inhibiting means 5 is connected to the reset input R, and will be described later. A flip-flop in which the output g of the first output clock delay means 7 is connected to the clock input T and the data input D is fixed at a low level, and 7 is an output clock. First output clock delay means for delaying f by T1 time, 8 is second output clock delay means for delaying the output clock by T2 time which is appropriately shorter than T1 time, and 9 is output g of the first output clock delay means 7. And a delay clock synthesizing means 10 for taking the logical product of the output h of the second output clock delay means 8 and a clock output terminal for outputting the shaped clock f.

Next, regarding the operation of one embodiment of the present invention,
1 and FIG. 2, which is an example of the operation timing chart of FIG. 1, will be described. The input clock a having a non-constant pulse width input from the clock input terminal 1 is input to the rising edge detecting means 2, and the rising edge detecting means 2 receives the input clock a.
Rising edge is detected and a rising edge detection pulse b is output. Further, the input clock a is input to the falling edge detecting means 3, the falling edge detecting means 3 detects the falling edge of the input clock a, and outputs the falling edge detecting pulse c.

The rising detection pulse inhibiting means 4 allows the rising detection pulse b from the rising detection means 2 to pass when the combined delay clock i from the delay clock synthesizing means 9 which will be described later is at a low level, and the flip-flop as a set pulse d. 6 set input S is output. Further, the fall detection pulse inhibiting means 5 is a first clock delay means 7 which will be described later.
When the delayed clock g from 1 is at the high level, the fall detection pulse c from the fall detection means 3 is passed and is output to the reset input R of the flip-flop 6 as the reset pulse f.

The flip-flop 6 is set by the set pulse d from the rising detection pulse inhibiting means 4 and reset by the reset pulse e from the falling detection pulse inhibiting means 5, and at the same time, the first output clock delay means described later. 7 always takes in a low level signal input to the data input D at the rising edge of the first delay clock g, and outputs a shaped output clock f in which both high level and low level pulse widths are equal to or longer than a fixed time. To do.

The first output clock delay means 7 outputs the output clock f from the flip-flop 6 at a time T1 corresponding to the minimum required low level and high level pulse widths.
It is delayed and output as the first delay clock g. The second output clock delay means 8 delays the output clock f from the flip-flop 6 by a time T2 which is shorter than the time T1 by an appropriate time and outputs it as a second delay clock h.

The delay clock synthesizing means 9 takes the logical product of the first delay clock g from the first output clock delay means 7 and the second delay clock h from the second output delay means 8 to produce a synthetic delay. Output as clock i.

Next, as an initial state, the output clock f output from the flip-flop 6, the first delay clock g output from the first output clock delay means 7 and the output clock f from the second output clock delay means 8 are output. The specific operation will be described with the second delay clock h that is set to the high level.

The change from the high level to the low level of the input clock a at the time t1 is detected by the fall detection means 3, and the fall detection means 3 is detected by the fall detection pulse c.
Is output. Since the first delay clock g that is the output of the first output clock delay means 7 at time t1 is at the high level, the falling detection pulse inhibiting means 5 passes the falling detection pulse c from the falling detection means 3. Then, the flip-flop 6 is reset as the reset pulse e, and the output clock f which is the output of the flip-flop 6 is set to the low level.

Since the first delay clock g, which is the output of the first output clock delay means 7, is at the high level from the time t1 to the time t5 when the time T1 elapses, the output of the delay clock synthesis means 9 is synthesized. Since the delayed clock i also becomes high level until time t5, the rising detection pulse b detected by the rising detection means 2 at time t2 between times t1 and t5 is prohibited by the rising detection pulse prohibiting means 4. Therefore, the set pulse d that sets the flip-flop 6 is not output, and the output clock f that is the output of the flip-flop 6 is held at the low level. Further, the fall detection pulse c detected by the fall detection means 3 at the time t3 between the times t1 and t5 passes through the fall detection pulse prohibition means 5 and the reset pulse e.
As a result, the flip-flop 6 is reset again, but the output clock f, which is the output of the flip-flop 6, does not change at the low level.

As mentioned above, the flip-flop 6
The output clock f of is changed to the low level and is then kept at the low level for at least the time T1. In other words, the output clock f whose low-level pulse width is equal to or longer than the constant time T1 is obtained.

The change from the low level to the high level of the input clock a at the time t6 is detected by the rising edge detecting means 2 and the rising edge detecting means 2 is detected by the rising edge detecting pulse b.
Is output. Time t4 when time T2 has elapsed from time t1
At the time t5 when the second delayed clock h which is the output of the second output clock delay means 8 changes from the high level to the low level and the time T1 has elapsed from the time t1 at the output of the first output clock delay means 7 at Since the first delay clock g which is the high level changes to the low level, the synthetic delay clock i output from the delay clock synthesizing unit 9 changes from the high level to the low level at the time t5, and at the time t6. Since it is at the high level, the rising detection pulse inhibiting means 4 allows the rising detection pulse b from the rising detection means 2 to pass through, sets the flip-flop 6 as the set pulse d, and sets the flip-flop 6
The output clock f, which is the output of, is set to the high level.

Since the first delay clock g output from the first output clock delay means 7 is at the low level from the time t6 to the time t9 when the time T1 elapses, at the time t7 between the times t6 and t9. The fall detection pulse c detected by the fall detection means 3 is prohibited by the fall detection pulse prohibition means 5. Therefore, the reset pulse e that resets the flip-flop 6 is not output, and the output clock f that is the output of the flip-flop 6 is held at the high level.

The second delay clock h output from the second output clock delay means 8 is from time t6 to time T2.
Is low level until time t8 when
Since the combined delay clock i output from the delayed clock synthesizing means 9 is at a low level from time t6 to t8, the rising detection pulse b detected by the rising detection means 2 between times t6 and t8 is the rising detection pulse. Prohibition means 4
Although the flip-flop 6 is set again as a set pulse d after passing through, the output clock f which is the output of the flip-flop 6 remains at the high level and does not change.

As described above, the output clock f of the flip-flop 6 is maintained at the high level for at least the time T1 after changing to the high level. In other words, the output clock f having the high-level pulse width of the predetermined time T1 or more is obtained.

Furthermore, the clock shaping circuit according to the present invention changes the first delay clock g from the first output clock delay means 7 from the low level to the high level as shown at time t11 in FIG. Even when the change of a from the low level to the high level occurs at the same time, the second delay which is the output of the second output clock delay means 8 at the time t10 which is (T1-T2) time earlier than the time t11. Since the clock h changes from the low level to the high level, the combined delay clock i, which is the output of the delay clock combining means 9, changes from the low level to the high level at the time t10, so that the rising edge detection detected at the time t11 is detected. The pulse b is prohibited by the rising detection pulse prohibiting means 4. Therefore, the set pulse d input to the flip-flop 6 and the delay clock g are prevented from changing at the same time, and the output clock f can be prevented from becoming indefinite.

[0032]

As described above, according to the present invention, in addition to the first output clock delay means for delaying the output clock by the time T1, the output clock is delayed by the time T2 which is a proper time shorter than the time T1. A second output clock delaying means, a first output clock delaying means, and a delay clock synthesizing means for synthesizing the outputs of the second output clock delaying means. Since the set input and the clock input are prevented from changing at the same time, a stable clock whose high-level and low-level pulse widths are both equal to or longer than a fixed time is output regardless of the time when the input clock a changes. A clock shaping circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock shaping circuit according to the present invention.

FIG. 2 is an operation timing chart of a block configuration diagram showing an embodiment of a clock shaping circuit according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a conventional clock shaping circuit.

FIG. 4 is an operation timing chart of a block configuration diagram which is an example of a conventional clock shaping circuit.

[Explanation of symbols]

 2 rising edge detecting means 3 falling edge detecting means 4 rising edge detecting pulse inhibiting means 5 falling edge detecting pulse inhibiting means 6 flip-flop 7 first output clock delaying means 8 second output clock delaying means 9 delayed clock synthesizing means

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[Procedure amendment]

[Submission date] August 29, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

The rising edge detection pulse inhibiting means 4 allows the rising edge detection pulse b from the rising edge detecting means 2 to pass when the delay clock g from the output clock delaying means 7 which will be described later is at a low level, and the flip-flop 6 as a set pulse d. To the set input S of. Further, the fall detection pulse inhibiting means 5 is provided for the fall detection means 3 when the delay clock g from the output clock delay means 7 described later is at a high level.
It passed through a falling detection pulse c from the reset pulse
as an e output to the reset input R of the flip-flop 6.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006] The output clock delay unit 7 causes the time T1 delay corresponding to the pulse width of the minimum required low level and a high level output clock f from the flip-flop 6, and outputs it as a delayed clock g.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

As described above, the output of the flip-flop 6 is
Output clock f is the force at least during the time T1 After changes to the low level is kept at the low level.
In other words, when the low-level pulse width is T
An output clock f of 1 or more is obtained.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010] change from the input clock a low level at time t5 to a high level is detected in the rising edge detection unit 2, the rise detection hand stage 2 rising edge detection pulse b
Is output. Time t4 when time T1 has elapsed from time t1
At the time t5, the delay clock g output from the output clock delay means 7 changes from the high level to the low level.
Is low level, the rising edge detection pulse prohibiting means 4 causes the rising edge detection pulse b from the rising edge detecting means 2 to rise.
Through the flip-flop 6 as a set pulse d.
To set the output clock f, which is the output of the flip-flop 6, to the high level.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

[0013]

Since the conventional clock shaping circuit is configured as described above, time t8 in FIG.
As shown in, the change of the delay clock g from the output clock delay means 7 from the low level to the high level and the change of the input clock a from the low level to the high level are at the same time.
If this occurs, it sets the pulse d to the flip-flop 6
Since the delay clock g and the delay clock g are input at the same time, the output clock f, which is the output of the flip-flop 6, becomes indefinite.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

[0015]

A clock shaping circuit according to the present invention delays an output clock by a time T1.
Output In addition to the clock delay hand stage, the output clock time T of the
A second output clock delay means for delaying a time T2 that is appropriately shorter than 1, a first output clock delay means, and a delay clock synthesis means for synthesizing the outputs of the second output clock delay means. is there.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

The rising detection pulse prohibiting means 4 allows the rising detection pulse b from the rising detection means 2 to pass when the combined delay clock i from the delay clock combining means 9 to be described later is at a low level, and flip-flops as the set pulse d. 6 set input S is output. Further, the fall detection pulse prohibiting means 5 is a first clock delay means 7 which will be described later.
Delayed clock g from the passed through a falling detection pulse c from the trailing edge detection means 3 in the case of high level, and outputs to the reset input R of the flip-flop 6 as a reset <br/> pulse e.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

As mentioned above, the flip-flop 6
Is output output clock f for at least the time T1 After changes to the low level is kept at the low level. In other words, the output clock f whose low-level pulse width is equal to or longer than the constant time T1 is obtained.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Change

[Correction content]

The change from the low level to the high level of the input clock a at the time t6 is detected by the rising edge detecting means 2 and the rising edge detecting means 2 is detected by the rising edge detecting pulse b.
Is output. Time t4 when time T2 has elapsed from time t1
At the time t5 when the second delayed clock h which is the output of the second output clock delay means 8 changes from the high level to the low level and the time T1 has elapsed from the time t1 at the output of the first output clock delay means 7 at than the first delay clock g is changed from high level to low level at the output a is combined delay clock i of the delay clock synthesizing means 9 is changed from high level to low level at time t5, at time t6, because it is Loule bell rise detection pulse prohibition means 4 passes the rising edge detection pulse b from the rising edge detection unit 2, and sets the flip-flop 6 as a set pulse d flip-flop 6
The output clock f, which is the output of, is set to the high level.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

As described above, the output of the flip-flop 6 is
Output clock f is the force at least during the time T1 after changes to the high level is kept at the high level.
In other words, if the high-level pulse width is T
An output clock f of 1 or more is obtained.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

[0032]

As described above, according to the present invention, in addition to the first output clock delay means for delaying the output clock by the time T1, the output clock is delayed by the time T2 which is a proper time shorter than the time T1. A second output clock delaying means, a first output clock delaying means, and a delay clock synthesizing means for synthesizing the outputs of the second output clock delaying means. since the set input and the clock input is a configuration that can prevent the simultaneous change, the pulse width of the even high level and a low level when the input <br/> clock is changed to any time is stable in both a fixed time or more A clock shaping circuit that outputs a clock can be obtained.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Reference Signs] 1 clock input terminal 2 rising edge detecting means 3 falling edge detecting means 4 rising edge detecting pulse inhibiting means 5 falling edge detecting pulse inhibiting means 6 flip-flop 7 first output clock delaying means 8 second output clock delaying means 9 Delayed clock synthesizing means 10 Clock output terminal

[Procedure Amendment 13]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (1)

[Claims] 1. A clock shaping circuit for obtaining a shaped output clock having high-level and low-level pulse widths both being equal to or longer than a fixed time from an input clock having a non-constant pulse width. Falling detection means, first output clock delay means for delaying the output clock, and second output clock delay means for delaying the output clock by a delay time shorter than the delay time of the first output clock delay means. A delay clock combining means for combining the outputs of the first output clock delay means and the second output clock delay means,
Rise detection pulse inhibiting means for controlling the output of the rise detecting means by the output of the delay clock synthesizing means, and fall detection pulse inhibiting means for controlling the output of the fall detecting means by the output of the first output clock delay means. Means, and a set input, a reset input, a data input and a clock input, the output of the rising detection pulse inhibiting means is connected to the set input, the output of the falling detection pulse inhibiting means is connected to the reset input, A flip-flop whose output is connected to the clock input and whose low-level signal is input to the data input, wherein the flip-flop is reset by one of the reset input and the clock input, and Output of the flip-flop when set by the set input The clock shaping circuit, characterized in that the output clock.