JP2000078000A - Waveform shaping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a waveform shaping circuit which can shorten the lock time, can decrease the number of delay circuit elements and also can reduce the area of a delay circuit. SOLUTION: This waveform shaping circuit includes a feedback clock sampling circuit 14 which compares the phase of a reference clock CLKS with the phase of an output signal (feedback clock CLKR) and decides whether the leading edge (a) of the clock CLKS. should be set at the leading edge (b) or trailing edge (d) of the clock CLKR, a feedback clock inverting signal generation circuit 13 which outputs the clock CLKR after turning it forward or backward based on the deciding result of the circuit 14 and the delay control circuits 15 and 16 which give the delay value equivalent to the phase difference between the clock CLKS and the output of the circuit 13 to the clock CLKS to use these delay value as output signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform shaping circuit, and more particularly to a waveform shaping circuit for shaping and outputting a waveform of an input reference frequency signal.

[0002]

2. Description of the Related Art Some conventional phase matching circuits (waveform shaping circuits) adjust the waveform of a reference frequency signal and supply the adjusted signal to a required circuit such as a flip-flop. This phase matching circuit is a phase locked loop circuit (Phase Lock Loo
p: PLL circuit), and compares the phase of an input reference frequency signal with the phase of an output signal that is fed back to the input side (hereinafter also referred to as a feedback signal).

The above-mentioned conventional phase matching circuit is described in Japanese Patent Application Laid-Open No. 6-61993 as a clock extraction circuit. In general, the phase matching circuit has a phase comparator. The phase comparator compares the rising edge of the reference frequency signal with the rising edge of the feedback signal, and generates a small signal at the rising edge of the reference frequency signal. The timing of the reference frequency signal and the timing of the feedback signal are adjusted while delaying each time.

[0004]

In the above-described phase matching (waveform shaping) processing using the phase comparator, when there is a phase difference of, for example, about a half cycle between the reference frequency signal and the feedback signal, If at least one cycle of the delay adjustment width by the delay circuit element is not prepared, the phase matching cannot be properly performed. Therefore, an enormous number of delay circuit elements are required, and a long lock time for phase locking within a delay adjustment width of about one cycle is required.

[0005] In view of the above, it is an object of the present invention to provide a waveform shaping circuit capable of shortening the lock time, reducing the number of delay circuit elements, and reducing the area of the delay circuit.

[0006]

In order to achieve the above object, the present invention provides a waveform shaping circuit for shaping a waveform of an input reference frequency signal to obtain an output signal. Is compared with the phase of the output signal, a predetermined first edge of the reference frequency signal,
A determining circuit for determining which of the first and second edges of the output signal is to be matched, a forward / inverting circuit for inverting or inverting the output signal according to the determination result of the determining circuit, A delay control circuit that applies a delay amount corresponding to a phase difference between the reference frequency signal and an output of the forward / inverting circuit to the reference frequency signal to be the output signal.

In the waveform shaping circuit according to the present invention, the predetermined first edge of the reference frequency signal is phase-matched while selecting one of the first edge and the second edge of the output signal that has the fastest matching. Can be greatly reduced as compared with the related art, and accordingly, the number of delay circuit elements can be reduced and the area of the delay circuit can be reduced.

Here, the first edge is a rising edge, and the second edge is a falling edge, and the determination circuit determines that the rising edge of the reference frequency signal matches the rising edge of the output signal. Preferably, a first determination signal is output when the determination is made, and a second determination signal is output when it is determined that the rising edge of the reference frequency signal matches the falling edge of the output signal. In this case, the process of inverting or inverting the output signal by the inversion / inversion circuit is quickened.

The forward / inverting circuit inverts the output signal when the first determination signal is output and outputs the output signal to the delay control circuit, and inverts the output signal when the second determination signal is output. Then, it is preferable to output to the delay control circuit. This speeds up the process of inverting or inverting the output signal.

More preferably, when the first determination signal is output, the reference frequency signal from the delay control circuit is inverted to be the output signal, and when the second determination signal is output, the reference frequency signal from the delay control circuit is output. And a signal output circuit for inverting a signal to be the output signal. This allows
The reference frequency signal according to the output signal inverted by the normal rotation / inversion circuit can be returned to a normal state and output.

Preferably, the output signal has a first delay value and a second delay value respectively corresponding to a delay amount of the output signal from the forward / inverting circuit at the time of forward output and a delay amount at the time of inverted output. A delay adjusting circuit that, in response to an output state of the output signal from the forward / inverting circuit, applies the first or second delay value to the reference frequency signal prior to input to the delay control circuit; Prepare. In this case, a delay equal to the delay when the output signal passes through the forward / inverting circuit is given to the reference frequency signal before input to the delay control means, and the timing between the reference frequency signal and the output signal is adjusted in advance. can do.

[0012]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a phase matching circuit (waveform shaping circuit) according to an embodiment of the present invention. The phase matching circuit is mounted on a semiconductor integrated circuit, and includes a digital phase locked loop circuit (hereinafter, referred to as a PLL circuit) and a clock buffer 18.

The digital PLL circuit 11 includes a delay adjustment circuit 12, a feedback clock inversion signal generation circuit (forward / inversion circuit) 13, and a feedback clock sampling circuit (judgment circuit).
14, a phase comparison circuit 15, a delay circuit 16, a signal output circuit 17, an input terminal 20 to which a reference clock CLK _S (reference frequency signal) is input, and an output signal fed back to the input side (feedback signal: feedback clock CLK _R) ) Is input to the input terminal 21
have.

The feedback clock sampling circuit 14 performs sampling for comparing the phase of the reference clock CLK _{S with} the phase of the feedback clock CLK _R , thereby obtaining the reference clock CL.
K determines the rising or falling edge of the feedback clock CLK _R to be latched on the rising edge of _S. The feedback clock sampling circuit 14 further sends a determination signal (determination flag) Fj, which is a result of the sampling, to the feedback clock inversion signal generation circuit 13, the delay adjustment circuit 12, and the signal output circuit 17, respectively.

The feedback clock inversion signal generation circuit 13 includes a feedback clock CLK _R and a feedback clock sampling circuit 14.
And the determination signal Fj at
Is high level (HIGH), the feedback clock CLK _R is inverted and sent to the phase comparison circuit 15. On the other hand, the judgment signal F
When j is at a low level (LOW), the phase of the phase comparison circuit 15 is inverted by inverting the feedback clock CLK _R and using it as an inverted feedback clock CLK _T.
To send to.

The delay adjustment circuit 12 receives an input from an input terminal 20.
Input reference clock CLK_SAnd the return clock sampler
And the determination signal Fj from the
Reference clock CLK until input to phase comparison circuit 15_Sof
Adjust the delay amount in two stages. That is, the judgment signal Fj is LO
Feedback clock CLK for W_RIs inverted, so the delay
The adjustment circuit 12 is provided within the feedback clock inversion signal generation circuit 13.
When passing through an inversion logic circuit (not shown)
Long delay with reference clock CLK_SGive to. On the other hand, the judgment signal
When Fj is HIGH, the feedback clock CLK_RIs not inverted
Therefore, the delay adjustment circuit 12_RWhen flipping
Shorter delay than reference clock CLK_SGive to. This
And the reference clock CLK_SAnd the feedback clock CLK_ROr inversion
Return clock CLK_TAfter adjusting the timing with
Clock CLK_SAnd CLK_R(Or CLK _T) Is the phase comparison circuit 15
Is input to

The phase comparison circuit 15 has a phase of the reference clock CLK _S passed through the delay adjustment circuit 12 and a feedback clock CLK _R or an inverted feedback clock CLK _T corresponding to the sampling result.
, And compares the comparison result with the delay control signal Cs
To the delay circuit 16. The delay circuit 16 gives the reference clock CLK _S passed through the delay adjustment circuit 12 a delay amount in response to the delay control signal Cs from the phase comparison circuit 15 and sends the result to the signal output circuit 17. That is, the phase comparator 15 and the delay circuit 16
A delay control circuit is provided which provides a delay amount corresponding to the phase difference between CLK _S and the output of the feedback clock inversion signal generation circuit 13 to the reference clock CLK _S and uses it as an output signal.

The signal output circuit 17 outputs a delay control signal Cs
The reference clock CLK _S to which the delay amount corresponding to the reference clock CLK _S is given and the determination signal Fj from the feedback clock sampling circuit 14 are input. When the determination signal Fj is HIGH, the feedback clock CLK _R is not inverted by the feedback clock inversion signal generation circuit 13, so that the signal output circuit 17 outputs the reference clock CLK _S from the delay circuit 16 as it is. On the other hand, the signal output circuit 17, when the determination signal Fj is LOW, the reference clock phase matching with respect to the inverted feedback clock CLK _T
CLK _S is inverted and output with its phase returned. The output of the signal output circuit 17 is input to a flip-flop (FF) group 19 via a clock buffer 18, and one of the clock lines is fed back to the feedback clock sampling circuit 14 as a feedback clock CLK _R.

Next, the operation of the phase matching circuit in this embodiment will be described. First, prior to the process of adjusting the phase of the reference clock CLK _S from the outside, the feedback clock sampling circuit 14 determines the phase of the feedback clock CLK _R to which the output to the FF group 19 is fed back and the phase of the reference clock CLK _S. Are compared with each other.

FIG. 2 shows a feedback clock sampling circuit 1.
4A is a timing chart showing a mutual relationship between signal waveforms for explaining the sampling process performed in FIG.
The feedback clock CLK _R, (B) is fed back at a different time than the (A) the clock CLK _R, (C) is the reference clock CL
K _S and (D) indicate the inverted feedback clock CLK _T , respectively. In the figure, the vertical axis indicates the signal level, and the horizontal axis indicates time.

For example, as shown in FIG. 2A, the rising edge b of the feedback clock CLK _R is the reference clock of FIG.
When the leading edge a of CLK _S is advanced, the feedback clock sampling circuit 14 outputs HIGH as the determination signal Fj as a determination result. On the other hand, as shown in FIG. 2B, the falling edge d of the feedback clock CLK _R is
Of if advances from the rising edge a of the reference clock CLK _S are, LOW is output to the determination signal Fj.

That is, the feedback clock sampling circuit 1
4 outputs HIGH to the determination signal Hj when it is determined that the rising edge b of the feedback clock CLK _R is used for the phase comparison, and when it is determined that the falling edge d of the feedback clock CLK _R is used for the phase comparison. Outputs LOW as the judgment signal Hj. Therefore, the feedback clock inversion signal generation circuit 13 outputs the determination signal Hj from the feedback clock sampling circuit 14
If HIGH, the feedback clock CLK _R is sent to the phase comparison circuit 15 without inversion, and if the determination signal Hj is LOW, the feedback clock CLK _R is inverted and the phase comparison circuit CLK _T is inverted. Send to 15.

[0023] The delay adjustment circuit 12 in accordance with the determination signal Fj from the feedback clock sampling circuit 14, provides a delay to the reference clock CLK _S input. At this time, if the determination signal Fj is LOW, a relatively long delay is given to the reference clock CLK _S , and if the determination signal Fj is HIGH, a delay shorter than the inversion of the feedback clock CLK _R is provided.
Give to CLK _S. As a result, the reference clock CLK _S and the feedback clock CLK _R or the inverted feedback clock CLK _T are input to the phase comparison circuit 15 with their timing adjusted.

The phase comparison circuit 15 compares the reference clock CLK _S input from the delay adjustment circuit 12 and the feedback clock CLK _R (or the inverted feedback clock CLK _T ) input from the feedback clock inversion signal generation circuit 13, respectively. The delay control signal Cs is output to the delay circuit 16. Therefore, the delay circuit 16 responds to the delay control signal Cs in response to the reference clock CL.
K _S is gradually delayed, the reference clock CLK _S is adjusted to the phase of the feedback clock CLK _R , and both clocks CLK _S and CL
While aligning the timing of K _R, shaping the output waveform.

The output of the signal output circuit 17 whose waveform has been shaped is input to the FF group 19 via the clock buffer 18 and is also fed back to the feedback clock sampling circuit 14 as the feedback clock CLK _R.

[0026] As described above, according to this embodiment, when performing the phase matching inclusive, the rising edge a of the reference clock CLK _S for either of the feedback clock CLK rising edge of _R b and falling edge d The phase comparison is performed while determining whether the comparison is appropriate. In this embodiment, since the falling edge d can be used for comparison in addition to the rising edge b of the feedback clock CLK _R , which has been conventionally used, the delay circuit element to be prepared in the delay circuit 16 , The adjustment width by about half of the conventional value is sufficient. Therefore, the phase matching time for at most a half cycle of the reference clock CLK _R can be reduced as compared with the related art. The delay circuit element for adjusting the delay is based on a reference clock.
Since the number of half cycles of CLK _S is enough, it is about 50 times
% Of the number of delay circuit elements can be reduced. By these,
The lock time can be reduced and the area of the delay circuit can be reduced.

Although the present invention has been described based on the preferred embodiment, the waveform shaping circuit such as the phase matching circuit of the present invention is not limited to the configuration of the above embodiment. Waveform shaping circuits obtained by making various modifications and changes from the configuration of the above embodiment are also included in the scope of the present invention.

[0028]

As described above, according to the waveform shaping circuit of the present invention, the lock time can be reduced, the number of delay circuit elements can be reduced, and the area of the delay circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a phase matching circuit according to an embodiment of the present invention.

FIGS. 2A and 2B are timing charts illustrating a relationship between signal waveforms for explaining a sampling process according to the embodiment; FIG. 2A is a feedback clock, and FIG. 2B is a feedback clock at a different timing from FIG. , (C) shows a reference clock, and (D) shows an inverted feedback clock.

[Explanation of symbols]

11: Digital PLL circuit 12: Delay adjustment circuit 13: Feedback clock inversion signal generation circuit 14: Feedback clock sampling circuit 15: Phase comparison circuit 16: Delay circuit 17: Signal output circuit 18: Clock buffer 19: Flip-flop group 20, 21 : Input terminals a, b: rising edge d: falling edge Cs: delay control signal CLK _R : feedback clock CLK _S : reference clock CLK _T : inverted feedback clock Fj: judgment signal

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[Procedure amendment]

[Submission Date] July 16, 1999 (1999.7.1)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

That is, the feedback clock sampling circuit 1
4 outputs HIGH to the determination signal Fj when it is determined that the rising edge b of the feedback clock CLK _R is used for phase comparison, and when it is determined that the falling edge d of the feedback clock CLK _R is used for phase comparison. Outputs LOW as the determination signal Fj. Therefore, the feedback clock inversion signal generation circuit 13 outputs the determination signal Fj from the feedback clock sampling circuit 14
If HIGH, the feedback clock CLK _R is sent to the phase comparison circuit 15 without inversion, and if the determination signal Fj is LOW, the phase comparison circuit is used as an inverted feedback clock CLK _T obtained by inverting the feedback clock CLK _R. Send to 15.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA03 CC21 CC59 DD24 GG10 HH02 JJ07 KK03 KK38 KK39 LL05 5K047 AA02 GG02 GG09 GG24 MM36 MM43 MM63

Claims (5)

[Claims] 1. A waveform shaping circuit for shaping a waveform of an input reference frequency signal as an output signal, wherein a phase of the reference frequency signal is compared with a phase of the output signal, and a predetermined phase of the reference frequency signal is A determination circuit for determining whether to align the first edge with the first or second edge of the output signal; and a normal rotation for inverting or inverting the output signal according to a determination result of the determination circuit. / Inverting circuit; and a delay control circuit that gives the reference frequency signal a delay amount corresponding to a phase difference between the reference frequency signal and the output of the forward / inverting circuit, and uses the delay amount as the output signal. Waveform shaping circuit. 2. The method according to claim 1, wherein the first edge includes a rising edge, and the second edge includes a falling edge, and the determination circuit determines that the rising edge of the reference frequency signal matches the rising edge of the output signal. 2. The waveform according to claim 1, wherein a first determination signal is output, and a second determination signal is output when it is determined that the rising edge of the reference frequency signal matches the falling edge of the output signal. Shaping circuit. 3. The forward / inverting circuit inverts the output signal and outputs the output signal to the delay control circuit when the first determination signal is output, and inverts the output signal when the second determination signal is output. 3. The waveform shaping circuit according to claim 2, wherein the signal is output to the delay control circuit. 4. When the first determination signal is output, the reference frequency signal from the delay control circuit is inverted and output as the output signal. When the second determination signal is output, the reference frequency signal from the delay control circuit is output. 4. The waveform shaping circuit according to claim 2, further comprising a signal output circuit for inverting the output signal. 5. The system according to claim 5, further comprising a first delay value and a second delay value respectively corresponding to a delay at the time of forward output and a delay at the time of inversion output of the output signal from the forward / inverting circuit. A delay adjusting circuit that, in response to an output state of the output signal from the inverting / inverting circuit, applies the first or second delay value to the reference frequency signal prior to input to the delay control circuit. 5. The method according to claim 1, wherein:
The waveform shaping circuit according to any one of the above.