JPH06209053A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH06209053A JPH06209053A JP5002216A JP221693A JPH06209053A JP H06209053 A JPH06209053 A JP H06209053A JP 5002216 A JP5002216 A JP 5002216A JP 221693 A JP221693 A JP 221693A JP H06209053 A JPH06209053 A JP H06209053A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating
- insulating substrate
- tape
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置とその製造方
法に関し、特に従来の薄膜半導体装置にかわる有機系絶
縁樹脂と金属導体の配線による多層配線構造を持った薄
膜半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a thin film semiconductor device having a multi-layer wiring structure formed by wiring of an organic insulating resin and a metal conductor, which replaces the conventional thin film semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置を小型化することを目的とし
て、図３に示すようにセラミック等の絶縁基板上にスパ
ッタや蒸着によりメタライズを施し、露光・エッチング
等のフォトリソ工程で多層配線を形成していき、半導体
チップを搭載する薄膜半導体装置がある。2. Description of the Related Art For the purpose of miniaturizing a semiconductor device, metallization is performed on an insulating substrate such as ceramics by sputtering or vapor deposition as shown in FIG. 3, and multilayer wiring is formed by a photolithography process such as exposure and etching. Now, there is a thin film semiconductor device on which a semiconductor chip is mounted.
【０００３】図３は薄膜半導体装置の例を示す図であ
り、図中２は配線、３は絶縁基板、６はビアホール、８
は導体層、９は絶縁層、１３は半導体チップである。従
来の薄膜半導体装置は、図３に示す各工程により絶縁基
板３上に導体層８と絶縁層９を積層していくことにより
製造される。 〔第１工程〕図３（１）に示す様に、セラミック等の絶
縁基板３上にスパッタ又は蒸着により１層目の導体層８
を形成する。この導体層８にほＴｉ、Ｍｏ、Ｃｒ、Ｎ
ｉ、Ｃｕ等が用いられる。 〔第２工程〕図３（２）に示す様に、１層目の導体層８
にレジストを塗布し、露光によりレジストパターンを作
り、エッチングにより配線２を形成する。 〔第３工程〕図３（３）に示す様に、配線２上にポリイ
ミド等の絶縁性樹脂をスピンナにより塗布し、加熱する
ことにより硬化させ絶縁層９を形成する。 〔第４工程〕図３（４）に示す様に、絶縁層９上にレジ
ストを塗布し、露光によりレジストパターンを作り、エ
ッチングによりビアホール６を形成する。このビアホー
ル６により各多層配線層に形成される配線２間を接続す
る。 〔第５工程〕図３（５）に示す様に、絶縁層９上にスパ
ッタ又は蒸着により２層目の導体層８を形成する。この
２層目の導体層８の形成方法は１層目の導体層８の形成
方法と同一である。 〔第６工程〕図３（６）に示す様に、第１工程から第５
工程を繰り返すことにより絶縁基板３上に配線２と絶縁
層９を積層し、半導体チップ１３を搭載する。FIG. 3 is a diagram showing an example of a thin film semiconductor device, in which 2 is wiring, 3 is an insulating substrate, 6 is a via hole, and 8 is a via hole.
Is a conductor layer, 9 is an insulating layer, and 13 is a semiconductor chip. The conventional thin film semiconductor device is manufactured by stacking the conductor layer 8 and the insulating layer 9 on the insulating substrate 3 by the steps shown in FIG. [First Step] As shown in FIG. 3A, the first conductor layer 8 is formed on the insulating substrate 3 made of ceramic or the like by sputtering or vapor deposition.
To form. This conductor layer 8 contains Ti, Mo, Cr, N
i, Cu or the like is used. [Second Step] As shown in FIG. 3B, the first conductor layer 8
A resist is applied to the substrate, a resist pattern is formed by exposure, and the wiring 2 is formed by etching. [Third Step] As shown in FIG. 3C, an insulating resin such as polyimide is applied onto the wiring 2 by a spinner and is cured by heating to form an insulating layer 9. [Fourth Step] As shown in FIG. 3D, a resist is applied on the insulating layer 9, a resist pattern is formed by exposure, and a via hole 6 is formed by etching. The via holes 6 connect the wirings 2 formed in each multilayer wiring layer. [Fifth Step] As shown in FIG. 3 (5), a second conductor layer 8 is formed on the insulating layer 9 by sputtering or vapor deposition. The method of forming the second conductor layer 8 is the same as the method of forming the first conductor layer 8. [Sixth step] As shown in FIG.
By repeating the process, the wiring 2 and the insulating layer 9 are laminated on the insulating substrate 3, and the semiconductor chip 13 is mounted.
【０００４】この様な薄膜半導体装置は、上述の様にフ
ォトリソ工程等によって製造されるため、工数が多く製
造に長時間を要し、必然的に製造コストがかさんで高価
な製品となってしまう。また、スピンナにより配線２上
にポリイミドを塗布して絶縁層９を形成しているので、
絶縁層９にピンホールや厚さの不十分な部分が発生し、
各配線２の絶縁が不完全になったり、フォトリソ工程時
のエッチングの過不足により配線２のショートや断線が
発生し歩留りが低いという問題がある。Since such a thin film semiconductor device is manufactured by the photolithography process or the like as described above, it requires a lot of man-hours and requires a long time for manufacturing, and the manufacturing cost is inevitably high and an expensive product. I will end up. Further, since the wiring layer 2 is coated with polyimide by the spinner to form the insulating layer 9,
Insulating layer 9 has pinholes and insufficient thickness,
There is a problem that the insulation of each wiring 2 is incomplete, or the wiring 2 is short-circuited or broken due to excess or shortage of etching during the photolithography process, resulting in a low yield.
【０００５】この問題点を解決する方法として特開平４
─１６２６９５号公報に開示された多層配線基板があ
る。この多層配線基板は、シート状感光性ポリイミド前
駆体に配線パターンを形成し、このシート状感光性ポリ
イミド前駆体を複数積層して圧着することにより多層配
線基板を得ている。図４は同公報に開示された多層配線
基板を示している。図中２１はシート状感光性ポリイミ
ド前駆体、２２は金属箔、２３はスルーホール孔、２４
はスルーホールコンタクト、２５は配線パターン、２６
はセラミック基板、２８は絶縁層であり、この方法によ
れば、次の様な工程により多層配線基板を形成する。 〔第１工程〕図４（１）に示す様に、金属箔２２上にシ
ート状感光性ポリイミド前駆体２１を加熱圧着する。 〔第２工程〕図４（２）に示す様に、フォトリソ工程に
よりシート状感光性ポリイミド前駆体２１にスルーホー
ル孔２３を開口する。 〔第３工程〕図４（３）に示す様に、金属箔２２を電極
としてメッキを施し、スルーホール孔２３にスルーホー
ルコンタクト２４を形成する。 〔第４工程〕図４（４）に示す様に、フォトリソ工程に
より、金属箔２２を所定の配線パターン２５に形成す
る。 〔第５工程〕図４（５）に示す様に、配線パターン２５
が形成されたシート状感光性ポリイミド前駆体２１を複
数枚積層して、圧着固定する。 〔第６工程〕図４（６）に示す様に、積層したシート状
感光性ポリイミド前駆体２１を加熱してイミド化処理を
行い、絶縁性有機物であるポリイミド樹脂に変化させ絶
縁層８とする。As a method for solving this problem, Japanese Unexamined Patent Publication No. Hei 4
There is a multilayer wiring board disclosed in Japanese Patent Laid-Open No. 162695/162. In this multilayer wiring board, a wiring pattern is formed on a sheet-shaped photosensitive polyimide precursor, and a plurality of sheet-shaped photosensitive polyimide precursors are laminated and pressure-bonded to obtain a multilayer wiring board. FIG. 4 shows the multilayer wiring board disclosed in the publication. In the figure, 21 is a sheet-shaped photosensitive polyimide precursor, 22 is a metal foil, 23 is a through hole hole, 24
Is a through hole contact, 25 is a wiring pattern, 26
Is a ceramic substrate and 28 is an insulating layer. According to this method, a multilayer wiring substrate is formed by the following steps. [First Step] As shown in FIG. 4A, the sheet-shaped photosensitive polyimide precursor 21 is heat-pressed onto the metal foil 22. [Second Step] As shown in FIG. 4B, through holes 23 are formed in the sheet-shaped photosensitive polyimide precursor 21 by a photolithography process. [Third Step] As shown in FIG. 4C, plating is performed using the metal foil 22 as an electrode to form the through hole contact 24 in the through hole hole 23. [Fourth Process] As shown in FIG. 4D, the metal foil 22 is formed into a predetermined wiring pattern 25 by a photolithography process. [Fifth Step] As shown in FIG.
A plurality of sheet-shaped photosensitive polyimide precursors 21 on which are formed are laminated and fixed by pressure. [Sixth Step] As shown in FIG. 4 (6), the laminated sheet-shaped photosensitive polyimide precursor 21 is heated to perform imidization treatment, and converted into a polyimide resin that is an insulating organic material to form the insulating layer 8. .
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記の
多層配線基板の製造方法には様々な問題点がある。ポリ
イミド前駆体は加熱することにより硬化（イミド化）し
てポリイミド樹脂になるが、イミド化が進行していない
未硬化のシート状感光性ポリイミド前駆体は容易に酸や
アルカリに侵される。However, the above-mentioned method for manufacturing a multilayer wiring board has various problems. The polyimide precursor is cured (imidized) by heating to become a polyimide resin, but the uncured sheet-shaped photosensitive polyimide precursor in which imidization has not progressed is easily attacked by acid or alkali.
【０００７】そのため、スルーホール孔にメッキによる
スルーホールコンタクトを形成する時や、エッチングに
より配線パターンを形成するときに所定の形状を保つこ
とが困難であり、微細な配線パターンを形成することが
できない。また、シート状感光性ポリイミド前駆体を積
層し圧着固定して、イミド化処理の為に加熱している
が、イミド化によりシート状感光性ポリイミド前駆体が
ポリイミド樹脂になる際に、シート状感光性ポリイミド
前駆体中の感光基等がガスとなって発生する。Therefore, it is difficult to maintain a predetermined shape when forming a through-hole contact by plating in the through-hole or when forming a wiring pattern by etching, and it is impossible to form a fine wiring pattern. . In addition, the sheet-shaped photosensitive polyimide precursor is laminated, press-bonded and fixed, and heated for imidization treatment, but when the sheet-shaped photosensitive polyimide precursor becomes a polyimide resin by imidization, the sheet-shaped photosensitive polyimide precursor The photosensitive groups and the like in the photosensitive polyimide precursor are generated as gas.
【０００８】このガスは、配線パターンに使用されてい
る銅、アルミ、ニッケル及び銀等の金属を酸化させるほ
か、配線パターンと絶縁層となるポリイミド樹脂の剥離
を生じさせてしまう。さらに、シート状感光性ポリイミ
ド前駆体のイミド化に伴い収縮が起こるので、このシー
ト状感光性ポリイミド前駆体表面に形成された配線パタ
ーンの精度が一層悪化してしまう。This gas not only oxidizes metals such as copper, aluminum, nickel and silver used for the wiring pattern, but also causes peeling of the wiring pattern and the polyimide resin which serves as an insulating layer. Furthermore, since shrinkage occurs along with imidization of the sheet-shaped photosensitive polyimide precursor, the accuracy of the wiring pattern formed on the surface of the sheet-shaped photosensitive polyimide precursor is further deteriorated.
【０００９】これらの問題点がある為、シート状感光性
ポリイミド前駆体表面に配線パターンを形成し、積層圧
着した後加熱によるイミド化を行い多層配線基板を得る
ことは極めて難しく、現実的ではない。本発明ではこの
様な問題点を解決する為に、積層された各絶縁テープ間
の剥離や、絶縁テープとその表面に形成された配線の剥
離を防ぎ、配線の酸化を防いだ構造をもつ半導体装置と
その製造方法を得ることを目的とする。Because of these problems, it is extremely difficult and unrealistic to obtain a multilayer wiring board by forming a wiring pattern on the surface of a sheet-shaped photosensitive polyimide precursor, laminating and press-bonding it, and then imidizing it by heating. . In the present invention, in order to solve such a problem, a semiconductor having a structure in which peeling between the laminated insulating tapes and peeling of the insulating tape and the wiring formed on the surface thereof is prevented and oxidation of the wiring is prevented. An object is to obtain a device and a manufacturing method thereof.
【００１０】[0010]
【課題を解決するための手段】本発明の半導体装置にお
いては、図１に示す様に、接着用樹脂４加熱時に発生す
るガスによる酸化を防止する為の保護膜１０で被覆され
た第１の配線２が表面に形成された絶縁基板３と、前記
保護膜１０で被覆された第２の配線２が表面に形成さ
れ、前記絶縁基板３上に前記接着用樹脂４により複数の
層が熱圧着され積層された絶縁テープ１とを有し、前記
絶縁テープ１に設けられたビアホール６により、前記第
１の配線２と第２の配線２が接続されており、複数積層
された前記絶縁テープ１上に半導体チップ１３が搭載さ
れ前記第２の配線２と電気的に接続されていることを特
徴とする。In the semiconductor device according to the present invention, as shown in FIG. 1, a first protective film 10 for preventing oxidation by a gas generated when the adhesive resin 4 is heated is formed. An insulating substrate 3 having a wiring 2 formed on the surface and a second wiring 2 covered with the protective film 10 are formed on the surface, and a plurality of layers are thermocompression-bonded on the insulating substrate 3 by the adhesive resin 4. And laminated insulating tape 1, and the first wiring 2 and the second wiring 2 are connected by a via hole 6 provided in the insulating tape 1, and the plurality of laminated insulating tapes 1 are connected. A semiconductor chip 13 is mounted on the top and is electrically connected to the second wiring 2.
【００１１】本発明の半導体装置の製造方法において
は、絶縁基板３表面に選択的に第１の配線２を形成する
工程と、前記絶縁基板３表面の第１の配線２を保護膜１
０により被覆する工程と、前記絶縁基板３表面に接着用
樹脂４を塗布し加熱して、前記接着用樹脂４を半硬化さ
せる工程と、表面に保護膜１０で被覆された第２の配線
２を有する絶縁テープ１を、前記接着用樹脂４を介して
前記絶縁基板３上に加熱し加圧して、半硬化させた前記
接着用樹脂４を全硬化させて前記絶縁基板３上に圧着す
る工程と、前記絶縁テープ１に前記第１の配線２と第２
の配線２を結ぶビアホール６を形成する工程と、前記ビ
アホール６を導電用メッキ７により充填する工程と、複
数積層された前記絶縁テープ１上に半導体チップ１３を
搭載し、前記第２の配線２と電気的に接続する工程を有
することを特徴とする。In the method of manufacturing a semiconductor device of the present invention, a step of selectively forming the first wiring 2 on the surface of the insulating substrate 3 and a step of protecting the first wiring 2 on the surface of the insulating substrate 3 with the protective film 1
0, a step of applying the adhesive resin 4 on the surface of the insulating substrate 3 and heating it to semi-cure the adhesive resin 4, and a second wiring 2 whose surface is covered with the protective film 10. A step of heating and pressurizing the insulating tape 1 having the above onto the insulating substrate 3 through the adhesive resin 4 to fully cure the semi-cured adhesive resin 4 and press-bond it onto the insulating substrate 3. And the first wiring 2 and the second wiring on the insulating tape 1.
Forming a via hole 6 connecting the wiring 2 of the above, a step of filling the via hole 6 with a conductive plating 7, a semiconductor chip 13 is mounted on the insulating tape 1 having a plurality of layers, and the second wiring 2 And a step of electrically connecting with.
【００１２】[0012]
【作用】本発明の半導体装置は、表面に保護膜で被覆さ
れた配線が形成されている絶縁基板上に、表面に保護膜
で被覆された配線が形成されている絶縁テープが接着用
樹脂により積層されており、各層の配線をビアホールで
接続した構造をしている。In the semiconductor device of the present invention, the insulating tape having the wiring covered with the protective film on the surface is formed by the adhesive resin on the insulating substrate having the wiring covered with the protective film on the surface. They are laminated and have a structure in which the wiring of each layer is connected by a via hole.
【００１３】そのため、もし熱圧着時に絶縁テープや接
着用樹脂からガスが発生したとしても、絶縁基板と絶縁
テープ上の配線にはＣｏメッキによる保護膜が形成され
ているので、配線の酸化を招くことがなく、半導体装置
の歩留りが向上する。本発明に用いる絶縁テープはイミ
ド化が済んだポリイミド樹脂よりなるので、この絶縁テ
ープを積層し接着用樹脂により熱圧着するときに、絶縁
テープからガスが発生して配線と絶縁テープ間の剥離を
生じることがない。Therefore, even if gas is generated from the insulating tape or the adhesive resin during thermocompression bonding, the wiring on the insulating substrate and the insulating tape has a protective film formed by Co plating, which causes oxidation of the wiring. And the yield of semiconductor devices is improved. Since the insulating tape used in the present invention is made of a polyimide resin that has been imidized, when the insulating tape is laminated and thermocompression-bonded with an adhesive resin, gas is generated from the insulating tape to separate the wiring from the insulating tape. It never happens.
【００１４】イミド化が済んだポリイミド樹脂同士やポ
リイミド樹脂とセラッミック等の絶縁基板は、加熱圧着
により接着させることができないので、本発明では接着
用樹脂によりポリイミド樹脂よりなる絶縁テープを積層
し加熱圧着している。この接着用樹脂はポリイミドより
なっているが、圧着面に塗布された後に３００℃以下で
イミド化し、各絶縁テープを圧着できる程度に硬化（半
硬化）させているので、ガスは圧着面に塗布された時の
イミド化により放出されてしう。Since the imidized polyimide resins or the polyimide resin and the insulating substrate such as ceramic cannot be adhered by thermocompression bonding, in the present invention, an insulating tape made of polyimide resin is laminated by an adhesive resin and thermocompression bonding is performed. is doing. Although this adhesive resin is made of polyimide, it is imidized at 300 ° C or lower after being applied to the pressure-bonded surface and cured (semi-cured) to the extent that each insulating tape can be pressure-bonded, so gas is applied to the pressure-bonded surface. It will be released by imidization when it is treated.
【００１５】そのため、絶縁テープを熱圧着する際の、
半硬化させた接着用樹脂を完全に硬化させる全硬化時に
ガスが発生し、各絶縁テープ間の剥離を生じることがな
い。Therefore, when the insulating tape is thermocompression bonded,
Gas is generated during the complete curing of the semi-cured adhesive resin, and peeling between the insulating tapes does not occur.
【００１６】[0016]
【実施例】図１は本発明の実施例図であり、本発明によ
る半導体装置とその製造方法を示している。図１中で、
１は絶縁テープ、２は配線、３は絶縁基板、４は接着用
樹脂、６はビアホール、７は導電用メッキ、１２は金属
ビア、１３は半導体チップ、１４はピンである。1 is a diagram showing an embodiment of the present invention, showing a semiconductor device according to the present invention and a manufacturing method thereof. In Figure 1,
1 is an insulating tape, 2 is a wiring, 3 is an insulating substrate, 4 is an adhesive resin, 6 is a via hole, 7 is conductive plating, 12 is a metal via, 13 is a semiconductor chip, and 14 is a pin.
【００１７】本発明では、次の様な工程により有機絶縁
材料と金属薄膜からなる多層構造の半導体装置を形成す
る。 〔第１工程〕図１（１）に示す様に、絶縁基板３上に金
属の薄膜からなる配線２を形成する。絶縁基板３はセラ
ミックよりなっており、外部接続用のピン１４との導通
をとる為の金属ビア１２が形成されている。In the present invention, a semiconductor device having a multilayer structure composed of an organic insulating material and a metal thin film is formed by the following steps. [First Step] As shown in FIG. 1A, the wiring 2 made of a metal thin film is formed on the insulating substrate 3. The insulating substrate 3 is made of ceramic and has metal vias 12 for establishing electrical connection with the pins 14 for external connection.
【００１８】この絶縁基板３上にスパッタ又は蒸着によ
りＣｕやＣｒ等の金属層を形成し、レジストパターン形
成、エッチングにより配線２を形成する。配線２はＣ
ｒ、Ｃｏ等の無電解メッキによる保護膜１０で表面を被
覆される。保護膜１０は、無電解メッキ液に配線２が形
成された絶縁基板３を浸漬することにより形成される
が、無電解メッキは金属の還元反応により形成されるも
のなので、配線２の表面にのみ無電解メッキによる保護
膜１０を形成することができる。A metal layer such as Cu or Cr is formed on the insulating substrate 3 by sputtering or vapor deposition, and the wiring 2 is formed by forming a resist pattern and etching. Wiring 2 is C
The surface is covered with a protective film 10 of electroless plating such as r or Co. The protective film 10 is formed by immersing the insulating substrate 3 on which the wiring 2 is formed in an electroless plating solution. Since the electroless plating is formed by a reduction reaction of metal, only the surface of the wiring 2 is formed. The protective film 10 can be formed by electroless plating.
【００１９】形成された配線２は、金属ビア１２の上に
形成されており、金属ビア１２の下に取り付けられるピ
ン１４により外部との接続ができる様になっている。 〔第２工程〕図１（２）に示す様に、配線２を形成した
絶縁基板３上にスピンナによりポリイミドからなる絶縁
性の接着用樹脂４を塗布し、３００℃以下の温度でイミ
ド化する。接着用樹脂４はこのイミド化により絶縁テー
プ１を圧着できる程度に半硬化すると共に脱ガスされ
る。 〔第３工程〕図１（３）に示す様に、表面に配線２を形
成しておいた絶縁テープ１を、半硬化させておいた接着
用樹脂４の全硬化により絶縁基板３に熱圧着する。この
熱圧着時には、接着用樹脂４が塗布された絶縁基板３及
び絶縁テープ１を３５０℃〜４５０℃の範囲で加熱す
る。The formed wiring 2 is formed on the metal via 12 and can be connected to the outside by the pin 14 attached under the metal via 12. [Second Step] As shown in FIG. 1 (2), an insulating adhesive resin 4 made of polyimide is applied by a spinner on the insulating substrate 3 on which the wiring 2 is formed, and imidized at a temperature of 300 ° C. or lower. . By this imidization, the adhesive resin 4 is semi-cured to the extent that the insulating tape 1 can be pressure-bonded and is degassed. [Third step] As shown in FIG. 1C, the insulating tape 1 having the wiring 2 formed on the surface thereof is thermocompression-bonded to the insulating substrate 3 by fully curing the semi-cured adhesive resin 4. To do. At the time of this thermocompression bonding, the insulating substrate 3 and the insulating tape 1 coated with the adhesive resin 4 are heated in the range of 350 ° C to 450 ° C.
【００２０】絶縁テープ１はイミド化の済んだポリイミ
ド樹脂からなり、表面に金属の薄膜からなる配線２が形
成されていて、この配線２は絶縁基板３上の配線２と同
様にＣｒ、Ｃｏ等の無電解メッキによる保護膜１０で被
覆されている。本発明では予め多層配線構造となる各層
の配線２を別々の絶縁テープ１上に形成しておく。 〔第４工程〕図１（４）に示す様に、絶縁基板３に熱圧
着した絶縁テープ１上にレジストを塗布し、露光により
レジストパターンを作り、エッチングによりビアホール
６を形成する。 〔第５工程〕図１（５）に示す様に、ビアホール６にメ
ッキにより導電用メッキ７を充填する。このビアホール
６と導電用メッキ７により積層される各絶縁テープ１上
の配線２と、絶縁基板３上の配線２を接続する。 〔第６工程〕図１（６）に示す様に、絶縁基板３上に所
定の層数だけ絶縁テープ１を積層していき、半導体チッ
プ１３を搭載する。金属ビア１２には、ピン１４を取り
付ける。The insulating tape 1 is made of imidized polyimide resin, and the wiring 2 made of a metal thin film is formed on the surface thereof. Like the wiring 2 on the insulating substrate 3, the wiring 2 is made of Cr, Co, or the like. It is covered with a protective film 10 formed by electroless plating. In the present invention, the wirings 2 of the respective layers having the multilayer wiring structure are previously formed on separate insulating tapes 1. [Fourth Step] As shown in FIG. 1D, a resist is applied onto the insulating tape 1 thermocompression bonded to the insulating substrate 3, a resist pattern is formed by exposure, and a via hole 6 is formed by etching. [Fifth Step] As shown in FIG. 1 (5), the via hole 6 is filled with a conductive plating 7 by plating. The wiring 2 on each insulating tape 1 laminated by the via hole 6 and the conductive plating 7 is connected to the wiring 2 on the insulating substrate 3. [Sixth Step] As shown in FIG. 1 (6), the insulating tape 1 is laminated on the insulating substrate 3 by a predetermined number of layers to mount the semiconductor chip 13. Pins 14 are attached to the metal vias 12.
【００２１】上述したように、本発明の半導体装置とそ
の製造方法に用いる絶縁テープはイミド化の済んだポリ
イミド樹脂よりなる。そのため、この絶縁テープを積層
し熱圧着するときに、絶縁層となるポリイミドテープか
らガスが発生することがなく、配線と絶縁テープ間の剥
離を生じることがない。また、ポリイミドよりなる接着
用樹脂も、圧着面に塗布した後に３００℃以下でイミド
化し、絶縁テープを圧着できる程度に半硬化すると共に
脱ガスされる。よって積層された各絶縁テープ間の剥離
を生じることがない。As described above, the insulating tape used in the semiconductor device and the manufacturing method of the present invention is made of imidized polyimide resin. Therefore, when the insulating tapes are laminated and thermocompression-bonded, no gas is generated from the polyimide tape serving as the insulating layer, and peeling between the wiring and the insulating tape does not occur. The adhesive resin made of polyimide is also degassed while being imidized at 300 ° C. or lower after being applied to the pressure-bonding surface, semi-cured to the extent that the insulating tape can be pressure-bonded. Therefore, peeling between the laminated insulating tapes does not occur.
【００２２】もし熱圧着時に絶縁テープや接着用樹脂か
らガスが発生しても、絶縁基板と絶縁テープ上の配線に
はＣｏメッキによる保護膜が被覆されているので、配線
の酸化を防止することができ、半導体装置の歩留りが向
上する。本発明の半導体装置に用いる表面に配線２を形
成した絶縁テープ１は、図２に示す方法で製造される。
図中１は絶縁テープ、２は配線、５はレジスト、８は導
体層、１０は保護膜、１１は配線用メッキを示してい
る。 〔第１工程〕図２（１）に示す様に、厚さ２０μｍ程の
イミド化が済んだポリイミド樹脂からなる絶縁テープ１
上に、スパッタ又は蒸着により配線２となる導体層８を
形成する。導体層８にはＣｒが用いられる。 〔第２工程〕図２（２）に示す様に、導体層８の表面に
レジスト５を塗布し、フォトリソ工程により配線形状に
レジストパターンを形成する。 〔第３工程〕図２（３）に示す様に、導体層８を電極と
してＣｕ等の配線となる金属をメッキ法によりレジスト
パターンの形状に形成し、配線用メッキ１１とする。 〔第４工程〕図２（４）に示す様に、レジストパターン
を除去後、配線用メッキ１１をマスクして導体層８をエ
ッチングし配線２を形成し、配線２の表面をＣｒ、Ｃｏ
等の無電解メッキによる保護膜１０で被覆する。Even if gas is generated from the insulating tape or the adhesive resin during thermocompression bonding, the wiring on the insulating substrate and the insulating tape is covered with a protective film by Co plating, so that the wiring is prevented from being oxidized. Therefore, the yield of semiconductor devices is improved. The insulating tape 1 having the wiring 2 formed on the surface used in the semiconductor device of the present invention is manufactured by the method shown in FIG.
In the figure, 1 is an insulating tape, 2 is wiring, 5 is resist, 8 is a conductor layer, 10 is a protective film, and 11 is wiring plating. [First Step] As shown in FIG. 2 (1), an insulating tape 1 made of a polyimide resin having a thickness of about 20 μm and having been imidized.
A conductor layer 8 to be the wiring 2 is formed on the top by sputtering or vapor deposition. Cr is used for the conductor layer 8. [Second Step] As shown in FIG. 2B, a resist 5 is applied to the surface of the conductor layer 8 and a resist pattern is formed in a wiring shape by a photolithography process. [Third step] As shown in FIG. 2C, a metal for wiring such as Cu is formed into a resist pattern shape by a plating method using the conductor layer 8 as an electrode to form the wiring plating 11. [Fourth step] As shown in FIG. 2D, after removing the resist pattern, the conductor layer 8 is etched by masking the wiring plating 11 to form the wiring 2, and the surface of the wiring 2 is made of Cr, Co.
And a protective film 10 formed by electroless plating.
【００２３】本発明による半導体装置とその製造方法で
は、多層配線構造となる各層の配線を別々の絶縁テープ
上に予め形成しているので、同一の配線を持った絶縁テ
ープを一度に大量に形成しておくことができ、製造期間
の短縮と、製造コストの削減をすることができる。ま
た、この絶縁テープは絶縁基板への熱圧着に先立って検
査をおこない、表面の配線に欠陥がないものだけ積層し
ていくことができるので、全ての配線層をスパッタやフ
ォトリソ工程で積層していく従来の薄膜半導体装置より
も歩留りを向上することができる。In the semiconductor device and the method of manufacturing the same according to the present invention, since the wirings of each layer having the multilayer wiring structure are formed in advance on separate insulating tapes, a large amount of insulating tapes having the same wirings are formed at one time. The manufacturing period can be shortened and the manufacturing cost can be reduced. In addition, this insulating tape can be inspected prior to thermocompression bonding to the insulating substrate, and only those without defects on the surface wiring can be laminated, so all wiring layers are laminated by sputtering or photolithography process. The yield can be improved over the conventional thin film semiconductor device.
【００２４】薄膜半導体装置の絶縁層は、一層につき２
５〜３０μｍの厚さにする事が求められているが、本発
明で用いる絶縁テープは厚さが２０μｍ程度なので、こ
の絶縁テープにより多層配線を形成していった半導体装
置の厚さが、スパッタ又は蒸着により多層配線を形成し
ていった従来の薄膜半導体装置の厚さよりも厚くなるこ
とはない。The number of insulating layers of the thin film semiconductor device is 2 for each layer.
Although the thickness of the insulating tape used in the present invention is about 20 μm, the thickness of the semiconductor device in which the multi-layer wiring is formed by this insulating tape is sputtered. Alternatively, it does not become thicker than the conventional thin film semiconductor device in which the multilayer wiring is formed by vapor deposition.
【００２５】[0025]
【発明の効果】以上説明した様に、本発明によれば表面
に配線が形成された絶縁テープを絶縁基板上に積層し、
圧着して多層配線構造とする半導体装置を、各絶縁テー
プ間の剥離を生じさせず、また配線の酸化を生じさせず
に得ることができる等、実用上の効果が著しい。As described above, according to the present invention, an insulating tape having wiring formed on the surface thereof is laminated on an insulating substrate,
A semiconductor device having a multilayer wiring structure by pressure bonding can be obtained without causing peeling between the insulating tapes and without causing oxidation of the wiring.
【図１】本発明の実施例による半導体装置とその製造方
法を示す図である。FIG. 1 is a diagram showing a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention.
【図２】本発明の半導体装置に用いる絶縁テープを示す
図である。FIG. 2 is a diagram showing an insulating tape used in the semiconductor device of the present invention.
【図３】従来の薄膜半導体装置とその製造方法を示す図
である。FIG. 3 is a diagram showing a conventional thin film semiconductor device and a method for manufacturing the same.
【図４】従来の多層配線基板の製造方法を示す図であ
る。FIG. 4 is a diagram showing a conventional method for manufacturing a multilayer wiring board.
１・・・絶縁テープ ２・・・配線 ３・・・絶縁基板 ４・・・接着用樹脂 ５・・・レジスト ６・・・ビアホール ７・・・導電用メッキ ８・・・導体層 ９・・・絶縁層 １０・・・保護膜 １１・・・配線用メッキ １２・・・金属ビア １３・・・半導体チップ １４・・・ピン ２１・・・シート状感光性ポリイミド前駆体 ２２・・・金属箔 ２３・・・スルーホール孔 ２４・・・スルーホールコンタクト ２５・・・配線パターン ２６・・・セラミック基板 ２８・・・絶縁層 1 ... Insulating tape 2 ... Wiring 3 ... Insulating substrate 4 ... Adhesive resin 5 ... Resist 6 ... Via hole 7 ... Conductive plating 8 ... Conductor layer 9 ... Insulating layer 10 ... Protective film 11 ... Wiring plating 12 ... Metal via 13 ... Semiconductor chip 14 ... Pin 21 ... Sheet-shaped photosensitive polyimide precursor 22 ... Metal foil 23 ... Through hole 24 ... Through hole contact 25 ... Wiring pattern 26 ... Ceramic substrate 28 ... Insulating layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/46 Ｂ 6921−4Ｅ Ｅ 6921−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/46 B 6921-4E E 6921-4E
Claims (2)
による酸化を防止する為の保護膜（１０）で被覆された
第１の配線（２）が表面に形成された絶縁基板（３）
と、 前記保護膜（１０）で被覆された第２の配線（２）が表
面に形成され、前記絶縁基板（３）上に前記接着用樹脂
（４）により複数の層が熱圧着され積層された絶縁テー
プ（１）とを有し、 前記絶縁テープ（１）に設けられたビアホール（６）に
より、前記第１の配線（２）と第２の配線（２）が接続
されており、 複数積層された前記絶縁テープ（１）上に半導体チップ
（１３）が搭載され前記第２の配線（２）と電気的に接
続されていることを特徴とする半導体装置。1. An insulating substrate (3) having on its surface a first wiring (2) covered with a protective film (10) for preventing oxidation due to a gas generated when the adhesive resin (4) is heated.
And a second wiring (2) covered with the protective film (10) is formed on the surface, and a plurality of layers are thermocompression-bonded and laminated on the insulating substrate (3) by the adhesive resin (4). An insulating tape (1), and the first wiring (2) and the second wiring (2) are connected by a via hole (6) provided in the insulating tape (1). A semiconductor device comprising a semiconductor chip (13) mounted on the laminated insulating tapes (1) and electrically connected to the second wiring (2).
線（２）を形成する工程と、 前記絶縁基板（３）表面の第１の配線（２）を保護膜
（１０）により被覆する工程と、 前記絶縁基板（３）表面に接着用樹脂（４）を塗布し加
熱して、前記接着用樹脂（４）を半硬化させる工程と、 表面に保護膜（１０）で被覆された第２の配線（２）を
有する絶縁テープ（１）を、前記接着用樹脂（４）を介
して前記絶縁基板（３）上に加熱し加圧して、半硬化さ
せた前記接着用樹脂（４）を全硬化させて前記絶縁基板
（３）上に圧着する工程と、 前記絶縁テープ（１）に前記第１の配線（２）と第２の
配線（２）を結ぶビアホール（６）を形成する工程と、 前記ビアホール（６）を導電用メッキ（７）により充填
する工程と、 複数積層された前記絶縁テープ（１）上に半導体チップ
（１３）を搭載し、前記第２の配線（２）と電気的に接
続する工程とを有することを特徴とする半導体装置の製
造方法。2. A step of selectively forming a first wiring (2) on the surface of the insulating substrate (3); and a step of protecting the first wiring (2) on the surface of the insulating substrate (3) with a protective film (10). A step of coating, a step of applying an adhesive resin (4) to the surface of the insulating substrate (3) and heating it to semi-cure the adhesive resin (4), and a surface of the insulating substrate (3) covered with a protective film (10). The insulating tape (1) having the second wiring (2) is heated and pressed onto the insulating substrate (3) through the adhesive resin (4) to be semi-cured. 4) fully curing and crimping onto the insulating substrate (3), and a via hole (6) connecting the first wiring (2) and the second wiring (2) to the insulating tape (1). Forming step, filling the via hole (6) with conductive plating (7), and insulating the stacked layers A step of mounting a semiconductor chip (13) on the tape (1) and electrically connecting the semiconductor chip (13) to the second wiring (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5002216A JPH06209053A (en) | 1993-01-11 | 1993-01-11 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5002216A JPH06209053A (en) | 1993-01-11 | 1993-01-11 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06209053A true JPH06209053A (en) | 1994-07-26 |
Family
ID=11523168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5002216A Pending JPH06209053A (en) | 1993-01-11 | 1993-01-11 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06209053A (en) |
-
1993
- 1993-01-11 JP JP5002216A patent/JPH06209053A/en active Pending
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