JPH06208965A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of doping processes by forming a pattern on a natural oxidation film to be used as a mask and, through selective adsorption of dopant atoms, forming a dopant atom layer pattern. CONSTITUTION:After an Sb atom 14 is adsorbed to an Si substrate 10, surface oxidation is performed in the oxygen atmosphere of 1Pa, so that a surface oxidation film 15 is formed. At that time, the Sb atoms boundary-segregate on the Si side of an oxidation film/Si boundary. Then, a part of the surface oxidation is irradiated with excimer laser light 12 for heating, sublimation, and eventual its removal. At this time, the Sb atoms also thermally desorb for its removal. Then HBO2 molecule 13 is selectively adsorbed on the Si surface, and lastly drive-in diffusion is performed in nitrogen so as to remove anoxidation film by etching, thus a well layer for CMOS is formed. With this, the number of doping processes can be reduced by more than a half.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to an impurity doping method.

[0002]

2. Description of the Related Art In Si LSIs, while higher integration and higher speed due to miniaturization are progressing, lower voltage and lower power consumption are required at the same time. For high integration, a metal-oxide film-semiconductor type field effect semiconductor device (Meta) having a simple structure is used.
l-Oxide-Semiconductor Fie
ld Effect Transistor: MOS
FET) is suitable, and for low power consumption, a complementary MOSFET in which an n-channel FET and a p-channel FET are mixedly mounted on the same substrate is suitable. In the complementary MOSFET, the control of the threshold voltage and the formation of the source / drain regions are performed by implanting channel ions independently of n and p. In addition, fine MOSFE
In T, a short channel effect such as punch-through in which a current flows between the source and drain through the substrate is a problem, and a dopant of the same conductivity type as that of the substrate is ion-implanted under the channel at a high concentration to form a punch-through stopper layer. Has been adopted. By the way, the gate length is 0.1μ
For elements having a thickness of m or less, it is necessary to reduce the depth of the punch-through stopper layer, but with the ion implantation method, even if the energy of ions is lowered, the spread of the impurity distribution is reduced to 10%.
It cannot be suppressed to below nm. Therefore, there arises a problem that the impurity concentration on the surface becomes high and the threshold voltage becomes high. In order to realize a low voltage operation of 1.5V level in the future, it is necessary to set the threshold voltage to ± 0.3V or less, and the ion implantation method has a lower threshold voltage controllability. It has been pointed out that the problem is not enough. Therefore, a technique for forming a high-concentration doping layer and growing a low-concentration channel layer on the high-concentration doping layer using a low-temperature epitaxial growth method such as molecular beam epitaxy is applied Physics Letters, Vol. 54 (198).
9) 1869 (Applied Physics Le)
tters, 54, (1989) p. 1869). In addition, the depth of the pn junction of the source / drain has a limit to the shallow junction in the ion implantation method. Therefore, a method of irradiating an Si surface with an excimer laser in a gas such as B ₂ H ₆ and performing doping is a journal method. of·
Applied Physics, Vol. 67 (1990) 72
Page 04 (Journal of Applied Ph
ysics, 67, (1990) p. 7204).

In ULSI, the number of steps tends to increase with miniaturization, and in the future, in order to proceed with integration, a process technology effective in reducing steps has been required.
From this point of view, the conventional ion implantation method has a problem in that it is necessary to use a resist mask because the selective doping cannot be performed, and the number of steps is increased. Moreover, about half of all photo processes are used for ion implantation.

[0004]

From the above point of view, there are many problems with the above method which should replace the ion implantation. That is, the above-mentioned first method has a problem that doping cannot be selectively performed within the wafer surface, and there is a problem that it is difficult to apply it to a complementary FET or the like. Further, in the above second method, the amount of doped atoms is complicatedly dependent on the gas flow rate, substrate temperature, laser power, etc., and the doping amount cannot be controlled at the atomic layer level. There was a problem that it would be done. Therefore, an object of the present invention is to provide a method for selectively forming, ie, patterning, a dopant controlled at the atomic layer level even in a plane.

[0005]

A method for solving the above problem will be described with reference to FIG. First, 1 on the Si10 surface
A native oxide film 11 having a film thickness of about nm is formed on the Si surface, and this is locally heated by irradiation of an excimer laser 12 or the like, sublimated, and processed into a pattern. Next, HBO ₂
Dopant atom (molecule) such as molecule 13 and Sb atom 14
Is controlled and adsorbed at the atomic layer level. At this time, we consider the Si substrate temperature of 800 ° C, which is the sublimation temperature of the natural oxide film.
It has been newly found that the adsorption occurs on the Si surface but not on the natural oxide film at the following low temperature.

In FIGS. 2 and 3, HBO ₂ (and Sb) is added to a Si substrate half of which is covered with a natural oxide film, at a K cell temperature of 90.
0 ° C (430 ° C), substrate temperature 600 ° C for 1 hour (10
Min) is an Auger electron spectroscopy (AES) spectrum of the adsorbed sample. Here, the horizontal axis is the energy of Auger electrons, and the axes are shown in common. B spectrum 2
1 is a KLL transition having a peak at 179 eV, Sb spectrum 31 is a MNN transition having a peak at 454 eV,
Si spectrum 22 has a KL peak at 1619 eV
Focused on the L transition. As an index of B, Sb concentration, B, S
Values (B / Si, Sb / Si) obtained by normalizing the peak-to-peak value of the b spectrum by the Si value were used. This condition is B
Corresponds to about 0.5 ML (atomic layer) (about 1 ML for Sb). The peaks of B and Sb are clearly observed on Si, but hardly observed on the natural oxide film. That is, it was found that HBO ₂ and Sb were selectively adsorbed on the Si surface. B ₂ H _{6 as a} gas source hardly adsorbs on SiO _{2 at} 825 ° C. (1
However, it was found for the first time with respect to HBO ₂ and Sb, which are solid sources having high concentration controllability. Here, it is significant that the substrate temperature is a relatively low temperature of 800 ° C. or lower. That is,
After that, if the heat treatment is performed at 800 ° C. or higher, the natural oxide film that has been functioning as a mask can be heated and sublimated. The required selectivity depends on the device application, but if the substrate temperature is raised to 700 ° C,
It was found that a selectivity of 100 or more was obtained (Fig. 4).
Here, it is significant that the substrate temperature is a relatively low temperature of 800 ° C. or lower. That is, after this, 80
This is because if the heat treatment is performed at 0 ° C. or higher, the natural oxide film that has served as a mask can be heated and sublimated. In fact, FIG. 2 also shows the AES spectrum after annealing in UHV at 800 ° C. for 10 minutes. O after annealing
The peak of B has almost disappeared, but the peak of B has hardly changed. The results of examining this state by changing the annealing time are summarized in FIG. Although the strength of B gradually decreased by annealing at 800 ° C for 90 minutes,
This confirms that B is inwardly diffused in Si by secondary ion mass spectrometry. On the other hand, FIG. 9B shows the case of Sb, and the annealing temperature is 750 ° C. S
The b intensity decreases exponentially, clearly indicating that thermal desorption has occurred. That is, from the above experimental results, the natural oxide film serves as a mask for dopant atoms (molecules). In the case of B, the drive-in diffusion and the sublimation removal of the natural oxide film mask can be performed by the subsequent heating in vacuum (FIG. 1A). On the other hand, in the case of Sb, the surface oxide film 15 is formed, the interface segregation of the SiO ₂ / Si interface to the Si side is caused, and then the surface oxide film may be removed by etching.

The natural oxide film pattern forming method is as follows.
Not limited to the above. Oxide film etching by electron beam or ion beam irradiation in an etching gas may be used. Further, a method of irradiating a laser in oxygen gas for local oxidation, a method of irradiating a part of the hydrogen-terminated Si surface with an electron beam to remove hydrogen, and then growing a natural oxide film only in a part without hydrogen in oxygen. Etc. are also possible.

Further, as the dopant material, HBO ₂
Similarly, B ₂ O ₃ and B ₂ H ₆ are also possible. Further, like Sb, P, PH ₃ , As, AsH ₃ , SbH _{3 and the} like are also possible.

[0009]

As a result, it becomes possible to form regions having different conductivity types in the same semiconductor substrate, and the impurity distribution thereof is very rapid unlike the conventional ion implantation method.

[0010]

【Example】

Example 1 First, according to the present invention, Si complementary MOSFET (CMO
An example 1 of producing the S) well layer will be described with reference to FIG.

1 × 10 Sb atoms 14 are added to the Si substrate 10.
After adsorbing ¹³ / cm ² (a), surface oxidation was performed in an oxygen atmosphere of 1 Pa to form a surface oxide film 15 having a thickness of 3 nm (b). At this time, Sb atoms were Si at the oxide film / Si interface. The interface segregates to the side. Next, the excimer laser beam 12 was irradiated to heat a part of the surface oxide film 15 to sublimate and remove it (c). At this time, Sb atoms can also be removed by thermal desorption together. Then, the HBO ₂ molecule 13 on the Si surface is
10 ¹³ / cm ^{2 was} selectively adsorbed (d). Finally, drive-in diffusion was performed in nitrogen (e), the oxide film was removed by etching (f), and CMOS well layers 61 and 62 were formed.

In the present invention, since the n-type impurity layer and the p-type impurity layer are formed in a self-aligned manner, there is no mask misalignment, and a photo step (excimer laser irradiation) for forming a pattern is also performed once. Good. Further, since no resist is used, many washing steps are not required, and the process is all dry and clean. As a result of the above, conventional 1
The number of well forming steps, which was 6 steps, can be reduced to 7 steps including the pre-cleaning step.

Embodiment 2 Next, according to the present invention, Si complementary MOSFET (CMO
The second example of the production of the S) well layer will be described with reference to FIG.

First, 1 Sb atom 14 is added to the Si substrate 10.
Adsorption was performed at × 10 ¹³ / cm ² (a). Subsequently, the Si surface was locally oxidized by irradiating the excimer laser beam 12 in oxygen of 1 Pa to form a surface oxide film 15 having a thickness of 3 nm. At this time, Sb atoms segregate on the Si side of the oxide film / Si interface (b). Then, H on the unoxidized Si surface
BO ₂ molecule 13 was selectively adsorbed on 1 × 10 ¹³ / cm ² (d). Finally, drive-in diffusion is performed in nitrogen (e), the oxide film is removed by etching (f), and the CMOS
Well layers 61 and 62 for use were formed.

In the present invention, since the n-type impurity layer and the p-type impurity layer are formed in a self-aligned manner, there is no mask misalignment, and a photo step (excimer laser irradiation) for forming a pattern is also performed once. Good. Further, since no resist is used, many washing steps are not required, and the process is all dry and clean. As a result of the above, conventional 1
The number of well forming steps, which was 6 steps, can be reduced to 7 steps including the pre-cleaning step.

Embodiment 3 Next, an example in which a punch-through stopper of SiCMOS is formed by using the present invention will be described with reference to FIG.

Well layer 61 for n-channel FET, and
Si substrate 10 having p-channel FET well layer 62
(A), and extremely surface oxidation was performed using an oxygen radical beam to form a surface oxide film 11 having a thickness of 2.5 nm or less (c). Next, the excimer laser light 12 is passed through the n-channel FE.
The T well layer 61 was irradiated and the surface oxide film was removed by heating and sublimation (c). Then, HBO ₂ molecule 13 (1 × 10
After selectively adsorbing ¹³ / cm ² ) (d), the entire Si substrate was heated to 800 ° C. or higher in vacuum. In this process, HB
The O ₂ molecule 13 is completely decomposed, H and O are desorbed, and only the B atom 15 diffuses into Si. Also, p channel F
The surface oxide film 11 remaining on the ET well layer 62 is also sublimated and removed. (E) Further, here, when heating in a hydrogen atmosphere instead of heating in vacuum, the surface oxide film 1
The B atom slightly adsorbed on 1 can be removed. Next, the n-channel FE is grown by growing the Si single crystal layer 83.
A punch through stopper layer 81 for T was formed (f). Subsequently, by adsorbing Sb atoms 14 (1 × 10 ¹³ / cm ² ), patterning, and growth of the Si single crystal layer 84, p channel F
A punch through stopper layer 82 for ET was formed (g,
h, i).

When a MOSFET is formed using this structure, the threshold voltage is determined by the film thickness of the Si single crystal layers 83 and 84, so that the doping for controlling the threshold voltage is unnecessary. There is. As a result, the number of steps has been reduced from the conventional 20 steps to 8 steps. Also, δ
By realizing a functional doping profile, a MOSFET with a gate length of 0.1 μm can be used without punch through.
It turns out to work fast.

Example 4 Finally, a shallow junction source of SiCMOS using the present invention,
An example of forming the drain will be described with reference to FIG.

After forming the well layers 61 and 62 and the punch-through stopper layers 81 and 82 on the Si substrate 10 by the method described in Embodiment 1 (or 2) and 3, the element isolation oxidation region 91 and the gate oxidation are formed. A film 92 and a polycide gate electrode 93 were formed. Next, after chemically cleaning the Si substrate, Sb atoms 14 are adsorbed at 1 × 10 ¹⁵ / cm ² (a) and then oxidized with an oxygen radical beam to a thickness of 2.
A surface oxide film 11 having a thickness of 5 nm or less was formed (b) At this time,
Sb atoms segregate on the Si side of the oxide film / Si interface. Then, the excimer laser 12 is irradiated to the surface oxide film 1
Part of 5 was heated to sublimate and removed (c). At this time, Sb atoms can also be removed by thermal desorption together. Subsequently, HBO ₂ molecules 13 were selectively adsorbed on the Si surface at 1 × 10 ¹⁵ / cm ² (d). Finally, drive-in diffusion is performed in nitrogen to form a source / drain region 9 for the n-channel FET.
4. Source / drain regions 95 for p-channel FET were formed (e).

According to the present invention, the number of steps is reduced from 11 steps in the prior art to 5 steps. Also, the junction depth is 0.05 μm
The following source and drain pn junctions could be formed, and high-speed operation of the complementary FET having the structure shown in FIG. 5 and having a gate length of 0.1 μm or less could be realized.

[0022]

According to the present invention, the number of doping steps can be reduced to less than half. Further, a doping layer controlled at the atomic layer level can be formed, and high speed operation of a complementary FET having a gate length of 0.1 μm or less becomes possible.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an experimental result for explaining the means of the present invention.

FIG. 3 is an experimental result for explaining the means of the present invention.

FIG. 4 is an experimental result for explaining the means of the present invention.

FIG. 5 is an experimental result for explaining the means of the present invention.

FIG. 6 is a cross-sectional view showing a well forming step according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a well forming step according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a punch-through stopper forming step which is an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a source / drain formation step which is an embodiment of the present invention.

[Explanation of Codes] 10 --- Semiconductor Substrate, 11 --- Surface Oxide Film, 12--Excimer Laser Light, 13--HBO ₂ Molecule, 14--Sb
Atoms, 15-B atoms, 16- Surface oxide film, 21-
B spectrum, 22-Si spectrum, 23-O spectrum, 31-Sb spectrum, well layer for 61-n channel FET, well layer for 62-p channel FET, punch through for 81-n channel FET Stopper layer, punch through stopper layer for 82-p channel FET, 83-Si single crystal layer, 84-Si single crystal layer,
91 --- oxidation region for device isolation, 92 --- gate oxide film,
93 --- polycide gate electrode, 94 --- n channel F
Source and drain for ET, source and drain for 95-p channel FET.

Claims (5)

[Claims] 1. A semiconductor region having the same conductivity type as or different from that of a first conductivity type semiconductor substrate is formed on a Si surface having a pattern-formed Si oxide film having a thickness of 2.5 nm or less. A method of manufacturing a semiconductor device, comprising a step of selectively adsorbing impurity atoms or molecules (hereinafter abbreviated as a dopant) for achieving the above. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the adsorbing dopant is formed in a pattern to form semiconductor regions having different conductivity types in the semiconductor substrate of the first conductivity type. And a method for manufacturing a complementary field effect transistor. 3. The method for manufacturing a semiconductor device according to claim 1, wherein energy of a laser beam, ultraviolet light, X-ray, electron beam or the like is locally irradiated to pattern the Si oxide film. Of manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein HBO ₂ , B ₂ O ₃ and B ₂ H _{6 are used} as p-type dopants.
And the like, and after adsorption, the above Si oxide film is heated in vacuum to be removed by sublimation. 5. The method of manufacturing a semiconductor device according to claim 1, wherein Sb, P, PH ₃ or the like is used as an n-type dopant, and after adsorbing, the dopant is treated in an oxidizing atmosphere to obtain Si as a dopant.
A method of manufacturing a semiconductor device, characterized in that the semiconductor device is diffused therein.