JPS63122177A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize high-speed operation by a method wherein a Ge film whose mobility of an electron and a hole is bigger than that of Si is formed on an Si substrate and this Ge is used as a channel for a MOS-type transistor. CONSTITUTION:A Ge layer 6 is formed in a region which is located just under a gate electrode 4 and a gate insulating film 3 and is transformed into a channel. In addition, a source and a drain are constructed by a germanium layer 7 and an Si layer 8 doped with an impurity to give a p-type or an n-type. Because the mobility of germanium is by about two times bigger for an electron and by about 4.5 times bigger for a hole than that of Si, a MOS-type transistor, of the identical size, constructed by the Ge can operate by two times faster for an n-channel and by 4.5 times faster for a p-channel than in the case of the Si. As compared with the MOS-type transistor constructed by the Si, the characteristic of the p-channel is improved remarkably and is nearly equal to that of the n-channel; it is possible to greatly improve the characteristic of an integrated circuit of the CMOS structure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device such as an MO8 type transistor capable of high-speed operation and a method for manufacturing the same.

[Conventional technology]

As shown in FIG. 5, the conventional MO8 transistor of S1 has a region surrounded by an element isolation insulating film 2 on an 81 substrate 1, and a gate insulating film 3 and a gate electrode 4 are formed in the region.
, and further has a source/drain layer 5 formed therein. The region where current flows in this MO8 type transistor is directly under the gate insulation b43o, which is sandwiched between the source and drain. In a conventional MO8 type transistor, this channel is connected to the substrate St, st, IE, ji, 1
500 m27 Va@e is relatively large, but the hole mobility is only 450 cm2/Va e c. That is, when comparing the characteristics of an n-channel 51MO8 type transistor and a p-channel NSIMOB type transistor configured with the same dimensions, the operating speed of the p-channel is considerably slower.

Furthermore, in the conventional MOB transistor formation process, the source/drain is formed by ion-implanting impurities that give n-type or p-type, such as As, P, or B. The source/drain layer formed in this way is
It is difficult to make the depth shallower. In particular, B used for the source/drain layer of a p-channel MO8 type transistor has a large diffusion coefficient in 81, and the source/drain depth becomes deep. As described above, when the drain layer is deep, good operating characteristics with good reproducibility are exhibited. There was a problem in that it was difficult to fabricate a small MO8 type transistor with a short channel length (for example, J, R, Br.ws).

”Phyalcm of MOS Transl.
stor', in D., Kahng, ED.

Appl, 5olid 5tat@5science, S
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Accad@mic Press, New York,
(1981). This is mainly due to the gate voltage m'it in the 81 substrate separated from the gate oxide film between the source and drain in FIG. This is caused by the flow of current that cannot be controlled at certain points (punch-through effect). In order to reduce this current, it is sufficient to increase the impurity concentration in the Sl substrate, but conversely, when the impurity concentration is increased, the mobility of electrons or holes decreases. Alternatively, problems such as the dark value voltage of the MO8 type transistor becoming too high may occur, and the characteristics of the MOS transistor may deteriorate.

The deterioration of the characteristics of the fine MO8 type transistor as described above is remarkable in the case of p-channel MO8, so in particular,
When the LSI has a 0MO8 configuration, the operating characteristics are:
This is determined by the characteristics of the p-channel MO8 type transistor, which has poor characteristics.

[Problem that the invention seeks to solve]

The present invention solves two problems in the MO8 type transistor of No. 81: the hole mobility is low and the characteristics of the MO8 type transistor with a short channel length are deteriorated. M.O.
An object of the present invention is to provide a semiconductor device having an 8-type transistor structure and a method for manufacturing the same.

[Means and effects for solving the problems] The present invention comprises an epitaxial layer made of germanium on a silicon substrate and a gate insulating film formed thereon, and at least a source region and a drain region in the epitaxial layer made of damanium. and a channel region are formed, and a gate electrode is formed on the gate insulating film on the region including the channel region. An epitaxial layer made of high-resistance germanium doped with impurities at a low concentration is formed on a silicon substrate which has been made low in resistance by doping impurities at a high concentration, and a gate insulating film is formed thereon. A source region, a drain region, and a channel region are formed in an epitaxial layer consisting of an insulated gate field effect transistor, and a gate electrode is formed on the gate insulating film on the region including the channel region. The method further includes a step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the dalmanium layer, and a step of forming the gate electrode. A step of ion-implanting an impurity as a mask and an ion-implanting step in which only the impurity implanted into the rA/manium layer is electrically activated, and the impurity implanted into the silicon crystal substrate is electrically activated. The method further comprises a step of performing heat treatment at a temperature at which the germanium layer is not electrically activated and electrically activating only the impurity implanted into the germanium layer to form the source region and drain region of the insulated gate field effect transistor. The method also includes a step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the dalmanium layer, and a step of forming the gate electrode. The impurity is diffused as a mask, and the insulating layer is diffused only into the germanium layer.
The method is characterized in that it includes a step of forming a source region and a drain region of a field effect transistor. Therefore, the present invention forms a G@ film with higher electron and hole mobility than St on a St substrate, and converts this G into MO
Its main feature is that it can be used as a channel for an 8-type transistor. This is different from the conventional 51 MO8 type transistor technology, which uses 81 for the channel as shown in Kozo O's. As described above, if p-channel and n-channel MO8 type transistors with Go channels formed on the 81 substrate are formed, the mobility of G holes and electrons is high;
This results in a transistor capable of high-speed operation.

〔Example〕

(Example 1) FIG. 1 is a diagram explaining the first example of the present invention, in which a G layer 6 is formed in a region directly under the gate electrode 4 and gate insulating film 3 that will become a channel. It is. In addition, the structure includes a germanium layer 7 and an S1 layer 8 doped with impurities that provide p-type or n-type conductivity as the source and drain. The mobility of r.rumanicum is about twice as large for electrons and about 4.5 times for holes as compared to Sl, so it can be used in MOS with the same dimensions.
(double) for n-channel, p when composing a transistor
Operates 4.5 times faster in channels. Compared to an MO8-type Sl transistor, the p-channel characteristics are greatly improved and approach n-channel characteristics, so the characteristics of an integrated circuit with a CMOB configuration can be greatly improved.

Next, the steps for forming the embodiment shown in FIG. 1 will be explained.

In the same manner as the conventional MO8 type transistor formation process,
A transistor formation region surrounded by the element isolation insulating film 2 is created (FIG. 2(a)). Next, a G layer 6 is epitaxially grown thereon. As a method for this bi-taxial growth, a known MBE method or CVD method may be used. In particular, by using the CVD method using G@H4 gas as a reaction gas, epitaxial growth can be selectively performed only on S1 (FIG. 2(b)).

Furthermore, this growth temperature can be lowered to as low as 300°C. Next, a gate insulating film 3 is formed on the G epitaxial film (FIG. 2(C): here, the Ge
Although the gate insulating film is formed only on the layer, it goes without saying that it may be formed covering the element isolation region as well.) Next, the gate electrode 4 is formed as shown in FIG.
)) Using this as a mask, an impurity giving n-type or p-type is ion-implanted, and then a known activation heat treatment can be performed (FIG. 2(, )).

Incidentally, since the epitaxial growth temperature of the G@ film can be easily lowered (300 DEG C. to 700 DEG C.), diffusion of impurities from the base S1 can be prevented from occurring during the formation of the G@ film. In other words, the impurity rust degree of the G layer can be determined independently of the impurity concentration of the underlying Sl layer. By using the characteristics of this formation method, it is possible to form the following structures. At the time of the step shown in FIG. 2(a), at least near the surface of the substrate 81 layer is doped with an impurity that provides a high concentration of n-type or pm. Next, in the process shown in Fig. 2(b), s G
When or after the epitaxial growth of @m, a low concentration of impurity is doped (the impurity placement affects the threshold of the MO8 type transistor, so
It is necessary to consider the value when choosing. In addition, doping of impurities can be done by diffusion from the surface of G after film formation or by ion implantation. temperature, so it is quite possible). After this, by continuing the steps explained in FIG. 2, the impurity concentration of the substrate 81 layer will be increased to a high concentration.
The impurity concentration in the region of the G layer 6 that becomes the channel can be made low. In this structure, if the thickness of the G layer 6 is made sufficiently shallow with respect to the channel length (the width of the G layer 6 in the source/drain direction), As explained, the nine-mother anti-through effect can be suppressed. Furthermore, since the 81 layer below the 00 layer has a high concentration, no 9 ruti-through occurs in the Si layer. In other words, by keeping the impurity humidity in the channel region low, it is possible to suppress the throughput. In the channel G region, the impurity concentration is low, so the mobility of electrons or holes is high.
High-speed operation becomes possible.

(Example 2) In Example 1, the formation of the diffusion layer shown in FIG.
When diffusing an impurity that gives n-type or p-type from the surface, the diffusion coefficient of most elements is much smaller in pSi than in Ga, so it is best to diffuse only into G. I can do it. Therefore, as shown in Figure 3,
It is possible to realize a structure in which the diffusion layer is mostly confined within the G@ layer.

If the thickness of the 06 layer is made sufficiently thinner than the channel length, a shallow diffusion layer can be formed.

(Example 3) In Example 1, after forming the diffusion layer in FIG. 3(-) by ion-implanting impurities,
When activated by heat treatment at a temperature of about 0°C to 700°C,
Only the impurities in Ge are electrically activated, and the impurities in S1 are not activated. Therefore, an effectively shallow diffusion layer can be formed.

In addition, when implanting impurity ions, the acceleration energy and dose of ion implantation are adjusted to at least disturb the lattice of the Si layer to make it nearly amorphous, and then heat treatment is performed at about 600 ° C. or less, Only the G layer recovers crystallinity, and the ion-implanted Si layer remains amorphous. (ζHere, depending on the type of impurity, 81
When ions are implanted until the layer becomes sufficiently amorphous,
G. It is possible that the solid solubility limit of impurities in the film may be exceeded.

In that case, it is sufficient to ion-implant G or Sl together with impurities to increase the total dose. Furthermore, there is a possibility that the 81 layer near the G@A1 interface partially recovers its crystallinity, but -1 this is not a problem because this thickness is sufficiently thin. ) With such a structure, the amorphous region (corresponding to 8 in FIG. 1) ion-implanted into layer 81 becomes a high-resistance layer. Therefore, since the structure is such that the source/drain layer is located on the high resistance layer, the junction capacitance of the source/drain can be reduced. Furthermore, if the impurity concentration in the region of the base S1 substrate close to the G layer is made relatively high, punch-through will not occur. In other words, a MOS f using a low-resistance substrate with a high impurity concentration, an extremely small junction capacitance, and a small decrease in kh degree due to impurities in the channel region.
fi ) 2' inzostar can be constructed.

(Example 4) In a typical 0810MO8 type transistor, a 5in2 film formed by thermally oxidizing the substrate S1 is often used as the gate insulating film. In order to use 5to2 as a gate insulating film in the MO8 type transistor according to the present invention, there is a method of epitaxially growing St on the G layer and thermally oxidizing it. A process for forming an MO8 type transistor according to the present invention using this method is shown in Figure 4. 8
1. An upper 81 layer 9 is epitaxially grown on the Go layer formed on the substrate 1 (FIG. 4(a)).

Since the natural oxide film on the Go surface is elevated as G.0 when heated above about 400'C, a clean G.surface can be easily obtained. After this, 81 of known SiH4 etc.
CVD method and SiMBE-
St can be easily epitaxially grown on Ge by a method such as a method. Next, the Sl on this table is thermally oxidized to form a 5to2 layer 10 (FIG. 4(b)).

The larger pA oxidation temperature for this 8102 layer formation is approximately 850
If the temperature is below ℃, Ga-
31 interdiffusion is suppressed. Next, the gate electrode 4 is formed (Fig. 4(, )), and then the source/drain layer 12 is formed by ion implantation (Fig. 4(d)).
), an MO5 type transistor according to the present invention can be formed.

Here, a vcst layer 9 is left between the 5102 layer 10 and the G/layer σ in the gap formed by 8102 formed by thermal oxidation of 810 on the surface. There is no problem since it is considered that it operates as an r-to insulating film. When forming the source/drain by diffusion from the surface, the 8102
This may be performed after removing layers 10 and 81 and layer 11.

(Example 5) Another method for forming a stable gate insulating film will be described. For example, when growing a Ge layer epitaxially by CVD using a gas containing G as a constituent element, such as GeH4, immediately after growing the Ge layer, do not expose the Ge film to the atmosphere and grow it by CVD. If the next gate insulating film is formed, there will be less contamination at the interface between the insulating film and G. In other words, the density of interface states formed at the insulating film and the G interface can be reduced.

For example, when 5102 is used as a gate insulating film, it is sufficient to use the following process. In the process shown in Figure 2(b),
G. is formed by, for example, a CVD method using GeH4 gas. Next, the introduction of G.H4 gas is stopped, followed by, for example, SiH4 or s t 2H6 gas and, for example, 02. Rirui introduces an oxidizing gas such as N208
If 102 layers are formed, Ge/5i0 with low interface state density
2 interfaces are formed. In addition, in the above process, if only 5IH4 gas is introduced immediately after stopping the GeH4 gas, and an oxidizing gas such as 02 is introduced after a while, G・A-i,
/S i O2 can be constructed. The epitaxial growth temperature of G by CVD can be 300°C to 600'c5, so if the introduction of G and H4 gas is stopped at this temperature and SiH4 gas is introduced, the deposition rate of Si will be several times higher than that of the previous one. Can be done in less than 1 minute. Therefore, Ge7B
i/S i 02 The thickness of the middle 31 layers of the bridge structure is 0.1
It is easy to control the thickness to about t + m - several nm,
When forming an MO8 type transistor, G can be used as the main channel region.

That is, since Ga, which has a higher mobility than Sl, serves as a channel, the characteristics of the MO8 type transistor are improved.

(Example 6) Since the heat treatment temperature required for forming the source/drain by ion implantation into the G layer is as low as about 500°C to 700°C, an insulating film with somewhat poor heat resistance such as Ta 205 can be used as the gate insulating film. You can also use

For the same reason, a metal with a low melting point or somewhat poor heat resistance, or a metallic compound such as metal silicide can also be used as the gate metal.

〔Effect of the invention〕

As explained above, if p-channel and n-channel MO8 type transistors with G as a channel formed on an 81 substrate are formed, high-speed operation is possible due to the high mobility of holes and electrons in G. This has the advantage of being a possible transistor.

Since the epitaxial growth of Go on S1 is possible at temperatures below 800°C, there is almost no contamination of impurities from the substrate S1 into the G@epitaxially grown film. A low concentration Ge layer can be epitaxially grown. If this is used as a channel, the channel region has a low impurity concentration and can suppress knock-through even when the mobility is high. Therefore, there is an advantage that a fine MO8 type transistor that operates at high speed can be produced.

Furthermore, if we take advantage of the fact that the temperature at which impurities and diffusion occur in Ge is 81°C lower, or that the activation temperature of impurities ion-implanted into Ge is significantly lower than 81°C, it is possible to The depth can be stopped at G/layer thickness. Therefore, G.

By reducing the layer thickness, a shallow diffusion layer can be formed and the known short channel effect can be reduced.
In addition, when forming sources and drains by ion implantation, recovery of the G crystal lattice after ion implantation has the advantage of improving the stability and reproducibility of the operating characteristics of J type transistors. is Sl 200℃～3
Taking advantage of the fact that it occurs at a temperature as low as 00°C, if the lower part of the Ge source and drain is made amorphous during ion implantation for source/drain formation, and only the Ge layer is crystallized,
A structure in which the source and drain are formed on high-resistance amorphous Si can be obtained. Therefore, St with high impurity daughterness
Even if an MO8 type transistor with G as a channel is formed on the substrate, there is an advantage that the junction capacitance between the source/drain of G and the substrate 81 can be reduced. In other words, it is possible to construct an integrated circuit that operates at high speed in a high-speed layer.

On the other hand, if a thin 81 layer is formed on the G layer and an 8102 layer is formed thereon as a gate insulating film, a good gate insulating film-channel interface can be obtained.

In addition, since the source/drain formation in the G@ layer can be performed at a relatively low temperature, it is possible to use an insulating film such as Ta205, which has somewhat poor heat resistance, for the gate insulating film, or a metal with poor heat resistance for the gate electrode. It has the advantage of being possible.

[Brief explanation of the drawing]

1H is a diagram showing an example of the cross-sectional structure of the MOa type transistor according to the present invention, Figure 2 is a diagram showing an example of the formation process of the MOB type transistor according to the present invention, and Figure 3 is a diagram showing an example of the process of forming an MOB type transistor according to the present invention. FIG. 4 is a diagram showing an example of the cross-sectional structure of an MO8 type transistor according to the present invention in which the source and drain are formed using 8102 as a gate insulating film, and FIG. The figure is a diagram showing a cross-sectional structure of a conventional MO8 type transistor. 1... 81 substrate, 2... Insulating film for element isolation, 3...
- Gate insulating film, 4...-gate electrode, 5... Source/drain layer, 6... G layer, 1... Dalmanium layer Ji mmm Si layer doped with impurity, 9...
81 layer, 10... 5tO2 layer, 11... Si layer doped with impurities, 12... -G source/drain layer, 1
3--81 layers added with impurities.

Claims (4)

[Claims] (1) An epitaxial layer made of germanium is formed on a silicon substrate, a gate insulating film is formed thereon, a source region, a drain region, and a channel region are formed in at least the epitaxial layer made of germanium, and a region including the channel region is formed. A semiconductor device comprising an insulated gate field effect transistor in which a gate electrode is formed on the gate insulating film. (2) An epitaxial layer made of high-resistance germanium into which impurities are introduced at a low concentration on a silicon substrate whose resistance has been reduced by introducing impurities at a high concentration into at least the surface, and a gate insulating film formed thereon; a source region in the epitaxial layer made of high-resistance germanium;
1. A semiconductor device comprising an insulated gate field effect transistor in which a drain region and a channel region are formed, and a gate electrode is formed on the gate insulating film on a region including the channel region. (3) A step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the germanium layer, and ion implantation of impurities using the gate electrode as a mask. and a heat treatment at a temperature where only the impurities implanted into the germanium layer in the ion implantation step are electrically activated and the impurities implanted into the silicon crystal substrate are not electrically activated. A method for manufacturing a semiconductor device, comprising the step of electrically activating only impurities implanted into the layer to form a source region and a drain region of the insulated gate field effect transistor. (4) A step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the germanium layer, and a step of diffusing impurities using the gate electrode as a mask. . A method of manufacturing a semiconductor device, comprising: forming a source region and a drain region of the insulated gate field effect transistor only in the germanium layer.