JPS63122177A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS63122177A
JPS63122177A JP26674586A JP26674586A JPS63122177A JP S63122177 A JPS63122177 A JP S63122177A JP 26674586 A JP26674586 A JP 26674586A JP 26674586 A JP26674586 A JP 26674586A JP S63122177 A JPS63122177 A JP S63122177A
Authority
JP
Japan
Prior art keywords
layer
channel
insulating film
region
germanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26674586A
Other languages
Japanese (ja)
Inventor
Tsuneo Takahashi
庸夫 高橋
Hitoshi Ishii
仁 石井
Kiyohisa Fujinaga
藤永 清久
Kazuhide Kiuchi
木内 一秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP26674586A priority Critical patent/JPS63122177A/en
Publication of JPS63122177A publication Critical patent/JPS63122177A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To realize high-speed operation by a method wherein a Ge film whose mobility of an electron and a hole is bigger than that of Si is formed on an Si substrate and this Ge is used as a channel for a MOS-type transistor. CONSTITUTION:A Ge layer 6 is formed in a region which is located just under a gate electrode 4 and a gate insulating film 3 and is transformed into a channel. In addition, a source and a drain are constructed by a germanium layer 7 and an Si layer 8 doped with an impurity to give a p-type or an n-type. Because the mobility of germanium is by about two times bigger for an electron and by about 4.5 times bigger for a hole than that of Si, a MOS-type transistor, of the identical size, constructed by the Ge can operate by two times faster for an n-channel and by 4.5 times faster for a p-channel than in the case of the Si. As compared with the MOS-type transistor constructed by the Si, the characteristic of the p-channel is improved remarkably and is nearly equal to that of the n-channel; it is possible to greatly improve the characteristic of an integrated circuit of the CMOS structure.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高速動作が可能なMO8型トランジスタ等の
半導体装置とその製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device such as an MO8 type transistor capable of high-speed operation and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

従来S1のMO8型トランジスタは、第5図に示す様に
、81基板1に、素子分離用絶縁膜2でかこまれた領域
を形成し、その領域内にゲート絶縁膜3とゲート電極4
、さらにソース・ドレイン層5を形成した構成となりて
いる。このMO8型トランジスタの電流が流れる領域は
ソースとドレインではさまれた、ゲート絶縁b43o直
下である。従来のMO8型トランジスタでは、このチャ
ネルは基板Stトナル、stハ、IE子移動jiハ、1
500 m27Va@eト比較的大きいが、正孔の移動
度は450 cm2/Va e cとかなシ小さい。す
なわち、同じ寸法で構成したnチャネル51MO8型ト
ランジスタとpチャネNSIMOB型トランジスタの特
性を比較すると、pチャネルの方が動作速度がかなシ遅
いことになる。
As shown in FIG. 5, the conventional MO8 transistor of S1 has a region surrounded by an element isolation insulating film 2 on an 81 substrate 1, and a gate insulating film 3 and a gate electrode 4 are formed in the region.
, and further has a source/drain layer 5 formed therein. The region where current flows in this MO8 type transistor is directly under the gate insulation b43o, which is sandwiched between the source and drain. In a conventional MO8 type transistor, this channel is connected to the substrate St, st, IE, ji, 1
500 m27 Va@e is relatively large, but the hole mobility is only 450 cm2/Va e c. That is, when comparing the characteristics of an n-channel 51MO8 type transistor and a p-channel NSIMOB type transistor configured with the same dimensions, the operating speed of the p-channel is considerably slower.

さらに、従来のMOB型ト2ンジスタの形成プロセスで
は、ソース・ドレインは、As、PやBなどのn型ある
いはp型を与える不純物をイオン注入する方法が用いら
れる。この様にして形成されたソース・ドレイン層は、
その深さを浅くするのが難かしいユ。特に、pチャネル
MO8型トランジスタのソース・ドレイン層に用いられ
るBは、81中の拡散係数が大きく、ソース・ドレイン
深嘔が深くなる。この様に、ドレイン層が深いと、再現
性の良い良好な動作特性を示す。チャネル長の短い微細
なMO8型トランジスタを装作するのが難かしいという
問題があった(たとえばJ、R,Br・ws 。
Furthermore, in the conventional MOB transistor formation process, the source/drain is formed by ion-implanting impurities that give n-type or p-type, such as As, P, or B. The source/drain layer formed in this way is
It is difficult to make the depth shallower. In particular, B used for the source/drain layer of a p-channel MO8 type transistor has a large diffusion coefficient in 81, and the source/drain depth becomes deep. As described above, when the drain layer is deep, good operating characteristics with good reproducibility are exhibited. There was a problem in that it was difficult to fabricate a small MO8 type transistor with a short channel length (for example, J, R, Br.ws).

”Phyalcm  of  MOS  Transl
stor’、in D、Kahng、ED、。
”Phyalcm of MOS Transl.
stor', in D., Kahng, ED.

Appl、5olid 5tat@5cience、S
upplem@nt 2A 。
Appl, 5olid 5tat@5science, S
upplem@nt 2A.

Accad@mic Press、NewYork、 
1981年)。これは、主に、ソース・ドレイン深さが
深い、チャネル長の短いMO8型トランジスタでは、第
5図のソースとドレイン間で、ゲート酸化膜からはなれ
た、81基板中を、ゲート電m′it位で制御できない
電流が流れてしまうこと(パンチスルー効果)によりて
起こる。この電流を減少させるためには、Sl基板中の
不純物濃度を高くすれば良いが、逆に、不純物濃度を高
くすると、電子あるいは正孔の移動度が低下する。ある
いはMO8型トランジスタの闇値電圧が高<逐る等の問
題が生じ、 MOS ffi )ランジスタの特性が悪
くなる。
Accad@mic Press, New York,
(1981). This is mainly due to the gate voltage m'it in the 81 substrate separated from the gate oxide film between the source and drain in FIG. This is caused by the flow of current that cannot be controlled at certain points (punch-through effect). In order to reduce this current, it is sufficient to increase the impurity concentration in the Sl substrate, but conversely, when the impurity concentration is increased, the mobility of electrons or holes decreases. Alternatively, problems such as the dark value voltage of the MO8 type transistor becoming too high may occur, and the characteristics of the MOS transistor may deteriorate.

以上の様な、微細なMO8型トランジスタの特性の悪化
は、pチャネルMO8の場合に顕著であるので、特に、
 LSIを、0MO8構成とした場合に、動作特性が、
特性の悪いpチャネルMO8型トランジスタの特性によ
りて決まってしまうことになる。
The deterioration of the characteristics of the fine MO8 type transistor as described above is remarkable in the case of p-channel MO8, so in particular,
When the LSI has a 0MO8 configuration, the operating characteristics are:
This is determined by the characteristics of the p-channel MO8 type transistor, which has poor characteristics.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明は81のMO8型トランジスタにおいて、正孔移
動度が小さいことおよび短いチャネル長のMO8型トラ
ンジスタの特性が悪化することの2点を解決した。MO
8型トランジスタ構造の半導体装置とその製造方法を提
供することを目的とする。
The present invention solves two problems in the MO8 type transistor of No. 81: the hole mobility is low and the characteristics of the MO8 type transistor with a short channel length are deteriorated. M.O.
An object of the present invention is to provide a semiconductor device having an 8-type transistor structure and a method for manufacturing the same.

〔問題点を解決するための手段と作用〕本発明は、シリ
コン基板上にゲルマニウムからなるエピタキシャル層と
その上にゲート絶縁膜が形成され、少なくとも前記ダル
マニウムからなるエピタキシャル層にソース領域、ドレ
イン領域及びチャネル領域が形成され、前記チャネル領
域を含む領域上の前記ゲート絶縁膜上にゲート電極が形
成されてなる絶縁ゲート型電界効果トランジスタを有す
ることを特徴とするものであシ、また、少なくとも表面
に高濃度に不純物が導入されて低−抵抗化されたシリコ
ン基板上に低濃度に不純物が導入された高抵抗ゲルマニ
ウムからなるエピタキシャル層とその上にゲート絶縁膜
が形成され、少なくとも前記高抵抗ゲルマニウムからな
るエピタキシャル層にソース領域、ドレイン領域及びチ
ャネル領域が形成され、前記チャネル領域を含む領域上
の前記ゲート絶縁膜上にゲート電極が形成されてなる絶
縁ゲート型電界効果トランジスタを有することを特徴と
するものであシ、更に、シリコン結晶基板上にゲルマニ
ウム層をエピタキシャル成長させる工程と、前記ダルマ
ニウム層上に絶縁ゲート型電界効果トランジスタのゲー
ト絶縁膜及びゲート電極を形成する工程と、前記ゲート
電極をマスクとして不純物をイオン注入する工程と、前
記イオン注入工程によシ前記rA/マニウム層中に注入
された不純物のみが電気的区活性化され前記シリ;ン結
晶基板中に注入された不純物は電気的に活性化されない
温度で熱処理し、前記ゲルマニウム層中に注入された不
純物のみを電気的に活性化して前記絶縁ゲート製電界効
果トランジスタのソース領域及びドレイン領域を形成す
る工程を含むことを特徴とするものであシ、また、シリ
コン結晶基板上にゲルマニウム層をエピタキシャル成長
させる工程と、前記ダルマニウム層上に絶縁ゲート型電
界効果トランジスタのゲート絶縁膜及びゲート電極を形
成する工程と、前記ゲート電極をマスクとして不純物を
拡散させ、前記ゲルマニウム層のみに前記絶縁y−トm
電界効果トランジスタのソース領域とドレイン領域を形
成する工程とを含むことを特徴とするものである。した
がりて、本発明は、Stと比べて電子および正孔の移動
度が高いG@膜をSt基板上に形成し、このG・をMO
8型トランジスタのチャネルとして用いることを主要な
特徴としている。従来の51MO8型トランジスタ講造
O様に81をチャネルに用いた技術とは異なる。以上の
様に、81基板上に形成したGoをチャネルとしたpチ
ャネルおよびnチャネルのMO8型トランジスタを形成
すれば、G・の正孔および電子の移動度が高いために、
高速動作の可能なトランジスタとなる。
[Means and effects for solving the problems] The present invention comprises an epitaxial layer made of germanium on a silicon substrate and a gate insulating film formed thereon, and at least a source region and a drain region in the epitaxial layer made of damanium. and a channel region are formed, and a gate electrode is formed on the gate insulating film on the region including the channel region. An epitaxial layer made of high-resistance germanium doped with impurities at a low concentration is formed on a silicon substrate which has been made low in resistance by doping impurities at a high concentration, and a gate insulating film is formed thereon. A source region, a drain region, and a channel region are formed in an epitaxial layer consisting of an insulated gate field effect transistor, and a gate electrode is formed on the gate insulating film on the region including the channel region. The method further includes a step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the dalmanium layer, and a step of forming the gate electrode. A step of ion-implanting an impurity as a mask and an ion-implanting step in which only the impurity implanted into the rA/manium layer is electrically activated, and the impurity implanted into the silicon crystal substrate is electrically activated. The method further comprises a step of performing heat treatment at a temperature at which the germanium layer is not electrically activated and electrically activating only the impurity implanted into the germanium layer to form the source region and drain region of the insulated gate field effect transistor. The method also includes a step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the dalmanium layer, and a step of forming the gate electrode. The impurity is diffused as a mask, and the insulating layer is diffused only into the germanium layer.
The method is characterized in that it includes a step of forming a source region and a drain region of a field effect transistor. Therefore, the present invention forms a G@ film with higher electron and hole mobility than St on a St substrate, and converts this G into MO
Its main feature is that it can be used as a channel for an 8-type transistor. This is different from the conventional 51 MO8 type transistor technology, which uses 81 for the channel as shown in Kozo O's. As described above, if p-channel and n-channel MO8 type transistors with Go channels formed on the 81 substrate are formed, the mobility of G holes and electrons is high;
This results in a transistor capable of high-speed operation.

〔実施例〕〔Example〕

(実施例1) 第1図は、本発明の第一の実施例を説明する図でちって
、ゲート電極4、ゲート絶縁膜3の直下のチャネルとな
る領域には、G・層6が形成しである。嘔らに、ソース
・ドレインとして、p型あるいはn型を与える不純物を
添加したゲルマニウム層7とS1層8を有する構成をと
る。rルマニクムはSlに比べ移動度が、電子で約2倍
、正孔で約4.5倍大きいので、同一の寸法のMOS 
匿)ランジスタを構成した場合にnチャネルで2倍、p
チャネルで4.5倍高速な動作をする。SlのMO8型
トランジスタと比べて、pチャネルの特性が大きく改善
されて、nチャネルの特性に近づくので、CMOB構成
の集積回路の特性を大きく改善できる。
(Example 1) FIG. 1 is a diagram explaining the first example of the present invention, in which a G layer 6 is formed in a region directly under the gate electrode 4 and gate insulating film 3 that will become a channel. It is. In addition, the structure includes a germanium layer 7 and an S1 layer 8 doped with impurities that provide p-type or n-type conductivity as the source and drain. The mobility of r.rumanicum is about twice as large for electrons and about 4.5 times for holes as compared to Sl, so it can be used in MOS with the same dimensions.
(double) for n-channel, p when composing a transistor
Operates 4.5 times faster in channels. Compared to an MO8-type Sl transistor, the p-channel characteristics are greatly improved and approach n-channel characteristics, so the characteristics of an integrated circuit with a CMOB configuration can be greatly improved.

次に第1図の実施例を形成する工程について説明する。Next, the steps for forming the embodiment shown in FIG. 1 will be explained.

従来のMO8型トランジスタの形成工程と同様にして、
素子分離用絶縁膜2に囲こまれた、トランジスタ形成領
域を作る(第2図(a))。次に、その上にG・層6を
エピタキシャル成長させる。この二−タキシャル成長の
方法としては、公知のMBE法あ羞いはCVD法によれ
ば良い。特に、G@H4ガスを反応ガスとしたCVD法
を用いれはS1上にのみ選択的にエピタキシャル成長で
きる(第2図(b))。
In the same manner as the conventional MO8 type transistor formation process,
A transistor formation region surrounded by the element isolation insulating film 2 is created (FIG. 2(a)). Next, a G layer 6 is epitaxially grown thereon. As a method for this bi-taxial growth, a known MBE method or CVD method may be used. In particular, by using the CVD method using G@H4 gas as a reaction gas, epitaxial growth can be selectively performed only on S1 (FIG. 2(b)).

さらに、この成長温度は、300℃程度の低温まで下げ
ることができる。次に、G・エピタキシャル膜上に、ゲ
ート絶縁膜3を形成する(第2図(C):ここではGe
層層上上のみゲート絶縁膜が形成されているが、素子分
離領域上をも覆りて形成してありても良いことは言うま
でもない)。次に、ゲート電極4を形成しく第2図(d
) )、それをマスクとして、n型あるいはp型を与え
る不純物をイオン注入した後、公知の活性化の熱処理を
行えば良い(第2図(、) )。
Furthermore, this growth temperature can be lowered to as low as 300°C. Next, a gate insulating film 3 is formed on the G epitaxial film (FIG. 2(C): here, the Ge
Although the gate insulating film is formed only on the layer, it goes without saying that it may be formed covering the element isolation region as well.) Next, the gate electrode 4 is formed as shown in FIG.
)) Using this as a mask, an impurity giving n-type or p-type is ion-implanted, and then a known activation heat treatment can be performed (FIG. 2(, )).

ところで、 G@膜のエピタキシャル成長温度は容易に
低温化(300℃〜700℃)できるので、G・膜形成
中に、下地S1からの不純物の拡散をほとんど生じない
様にできる。すなわち、下地Sl層の不純物濃度と独立
にG・層の不純物錆度を決定できることになる。この形
成法の特徴を用いると次の−様な構造の形成が可能とな
る。第2図(a)の工程の際に基板81層の少なくとも
表面付近に高濃度のn型あるいはpmを与える不純物を
ドーピングしておく。次に第2図(b)の工程でs G
@mをエピタキシャル成長させる際、あるいは成長させ
た後に、低濃度の不純物をドーピングする(不純物製置
は、MO8型トランジスタの閾値に影響するので、rA
値を考慮して選ぶ必要がある。また、不純物のドーピン
クは、G・膜形成後G・表面からの拡散やイオン注入で
行りても、G・中の不純物の電気的活性化処理の温度あ
るいは拡散温度がSi中の不純物の拡散温度より低いの
で、十分可能である)。この後、第2図で説明した工程
を続けて行けば、基板81層の不純物濃度を高濃度に、
チャネルとなるG・層6の領域の不純物濃度を低濃度に
できる。この構造では、チャネル長(G・層6のソース
・ドレイン方向への幅)に対して、G・層6の厚さを十
分浅くしておけば、G・層内での、前記従来技術で説明
し九ノ母ンチスルー効果は押えられる。さらに、00層
の下の81層は高濃度であるので、Si層でのノ9ルチ
スルーも生じない。すなわち、チャネル領域の不純物湿
度を低く押えたiま、ノ々ンチスルーを押えることがで
きることになる。チャネルG・領域では不純物濃度が低
いために、電子あるいは正孔の移動度は高くなるので、
高速動作が可能になる。
Incidentally, since the epitaxial growth temperature of the G@ film can be easily lowered (300 DEG C. to 700 DEG C.), diffusion of impurities from the base S1 can be prevented from occurring during the formation of the G@ film. In other words, the impurity rust degree of the G layer can be determined independently of the impurity concentration of the underlying Sl layer. By using the characteristics of this formation method, it is possible to form the following structures. At the time of the step shown in FIG. 2(a), at least near the surface of the substrate 81 layer is doped with an impurity that provides a high concentration of n-type or pm. Next, in the process shown in Fig. 2(b), s G
When or after the epitaxial growth of @m, a low concentration of impurity is doped (the impurity placement affects the threshold of the MO8 type transistor, so
It is necessary to consider the value when choosing. In addition, doping of impurities can be done by diffusion from the surface of G after film formation or by ion implantation. temperature, so it is quite possible). After this, by continuing the steps explained in FIG. 2, the impurity concentration of the substrate 81 layer will be increased to a high concentration.
The impurity concentration in the region of the G layer 6 that becomes the channel can be made low. In this structure, if the thickness of the G layer 6 is made sufficiently shallow with respect to the channel length (the width of the G layer 6 in the source/drain direction), As explained, the nine-mother anti-through effect can be suppressed. Furthermore, since the 81 layer below the 00 layer has a high concentration, no 9 ruti-through occurs in the Si layer. In other words, by keeping the impurity humidity in the channel region low, it is possible to suppress the throughput. In the channel G region, the impurity concentration is low, so the mobility of electrons or holes is high.
High-speed operation becomes possible.

(実施例2) 前記実施例1において、第2図(・)の拡散層形成を、
表面から、n型あるいはp型を与える不純物を拡散させ
て行うと、はとんどの元素は、その拡散係数がGa中よ
pSi中の方がはるかに小さいので、G・中のみに拡散
させることができる。したがりて、第3図に示す様な、
はとんどG@層内に拡散層を留めた構造が実現できる。
(Example 2) In Example 1, the formation of the diffusion layer shown in FIG.
When diffusing an impurity that gives n-type or p-type from the surface, the diffusion coefficient of most elements is much smaller in pSi than in Ga, so it is best to diffuse only into G. I can do it. Therefore, as shown in Figure 3,
It is possible to realize a structure in which the diffusion layer is mostly confined within the G@ layer.

06層の厚さをチャネル長よシ十分薄くしておけば、浅
い拡散層が形成できる。
If the thickness of the 06 layer is made sufficiently thinner than the channel length, a shallow diffusion layer can be formed.

(実施例3) 前記実施例1において、第3図(・)における拡散層形
成を、不純物をイオン注入する方法で行りた後に、40
0℃〜700℃程度の温度で熱処理し、活性化すると、
Ge中の不純物のみ電気的に活性化し、S1中の不純物
は活性化しない。したがって、実効的に浅い拡散層が形
成できる。
(Example 3) In Example 1, after forming the diffusion layer in FIG. 3(-) by ion-implanting impurities,
When activated by heat treatment at a temperature of about 0°C to 700°C,
Only the impurities in Ge are electrically activated, and the impurities in S1 are not activated. Therefore, an effectively shallow diffusion layer can be formed.

また、不純物のイオン注入の際に、イオン注入の加速エ
ネルギーおよびドース量を調整し、少なくともSi層の
格子を乱だし、アモルファスに近い状態にしておき、そ
の後に、600℃程度以下で熱処理し、G・層のみ結晶
性を回復させ、イオン注入されたSi層をアモルファス
のまま保つ。(ζこで、不純物の種類によりては、81
層が十分、アモルファスになるまでイオン注入すると、
G・膜中の不純物の固溶限界を越えてしまうこともちシ
うる。
In addition, when implanting impurity ions, the acceleration energy and dose of ion implantation are adjusted to at least disturb the lattice of the Si layer to make it nearly amorphous, and then heat treatment is performed at about 600 ° C. or less, Only the G layer recovers crystallinity, and the ion-implanted Si layer remains amorphous. (ζHere, depending on the type of impurity, 81
When ions are implanted until the layer becomes sufficiently amorphous,
G. It is possible that the solid solubility limit of impurities in the film may be exceeded.

その際には、不純物と共に、G・あるいはSlをイオン
注入してトータルのドース量を増やせば十分である。さ
らに、G@A1界面付近の81層が一部結晶性を回復す
る可能性があるが−1この厚さは十分薄いので問題では
ない。)この様な構成とすると81層にイオン注入され
たアモルファス領域(第1図の8に対応する)が高抵抗
層となる。したがりて、ソース・ドレイン層が高抵抗層
上にある構造となるので、ソース・ドレインの接合容量
を゛低減できる。さらに、下地S1基板のG・層に近い
領域の不純物濃度を比較的高くしておけば、パンチスル
ーも生じない。すなわち、高不純物濃度の低抵抗基板を
用いて、なお且つ接合容量のきわめで小さく、チャネル
領域での不純物による移kh度低下の少ないMOS f
fi )2′ンゾスタが構成できることになる。
In that case, it is sufficient to ion-implant G or Sl together with impurities to increase the total dose. Furthermore, there is a possibility that the 81 layer near the G@A1 interface partially recovers its crystallinity, but -1 this is not a problem because this thickness is sufficiently thin. ) With such a structure, the amorphous region (corresponding to 8 in FIG. 1) ion-implanted into layer 81 becomes a high-resistance layer. Therefore, since the structure is such that the source/drain layer is located on the high resistance layer, the junction capacitance of the source/drain can be reduced. Furthermore, if the impurity concentration in the region of the base S1 substrate close to the G layer is made relatively high, punch-through will not occur. In other words, a MOS f using a low-resistance substrate with a high impurity concentration, an extremely small junction capacitance, and a small decrease in kh degree due to impurities in the channel region.
fi ) 2' inzostar can be constructed.

(実施例4) 通常0810MO8型トランジスタでは、ゲート絶縁膜
として、基板S1を熱酸化して形成した5in2を用い
る場合が多い。本発明によるMO8型トランジスタにお
いて、 5to2をゲート絶縁膜として用いるためには
、G・層上にStをエピタキシャル成長てせ、こ゛れを
熱酸化する方法がある。この方法を用いた、本発明によ
るMO8型トランジスタの形成工程を嬉4図に示す。8
1基板1上に形成したGo層層上上81層9をエピタキ
シャル成長させる(第4図(a))。
(Example 4) In a typical 0810MO8 type transistor, a 5in2 film formed by thermally oxidizing the substrate S1 is often used as the gate insulating film. In order to use 5to2 as a gate insulating film in the MO8 type transistor according to the present invention, there is a method of epitaxially growing St on the G layer and thermally oxidizing it. A process for forming an MO8 type transistor according to the present invention using this method is shown in Figure 4. 8
1. An upper 81 layer 9 is epitaxially grown on the Go layer formed on the substrate 1 (FIG. 4(a)).

Go表面の自然酸化膜は、約400’C以上に加熱する
とG・0として昇化するので、容易に清浄なG・表面を
出すことができる。この後に、公知のSiH4等の81
を構成元素とするガスを用いたCVD法やSiMBE−
法等によりて、Ge上に容易にStをエピタキシャル成
長させることができる。次に、この表−のSlを熱酸化
し、5to2層10を形成する(第4図(b))。
Since the natural oxide film on the Go surface is elevated as G.0 when heated above about 400'C, a clean G.surface can be easily obtained. After this, 81 of known SiH4 etc.
CVD method and SiMBE-
St can be easily epitaxially grown on Ge by a method such as a method. Next, the Sl on this table is thermally oxidized to form a 5to2 layer 10 (FIG. 4(b)).

この8102層形成の大めのpA酸化温度は、約850
℃以下にすれば、GI層とSi層の界面におけるGa−
31の相互拡散は押えられる。次に、ゲート−極4を形
成しく第4図(、) ) 、次いで、イオン注入によシ
、ソース・ドレイン層12を形成すれば(第4図(d)
 )、本発明によるMO5型トランジスタが形成できる
The larger pA oxidation temperature for this 8102 layer formation is approximately 850
If the temperature is below ℃, Ga-
31 interdiffusion is suppressed. Next, the gate electrode 4 is formed (Fig. 4(, )), and then the source/drain layer 12 is formed by ion implantation (Fig. 4(d)).
), an MO5 type transistor according to the present invention can be formed.

ここで、表面の810熱酸化による8102形成の隙に
、5102層10とG・層σの間vcst層9を残すこ
とになるがとの′厚さが薄ければ、この81層も実効的
にr−ト絶縁膜として動作すると考えられるので問題は
ない。ソース・ドレインを表面からの拡散によりて形成
する場合は、ソース・ドレインとなる領域上の8102
層10と81層11を除去した後に行えば良い。
Here, a vcst layer 9 is left between the 5102 layer 10 and the G/layer σ in the gap formed by 8102 formed by thermal oxidation of 810 on the surface. There is no problem since it is considered that it operates as an r-to insulating film. When forming the source/drain by diffusion from the surface, the 8102
This may be performed after removing layers 10 and 81 and layer 11.

(実施例5) もう一つの安定なゲート絶縁膜の形成方法について述べ
る。たとえばGe層をGeH4等のG・を構成元素とし
たガスを用いたCVD法によりてエピタキシャル成長さ
せる場合は、Ge層の成長を行りた直後に、Ge膜を大
気にさらさずに、CVD法によって次のゲート絶縁膜を
形成すれば、絶縁膜とG・の界面の汚染が少ない。すな
わち、絶縁膜とG・界面にできる界面準位の密度を少な
くできることになる。
(Example 5) Another method for forming a stable gate insulating film will be described. For example, when growing a Ge layer epitaxially by CVD using a gas containing G as a constituent element, such as GeH4, immediately after growing the Ge layer, do not expose the Ge film to the atmosphere and grow it by CVD. If the next gate insulating film is formed, there will be less contamination at the interface between the insulating film and G. In other words, the density of interface states formed at the insulating film and the G interface can be reduced.

たとえば5102をゲート絶縁膜とする場合は以下の様
な工程を用いれば十分である。第2図(b)の工程で、
G・をたとえばGeH4ガスを用いたCVD法によって
形成する。次に、G・H4ガスの導入を停止し、引き続
いてたとえばSiH4あるいはs t 2H6ガスとた
とえば02.りるいはN20等の酸化性ガスを導入し8
102層を形成すれば界面準位密度の低いGe/5i0
2界面ができる。また、上記工程で、 GeH4ガスを
停止した直後に、5IH4,ガスのみを導入し、時間を
置いて02等の酸化性ガスを導入すれば、G・A−i、
/S i O2のイ4造ができる。G・のCVDによる
エピタキシャル成長温度は300℃〜600′c5度に
できるので、この温度で、G・H4ガスの導入を停止し
て、 SiH4ガスを導入した場合、Siの堆積速度は
、数!1即分以下にできる。したがりて、 Ge7B 
i/S i 02橋造の中間の31層の厚さを0.1 
t+m−数nm程度に薄く制御するのは容易であり、 
MO8型トランジスタを構成した場合にG・を主たるチ
ャネル領域にすることができる。
For example, when 5102 is used as a gate insulating film, it is sufficient to use the following process. In the process shown in Figure 2(b),
G. is formed by, for example, a CVD method using GeH4 gas. Next, the introduction of G.H4 gas is stopped, followed by, for example, SiH4 or s t 2H6 gas and, for example, 02. Rirui introduces an oxidizing gas such as N208
If 102 layers are formed, Ge/5i0 with low interface state density
2 interfaces are formed. In addition, in the above process, if only 5IH4 gas is introduced immediately after stopping the GeH4 gas, and an oxidizing gas such as 02 is introduced after a while, G・A-i,
/S i O2 can be constructed. The epitaxial growth temperature of G by CVD can be 300°C to 600'c5, so if the introduction of G and H4 gas is stopped at this temperature and SiH4 gas is introduced, the deposition rate of Si will be several times higher than that of the previous one. Can be done in less than 1 minute. Therefore, Ge7B
i/S i 02 The thickness of the middle 31 layers of the bridge structure is 0.1
It is easy to control the thickness to about t + m - several nm,
When forming an MO8 type transistor, G can be used as the main channel region.

すなわち、Slと比べて移動度が大きいGaをチャネル
となるので、 MO8型トランジスタの特性が向上する
ことになる。
That is, since Ga, which has a higher mobility than Sl, serves as a channel, the characteristics of the MO8 type transistor are improved.

(実施例6) G・層中へのイオン注入によるソース・ドレイン形成に
必要な熱処理温度は500℃〜700℃程度と低いので
、ゲート絶縁膜として、Ta 205等の耐熱性が多少
とぼしい絶縁膜を用いることもできる。
(Example 6) Since the heat treatment temperature required for forming the source/drain by ion implantation into the G layer is as low as about 500°C to 700°C, an insulating film with somewhat poor heat resistance such as Ta 205 can be used as the gate insulating film. You can also use

同じ理由で、ゲート金属としても、低融点あるいは耐熱
性の多少とぼしい金属あるいは金属シリ−サイド等の金
属性化合物をも用いることができる。
For the same reason, a metal with a low melting point or somewhat poor heat resistance, or a metallic compound such as metal silicide can also be used as the gate metal.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、81基板上に形成したG・をチャネ
ルとしたpチャネルおよびnチャネルのMO8型トラン
ジスタを形成すれば、G・の正孔および電子の移動度が
高いために、高速動作の可能なトランジスタとなるとい
う利点がある。
As explained above, if p-channel and n-channel MO8 type transistors with G as a channel formed on an 81 substrate are formed, high-speed operation is possible due to the high mobility of holes and electrons in G. This has the advantage of being a possible transistor.

S1上へのGoのエピタキシャル成長は、800℃以下
で可能であるので、基板S1からG@エビタΦシャル成
長膜への不純物の混入はほとんどないため、基板S1の
不純物を高濃度にし、その上に低濃度のGe層をエピタ
キシャル成長できる。これをチャネルとすれば、チャネ
ル領域は、低不純物濃度が低いため高移動度のtま、ノ
クンチスルーを押えることができる。したがって、高速
動作の微細なMO8型トランジスタができるという利点
がある。
Since the epitaxial growth of Go on S1 is possible at temperatures below 800°C, there is almost no contamination of impurities from the substrate S1 into the G@epitaxially grown film. A low concentration Ge layer can be epitaxially grown. If this is used as a channel, the channel region has a low impurity concentration and can suppress knock-through even when the mobility is high. Therefore, there is an advantage that a fine MO8 type transistor that operates at high speed can be produced.

さらに、Ge中での不純物・拡散が生じる温度が81よ
シかなシ低いこと、あるいは、Ge中にイオン注入した
不純物の活性化温度が81よシ著しく低いことを利用す
れば、ソース・ドレインの深さをG・層の厚さで止める
ことができる。したがりて、G。
Furthermore, if we take advantage of the fact that the temperature at which impurities and diffusion occur in Ge is 81°C lower, or that the activation temperature of impurities ion-implanted into Ge is significantly lower than 81°C, it is possible to The depth can be stopped at G/layer thickness. Therefore, G.

層厚を薄くすれば、浅い拡散層が形成できるので、公知
の短チヤネル効果を低減できるので前記の微細なMO8
型トランジスタの動作特性の安定性、再現性を向上させ
ることができるという利点があるJさらに、加えて、イ
オン注入でソース・ドレインを形成する場合に、イオン
注入後のG・の結晶格子の回復がSlよシ200℃〜3
00℃程度低い温度で生じることを利用し、Geのソー
スもドレインの下部をソース・ドレイン形成のイオン注
入の際にアモルファス化し、Ge層のみ結晶化すれば、
ソース・ドレインを高抵抗のアモルファスSi上に形成
した構造にできる。したがって、高い不純物娘度のSt
基板上にG・をチャネルとしたMO8型トランジスタを
形成しても、G・のソース・ドレインと基板81間の接
合容量を小嘔くできるという利点がある。すなわち、よ
シー層の高速動作をする集積回路が構成できる。
By reducing the layer thickness, a shallow diffusion layer can be formed and the known short channel effect can be reduced.
In addition, when forming sources and drains by ion implantation, recovery of the G crystal lattice after ion implantation has the advantage of improving the stability and reproducibility of the operating characteristics of J type transistors. is Sl 200℃~3
Taking advantage of the fact that it occurs at a temperature as low as 00°C, if the lower part of the Ge source and drain is made amorphous during ion implantation for source/drain formation, and only the Ge layer is crystallized,
A structure in which the source and drain are formed on high-resistance amorphous Si can be obtained. Therefore, St with high impurity daughterness
Even if an MO8 type transistor with G as a channel is formed on the substrate, there is an advantage that the junction capacitance between the source/drain of G and the substrate 81 can be reduced. In other words, it is possible to construct an integrated circuit that operates at high speed in a high-speed layer.

一方、G・層上に薄い81層を形成し、その上にゲート
絶縁膜として8102層を形成すれば良好なゲート絶縁
膜−チャネル界面が得られる。
On the other hand, if a thin 81 layer is formed on the G layer and an 8102 layer is formed thereon as a gate insulating film, a good gate insulating film-channel interface can be obtained.

また、G@層へのソース・ドレイン形成は比較的低温化
できるので、多少耐熱性のとぼしい、Ta205の様な
絶縁膜をゲート絶縁膜に、あるいは耐熱性のとぼしい金
属をゲート電極に用いることができるという利点がある
In addition, since the source/drain formation in the G@ layer can be performed at a relatively low temperature, it is possible to use an insulating film such as Ta205, which has somewhat poor heat resistance, for the gate insulating film, or a metal with poor heat resistance for the gate electrode. It has the advantage of being possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1Hは本発明によるMOa型トランジスタの断面構造
の一つの例を示す図、 第2図は本発明によるMOB型トランジスタの形成工程
の例を示す図、 第3図は不純物を表面から拡散することによりてソース
・ドレインを形成した本発明によるMO8型トランジス
タの断面構造の一例を示す図、第4図は8102をゲー
ト絶縁膜とする本発明によるMO8型トランジスタ形成
工程の例を示す図、第5図は従来のMO8型トランジス
タの断面構造を示す図である。 1・・・81基板、2・・・素子分離用絶縁膜、3・・
・ゲート絶縁膜、4・・−ゲート電極、5・・・ソース
・ドレイン層、6・・・G・層、1・・・ダルマニウム
層 Ji mmm不純物を添加されたSi層、9・・・
81層、10・・・5tO2層、11・・・不純物を添
加されたSi層、12・−G・ソース・ドレイン層、1
3−・・不純物を添加された81層。
1H is a diagram showing an example of the cross-sectional structure of the MOa type transistor according to the present invention, Figure 2 is a diagram showing an example of the formation process of the MOB type transistor according to the present invention, and Figure 3 is a diagram showing an example of the process of forming an MOB type transistor according to the present invention. FIG. 4 is a diagram showing an example of the cross-sectional structure of an MO8 type transistor according to the present invention in which the source and drain are formed using 8102 as a gate insulating film, and FIG. The figure is a diagram showing a cross-sectional structure of a conventional MO8 type transistor. 1... 81 substrate, 2... Insulating film for element isolation, 3...
- Gate insulating film, 4...-gate electrode, 5... Source/drain layer, 6... G layer, 1... Dalmanium layer Ji mmm Si layer doped with impurity, 9...
81 layer, 10... 5tO2 layer, 11... Si layer doped with impurities, 12... -G source/drain layer, 1
3--81 layers added with impurities.

Claims (4)

【特許請求の範囲】[Claims] (1)シリコン基板上にゲルマニウムからなるエピタキ
シャル層と、その上にゲート絶縁膜が形成され、少なく
とも前記ゲルマニウムからなるエピタキシャル層にソー
ス領域、ドレイン領域及びチャネル領域が形成され、前
記チャネル領域を含む領域上の前記ゲート絶縁膜上にゲ
ート電極が形成されてなる絶縁ゲート型電界効果トラン
ジスタを有することを特徴とする半導体装置。
(1) An epitaxial layer made of germanium is formed on a silicon substrate, a gate insulating film is formed thereon, a source region, a drain region, and a channel region are formed in at least the epitaxial layer made of germanium, and a region including the channel region is formed. A semiconductor device comprising an insulated gate field effect transistor in which a gate electrode is formed on the gate insulating film.
(2)少なくとも表面に高濃度に不純物が導入されて低
抵抗化されたシリコン基板上に低濃度に不純物が導入さ
れた高抵抗ゲルマニウムからなるエピタキシャル層とそ
の上にゲート絶縁膜が形成され、少なくとも前記高抵抗
ゲルマニウムからなるエピタキシャル層にソース領域、
ドレイン領域及びチャネル領域が形成され、前記チャネ
ル領域を含む領域上の前記ゲート絶縁膜上にゲート電極
が形成されてなる絶縁ゲート型電界効果トランジスタを
有することを特徴とする半導体装置。
(2) An epitaxial layer made of high-resistance germanium into which impurities are introduced at a low concentration on a silicon substrate whose resistance has been reduced by introducing impurities at a high concentration into at least the surface, and a gate insulating film formed thereon; a source region in the epitaxial layer made of high-resistance germanium;
1. A semiconductor device comprising an insulated gate field effect transistor in which a drain region and a channel region are formed, and a gate electrode is formed on the gate insulating film on a region including the channel region.
(3)シリコン結晶基板上にゲルマニウム層をエピタキ
シャル成長させる工程と、前記ゲルマニウム層上に絶縁
ゲート型電界効果トランジスタのゲート絶縁膜及びゲー
ト電極を形成する工程と、前記ゲート電極をマスクとし
て不純物をイオン注入する工程と、前記イオン注入工程
により前記ゲルマニウム層中に注入された不純物のみが
電気的に活性化され前記シリコン結晶基板中に注入され
た不純物は電気的に活性化されない温度で熱処理し、前
記ゲルマニウム層中に注入された不純物のみを電気的に
活性化して前記絶縁ゲート型電界効果トランジスタのソ
ース領域及びドレイン領域を形成する工程を含むことを
特徴とする半導体装置の製造方法。
(3) A step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the germanium layer, and ion implantation of impurities using the gate electrode as a mask. and a heat treatment at a temperature where only the impurities implanted into the germanium layer in the ion implantation step are electrically activated and the impurities implanted into the silicon crystal substrate are not electrically activated. A method for manufacturing a semiconductor device, comprising the step of electrically activating only impurities implanted into the layer to form a source region and a drain region of the insulated gate field effect transistor.
(4)シリコン結晶基板上にゲルマニウム層をエピタキ
シャル成長させる工程と、前記ゲルマニウム層上に絶縁
ゲート型電界効果トランジスタのゲート絶縁膜及びゲー
ト電極を形成する工程と、前記ゲート電極をマスクとし
て不純物を拡散させ、前記ゲルマニウム層のみに前記絶
縁ゲート型電界効果トランジスタのソース領域とドレイ
ン領域を形成する工程とを含むことを特徴とする半導体
装置の製造方法。
(4) A step of epitaxially growing a germanium layer on a silicon crystal substrate, a step of forming a gate insulating film and a gate electrode of an insulated gate field effect transistor on the germanium layer, and a step of diffusing impurities using the gate electrode as a mask. . A method of manufacturing a semiconductor device, comprising: forming a source region and a drain region of the insulated gate field effect transistor only in the germanium layer.
JP26674586A 1986-11-11 1986-11-11 Semiconductor device and its manufacture Pending JPS63122177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26674586A JPS63122177A (en) 1986-11-11 1986-11-11 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26674586A JPS63122177A (en) 1986-11-11 1986-11-11 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS63122177A true JPS63122177A (en) 1988-05-26

Family

ID=17435117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26674586A Pending JPS63122177A (en) 1986-11-11 1986-11-11 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS63122177A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03296271A (en) * 1990-04-16 1991-12-26 Nec Corp Semiconductor device and manufacture thereof
US5155571A (en) * 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
US5241197A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Transistor provided with strained germanium layer
EP0568065A2 (en) * 1992-05-01 1993-11-03 Texas Instruments Incorporated High-dielectric constant oxides on semiconductors using a Ge buffer layer
US5268324A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Modified silicon CMOS process having selectively deposited Si/SiGe FETS
JP2005210096A (en) * 2004-01-21 2005-08-04 Sharp Corp Super shallow metal oxide surface channel mos transistor
FR2868207A1 (en) * 2004-03-25 2005-09-30 Commissariat Energie Atomique FIELD EFFECT TRANSISTOR WITH SUITABLE SOURCE, DRAIN AND CHANNEL MATERIALS AND INTEGRATED CIRCUIT INCLUDING A SUCH TRANSISTOR

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151464A (en) * 1983-02-17 1984-08-29 Nec Corp Metal insulator semiconductor transistor and manufacture thereof
JPS60210877A (en) * 1984-04-04 1985-10-23 Matsushita Electric Ind Co Ltd Semiconductor device
JPS61112364A (en) * 1984-11-07 1986-05-30 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151464A (en) * 1983-02-17 1984-08-29 Nec Corp Metal insulator semiconductor transistor and manufacture thereof
JPS60210877A (en) * 1984-04-04 1985-10-23 Matsushita Electric Ind Co Ltd Semiconductor device
JPS61112364A (en) * 1984-11-07 1986-05-30 Hitachi Ltd Semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241197A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Transistor provided with strained germanium layer
JPH03296271A (en) * 1990-04-16 1991-12-26 Nec Corp Semiconductor device and manufacture thereof
US5155571A (en) * 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
EP0568065A2 (en) * 1992-05-01 1993-11-03 Texas Instruments Incorporated High-dielectric constant oxides on semiconductors using a Ge buffer layer
EP0568065A3 (en) * 1992-05-01 1994-09-14 Texas Instruments Inc High-dielectric constant oxides on semiconductors using a ge buffer layer
US5268324A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Modified silicon CMOS process having selectively deposited Si/SiGe FETS
JP2005210096A (en) * 2004-01-21 2005-08-04 Sharp Corp Super shallow metal oxide surface channel mos transistor
FR2868207A1 (en) * 2004-03-25 2005-09-30 Commissariat Energie Atomique FIELD EFFECT TRANSISTOR WITH SUITABLE SOURCE, DRAIN AND CHANNEL MATERIALS AND INTEGRATED CIRCUIT INCLUDING A SUCH TRANSISTOR
WO2005093812A1 (en) * 2004-03-25 2005-10-06 Commissariat A L'energie Atomique Transistor with adapted source, drain and channel materials and integrated circuit comprising same
US7566922B2 (en) 2004-03-25 2009-07-28 Commissariat A L'energie Atomique Field effect transistor with suitable source, drain and channel materials and integrated circuit comprising same

Similar Documents

Publication Publication Date Title
US4463492A (en) Method of forming a semiconductor device on insulating substrate by selective amorphosization followed by simultaneous activation and reconversion to single crystal state
JP3229012B2 (en) Method for manufacturing semiconductor device
US7018901B1 (en) Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
KR920009745B1 (en) Manufacturing method of semiconductor
US5428234A (en) Semiconductor device
JPS6038877B2 (en) Manufacturing method for semiconductor devices
JPH05502548A (en) Microfabricated MISFET device that suppresses hot carriers
JPS63122176A (en) Semiconductor device and its manufacture
JPS63122177A (en) Semiconductor device and its manufacture
JPS5932173A (en) Manufacture of field effect transistor
JPH04225568A (en) Contact structure of semiconductor device and manufacture thereof
JP2623902B2 (en) Semiconductor device and manufacturing method thereof
JP3744895B2 (en) Manufacturing method of CMOS semiconductor device
JPH05343666A (en) Integrated circuit transistor
JPS6313378A (en) Semiconductor device and manufacture thereof
JPH11168211A (en) Semiconductor device
JPS5868979A (en) Semiconductor device
JPH0291932A (en) Manufacture of semiconductor device
JPH0645598A (en) Semiconductor device and manufacture thereof
JPH11243065A (en) Manufacture of semiconductor device and formation of conductive silicon film
JPH0517701B2 (en)
JPH04158529A (en) Fabrication of semiconductor element
KR100733605B1 (en) Method for manufacturing schotkky?barrier transistor
JP3008579B2 (en) Method for manufacturing semiconductor device
JPH04303963A (en) Semiconductor device