JPH06204879A - D/a converter - Google Patents

Abstract

PURPOSE:To provide a D/A converter for improving linearity and resolution. CONSTITUTION:The binary data Din to be converted of (m) bits are divided into optional high-order (q) bits and remaining low-order (h) bits and (2<m>-1) pieces of transistors to be equivalent load current sources are arranged in the matrix of (2<g>-1) rows and (2<h>+1) columns. Further, the respective currents of (2<g>-1) pieces of the transistors arranged at the center column of (2<h>+1) columns are switched by the decoded data of the binary data to be converted of the low-order (h) bits and the currents of the transistor group of the respective rows except for the transistor group positioned at the center column are switched by the decoded data of the binary data to be converted of the high- order (g) bits. Thus, D/A conversion is performed by making a total current IS corresponding to the binary data Din to be converted flow to a current addition point P.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter,
In particular, it is equipped with a plurality of equal-load current sources, and the digital input data is used to control whether each constant current flowing from these equal-load current sources is sent to the ground side or to the current addition point. The present invention relates to a D / A converter of a type that generates an analog signal corresponding to data at a current addition point.

[0002]

2. Description of the Related Art Conventionally, such a D / A converter is shown in FIG.
The configuration is as shown in. That is, a plurality of n transistors T _{0 to} T _n-1 each having the same size are connected to the reference transistor T _RF connected to the constant current source 2 provided in the standard bias circuit 1. A current mirror circuit is formed, and each of the transistors T _{0 to} T _n-1 serves as an equal weight current source that outputs a current equal to the reference current I ₀ of the constant current source 2.

[0003] Further, each of the transistors T ₀ ~T _n-1, the switch element x ₀ ~x _n-1 such as an analog switch is connected, these switching elements x ₀ ~x _n-1, the decoder circuit Control is performed according to the digital input data y _{0 to} y _n-1 from 3 to switch to the ground side or the current addition point P side.

Here, the decoder circuit 3 decodes the m-bit binary data D _in to be D / A converted into n-bit digital input data y _{0 to} y _n-1 corresponding to the maximum span. For example, if m = 8 bits, the number of bits of the digital input data y _{0 to} y _n−1 is 256 bits because of the relationship of n = 2 ^m , and is set so that the span from 0 to 255 can be taken. There is.

The current addition point P, to which the output sides of the switch elements x _{0 to} x _n-1 are commonly connected, is connected to a current-voltage conversion circuit 5 composed of an amplifier 4 and a resistor R, and this current-voltage conversion circuit 5 adds current. It generates an analog voltage V _o (= I _s R) corresponding to the product of the total current I _s flowing through the point P and the resistor R.

Therefore, the digital input data y _{0 to} y
Depending on the logical value of each of _n-1, when the switching element is switched to the ground side, x _i = 0 (where, 0 ≦ i ≦ n-1 ),
If x _i = 1 when switching to the current addition point P side,
The analog voltage V _o is V _o = I ₀ R (x ₀ + x ₁ + ... + x _n-1 ) ... (1), and a resolution of n = 2 ^m is obtained.

By the way, since the resolution is set in the relation of 2 ^m , in order to improve the resolution, it is necessary to increase the number n of equal load current sources and switching elements. When the D / A converter is implemented as an LSI, it is important to improve the linearity by arranging such many constituent elements on the semiconductor chip.

Conventionally, in order to improve the linearity, the constituent elements have been formed into an LSI with an arrangement as shown in FIG. Taking a D / A converter of m = 8 bits as an example, 256 equal weight current source transistors T _{0 to} T
_By grouping ₂₅₅ and switch elements x _{0 to} x ₂₅₅ into 16 groups, 16 sets of blocks L _{0 to} L ₁₅ are set, and each block L _{0 to} L ₁₅ has the same cell structure and is arranged in 16 columns. To be done. Further, the reference transistor T _RF in the standard bias circuit 1 and the transistors T _{0 to} T ₂₅₅ for equal weight current sources in the blocks L _{0 to} L ₁₅ are connected to form a current mirror circuit and a decoder circuit. digital input data y ₀ ~y ₂₅₅ from 3 are wired so as to be supplied to each switch element y ₀ ~y ₂₅₅ in the block L ₀ ~L _15, further, the output of all the switching elements x ₀ ~x ₂₅₅ It was wired to connect the current addition point P on the side to the current-voltage conversion circuit 5.

Therefore, the equal weight current source transistors T _{0 to} T ₂₅₅ are arranged and arranged in a matrix according to the layout technique, and any of the transistors T ₀ to T ₂₅₅ is formed.
T _{255 is} also said to generate a uniform equal-load current I ₀ and improve linearity.

[0010]

However, as described above, the prior art is to improve linearity geometrically by arranging transistors for equal weight current sources in a matrix, as described above, but geometrically the same. Even in the case of designing the transistor for constant load current source, all transistors for constant load current source do not have uniform and identical electric characteristics in the actual manufacturing process, and it is difficult to further improve linearity.

That is, since a large number of transistors for equal weight current sources are arranged in a matrix with a planar spread, for example, transistors T _{0 to} T ₁₅ for equal weight current sources in the block L _{0 of} FIG. In the actual manufacturing process, the transistors T _{240 to} T ₂₅₅ for constant-load current sources in the block L ₁₅ do not have completely uniform and identical electrical characteristics because of spatial misalignment. In addition, as long as a large number of transistors for constant-load current sources are formed with a two-dimensional spread, not only the non-uniformity among the blocks but also the non-uniformity within each block cannot be avoided.

As a result, as shown in FIG. 8, the conversion characteristic r is deviated from the ideal conversion characteristic r1 in which the relationship between the value of the converted binary data D _{in and} the output voltage V _o is linear.
As shown in FIG. 2, when the output currents from a certain constant-load current source transistor are current-added, the analog output voltage V _o increases, resulting in a non-linear conversion characteristic. When the output currents from the load current source transistors are summed, the analog output voltage V _o decreases, resulting in a non-linear conversion characteristic, or a combination of these increase / decrease characteristics.

The present invention has been made in view of such conventional problems, and an object thereof is to provide a D / A converter capable of improving linearity and resolution.

[0014]

In order to achieve such an object, the present invention provides m-bit converted binary data D.
_In is divided into arbitrary upper g bits and remaining lower h bits, and a matrix of (2 ^g -1) rows (2 ^h +1) columns with (2 ^m -1) transistors serving as equal weight current sources. And the individual currents of the (2 ^g -1) transistors arranged in the central column of the (2 ^h +1) column are switched by the decoded data of the lower h bits of the converted binary data. by switching the current of the transistor group of each row except the transistor group located in the middle column decode data of the converted binary data of the upper g bits, the total current I _s current summing point P corresponding to the converted binary data D _in The D / A conversion is carried out by flowing it into the air.

[0015]

According to the present invention having such a configuration, the total current I _s is determined by the respective currents from the equal-load current source group arranged in the central block which traverses in the longitudinal direction at the center of the semiconductor chip and the lateral direction of the semiconductor chip. And the respective currents of the equal-load current source group of each row arranged in the above are evenly added.
As a result, even if all the equal-load current source groups arrayed and formed in the semiconductor chip are not completely uniform in the manufacturing process, these nonuniformities are dispersed and the converted binary data D _{in is} converted. The linearity of the analog voltage V _o can be improved and the resolution can be improved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the current flowing out from a plurality of equal weight current sources realized by the current mirror circuit is switched in accordance with the converted binary data, so that the total current generated at the current addition point is detected. It is a constant-weight current type D / A converter that realizes D / A conversion by setting a proportional relationship with the conversion binary data and further converting this total current into an analog voltage. That is, as shown in FIG. 1, the basic circuit for one equal weight current source has a reference bias circuit A, an equal weight current source T, and a changeover switch circuit S. The current-voltage conversion circuit is connected in parallel to the addition point P and further converts the total current I _s generated at the current addition point P into an analog voltage V _o . All FETs described below are p-channel field effect transistors.

The reference bias circuit A includes a constant current source for generating a constant current I ₀ of a predetermined number k and a predetermined number k of p-channel field effect transistors (hereinafter referred to as FETs) q ₀ whose gates and drains are commonly connected. The FET q _{0 has} a gate and a drain connected to a constant current source, and a source connected to a power source V _DD.
It is configured to be connected to. The constant load current source T is FE
The p-channel FET q ₁ whose gate is connected to the gate of T q ₀ and whose source is connected to the power supply V _DD constitutes a current mirror circuit together with the reference bias circuit A. Here, the constant current source of the reference bias circuit A flows a current of k × I ₀ , and since the k FETs q ₀ are connected in parallel, the drain source current of the FET q ₁ becomes I ₀ .

In the switch circuit S, the source is FET q ₁
P-channel first FET q connected to the drain of
₂ and the second FET q ₃ , and further the first FET
q ₂ is and the drain is always gate biased at a constant voltage V _ref gate is grounded, a second FET q ₃
Has a gate to which digital input data d corresponding to the converted binary data D _in is input, and a drain to which the current addition point P is added.
Connected to. Then, when the logic level of the digital input data d is “H”, the second FET q ₃ is turned off, so that the current I ₀ flowing out of the FET q ₁ passes through the first FET q _2. When the logic level of the digital input data d is "L", the second FET q ₃ is turned on, and the logic level "L" causes the first FET to flow to the ground side. q ₂ is reverse biased and turned off. Therefore, when the digital input data d is logic “H”, the current I ₀ is the current addition point P.
However, the current I ₀ flows to the current addition point P when the logic is “L”, and the analog voltage V _o proportional to the converted binary data D _in is obtained.

In the D / A converter of this embodiment, the reference bias circuit A, the equal-load current source T, and the switch circuit S are all realized by a cell structure when integrated into an LSI.

Next, an overall circuit configuration to which the principle of the basic circuit is applied is shown in FIG. 2 showing a geometrical arrangement of components (arrangement corresponding to the layout technique) and a main circuit corresponding to FIG. It demonstrates based on FIG. 3 and FIG. 4 which show. In addition, m
The case where the 8-bit converted binary data D _in is converted into the analog voltage V _o in the span of 0 to 255 is shown.

First, the geometrical arrangement will be described with reference to FIG. 225 p-channel FETs that are equal-load current sources
T _{0,1 to} T _16,17 are arrayed and formed in a matrix of 17 rows and 17 columns, and these FETs T _{1,1 to} T _15,17 are all realized in a geometrically identical cell configuration and have a mutual cell structure. Are arranged so that the intervals are also equal. For the sake of explanation, it is assumed that these FETs T _{0,1 to} T _16,17 are represented by T _{i, j} (where 0 ≦ i ≦ 16 and 1 ≦ j ≦ 17) based on the arrangement of the i-th row and the j-th column. To do.

1 arranged in the central row, ie the ninth row
The gates of all five FETs T _{i, 9} (where 1 ≦ i ≦ 15) are connected in common, and all the sources are connected to a predetermined voltage source V _DD . These FET T _{i, 9}
Is called the central block.

Further, the FET T included in the center block
_{Except i, 9} (where 1 ≦ i ≦ 15), the gates of 16 FET groups arranged in each row i are commonly connected, and all sources are voltage sources V _DD It is connected to the. That is, 17 arranged in the 0th row (i = 0)
The gates of the FETs T _{0, j} are commonly connected to each other and their sources are connected to the power supply V _DD , and the other rows i =
The 17 FET groups arranged in 1 to 16 have the same connection relationship.

Furthermore, 17 arranged in the 0th row (i = 0)
Next to the FETs T _{0, j} , 17 constant current source circuits I
_{0,1 to} I _0,17 are formed, all of which have a uniform constant current I
It is set to flow ₀ . Also, line 16 (i = 1
Next to the 17 FETs T _{16, j} arranged in 6), 17
A number of constant current source circuits I _{16,1 to} I _16,17 are formed, and all of them are set so that a uniform constant current I ₀ flows.

The 17 FEs arranged in the 0th row
The T T _{0,1 to} T _0,17 and the constant current source circuits I _{0,1 to} I _0,17 are _referred to as a reference bias block A, and 17 FETs T _16,1 to 16 similarly arranged in the 16th row. The T _16,17 and the constant current source circuits I _{16,1 to} I _16,17 are referred to as a reference bias block B.

In the reference bias block A, as shown in FIG. 3, all the sources of all the FETs T _{0,1 to} T _0,17 are connected to the power source V _DD , and all the gates and the drains are common. All 17 constant current source circuits I _{0,1 connected}
To I _0,17 are commonly connected. Therefore, the reference bias block A constitutes a reference bias circuit for _supplying a constant current of 17 × I ₀ to the 17 FETs T _{0,1 to} T _0,17 connected in parallel, and further, all the FET T _0,1 ~ T
The connecting contacts Ga of all gates and drains of 0 and ₁₇ are FE
By being connected to all the gates of T T _{1,1 to} T _7,17 , the current mirrors of the first to seventh rows are constructed.

The reference bias block B, as shown in FIG. 3, all the all the source of FET T _16,1 ~T _16,17 are connected to the power supply V _DD, further, all of the gates and drains commonly All 17 constant current source circuits I connected
_{16,1 to} I _16,17 are commonly connected. Therefore, the reference bias block B constitutes the reference bias circuit for supplying the 17 × FET T _16,1 ~T _16,17 the constant current was 17 parallel connection I _0, further, all FET T
By all of the gate and drain connection contact Gb of _16,1 through T _{16, 17} are connected to all the gates of FET T _8,1 ~T _15,17, a current mirror of the eighth row to the 15th row Is configured.

Further, the connection contact Ga and the connection contact Gb are
Are connected between the 7th and 8th rows. As a result,
The current mirrors of the first to fifteenth rows are realized by cooperation with the reference bias circuits of the reference bias blocks A and B, and further two reference bias circuits of the reference bias blocks A and B are located at both ends. FET T
The gate potentials of _{1,1 to} T _15,17 are stabilized, and FET T
Drain-source current of each of _{1, 1} through T _{15, 17} is stabilized in the I _0.

In the left side region of the FET T _{i, j} arranged in a matrix, a total of 15 current switching switch circuits S _{1,9 to} S _15,9, one for each row i, are formed. The switch circuits S _{1,9 to} S _15,9 have the same cell structure geometrically and electrically. Then, the FETs T _{1,9 to} T _15,9 and the switch circuits S _{1,9 to} S in the center block are
_{15 and 9} are individually associated and connected.

Further, the FETs T arranged in matrix are
_In the right side area of _{i, j} , the individual FETs in the first to fifteenth rows are
T _{i, j} (However, FETs T _{1,9 to} T in the center block
Current switching switch circuits S _{i, j} (excluding j = 9) associated with (excluding _15,9 ) are formed in a matrix arrangement. And the first row FET T _{1, j}
And the switch circuits S _{1, j} in the first row are connected in the order of arrangement, and the remaining FETs in the second to fifteenth rows are connected.
T _{2, j to} T _{15, j} and the switch circuits S _{2, j to} S _{15, j} are also individually connected in the same relationship. It should be noted that all of these switch circuits S _{i, j} have the same cell structure geometrically and electrically as the switch circuits S _{1,9 to} S _15,9 formed in the left side region.

Further, all output contacts of all switch circuits S _{i, j} formed in the left and right regions are connected to the current addition point P shown in FIG. 1, and the total current I generated at the current addition point P is further connected.
_The current-voltage conversion circuit 6 converts _s into an analog voltage V _o and outputs it. Also, the decoder circuit 7
{B ₇ , b ₆ , b ₅ , b ₄ , b ₃ , b ₂ , b ₁ , b ₀ }
Input 8-bit converted binary data D _in and upper 4 bits {b ₇ , b ₆ , b ₅ , b ₄ } as 4-bit binary data into 15-bit digital input data β _{15 to} β ₁ . At the same time as decoding, the values of the lower 4 bits {b ₃ , b ₂ , b ₁ , b ₀ } are decoded into 15-bit digital input data α _{15 to} α ₁ . Here, the upper 4 bits {b ₇ , b ₆ , b ₅ , b ₄ } are actually 16
Although it is a value that is an integral multiple of, it is decoded as a 4-bit binary data, and thus is decoded as a value of 0 to 15.
When the upper 4 bits {b ₇ , b ₆ , b ₅ , b ₄ } are all 0, all the logics of β _{15 to} β ₁ are “H”, and {b ₇ , b ₆ , b ₅ , When the value of b ₄ } is 1, β
_{15 to} β ₂ are logic “H” and β ₁ is logic “L”, and so on, in the same manner, the upper 4 bits {b ₇ , b ₆ , b ₅ , b.
Decoding is performed such that the number of bits that become logical "L" sequentially increases from β ₁ in accordance with the value of ₄ }. In other words, the value of the upper 4 bits {b ₇ , b ₆ , b ₅ , b ₄ } is set to 1
Decoding is performed by associating with the number which becomes the logical "L" among the 5 bits β _{15 to} β ₁ .

The lower 4 bits {b ₃ , b ₂ , b ₁ , b
Similarly, the value of ₀ } is decoded in correspondence with the number of the logical "L" of 15 bits α _{15 to} α ₁ .

Further, on / off control of all the switch circuits S _{1, j} (excluding j = 9) arranged in the first row is performed according to the logic of the digital input data β ₁ , and the switch circuits S _{2 in} the second row are _{, j} (excluding j = 9) is controlled according to the logic of the digital input data β ₂ , and similarly, the switch circuits S _{3, j to} S of the 3rd to 15th rows are similarly performed.
_{15, j} (except j = 9) is digital input data β ₃
Each of ~ β ₁₅ is wired so as to be on / off controlled. That is, since the second FET q ₃ shown in FIG. 1 is provided in the switch circuits S _{i, j} (except j = 9) of each row, the gate input d of these FET q ₃ is Digital input data β _{1 to} β ₁₅ are applied.
On the other hand, the switches S _{1,9 to} S _15,9 connected to the FETs T _{1,9 to} T _15,9 of the central block have 15-bit data α.
_{1 to} α ₁₅ are associated and wired. That is, each of the switches S _{1,9 to} S _15,9 has the second F shown in FIG.
Since ETq ₃ is provided, these FET q ₃
Digital input data α _{1 to} α ₁₅ as the gate input d of
Has been applied.

Then, F in all switch circuits S _{i, j}
The source contact of ET q ₃ is commonly connected to the current addition point P, and the current addition point P is further connected to the current-voltage conversion circuit 6.

As described above, the respective constituent elements are arranged and formed according to the geometrical arrangement shown in FIG. 2, and the portion corresponding to the upper block is shown in FIG. 3 in a circuit configuration, and corresponds to the lower block. FIG. 4 shows a portion of the circuit configuration.

The operation of this embodiment will be described below.
In addition, in the switch circuit S _{i, j}
The current I ₀ flowing out of T T _{i, j} is called an off state when it does not flow to the current addition point P, and an on state when it flows. Further, the current-voltage conversion circuit 6 determines that the total current I at the current addition point P is _It is assumed that the product (RI _s ) of _s and the resistance R is generated as the analog voltage V _o .

First, when the converted binary data D _in is 0, all of the digital input data α _{1 to} α ₁₅ and β _{1 to} β ₁₅ are logic "H", so that all switch circuits S _{i, j.}
It is turned off like, analog voltage V _o is zero volts.

When D _in = 1, the digital input data α
₁ to? _15, since only alpha ₁ of the β ₁ ~β ₁₅ becomes logical "L", only the switch circuit S _{1, 9} is turned on, a current I ₀ of FET T _{1, 9} in the central block Only flows to the current addition point P. Therefore, V _o = RI ₀ .

When D _in = 2, digital input data α
_Since α ₁ and α _{2 of 1 to} α ₁₅ and β _{1 to} β ₁₅ are logic “L”, the switch circuits S _1,9 and S _2,9 are turned on, and the FET T ₁ in the center block is turned on. _{, 9} and T _{2 , 9} current I ₀ flows to the current addition point P. Therefore, V _o = 2RI ₀
Becomes

When D _in = 3, digital input data α
_Since α ₁ and α ₂ and α _{3 of 1 to} α ₁₅ and β _{1 to} β ₁₅ are logic “L”, the switch circuits S _1,9 and S _2,9 and S
FETs _{3 and 9 in} the center block are turned on.
_The currents I _{0 of 1,9} and T _2,9 and T _3,9 flow to the current addition point P. Therefore, V _o = 3RI ₀ .

Similarly, when D _in is in the range of 4 to 15,
Since the digital input data β _{1 to} β ₁₅ are always logic “H” and the number of digital input data α _{1 to} α ₁₅ are logic “L” sequentially increases according to the value of D _in , the analog voltage V _o. Is 4RI _{0 to} 15RI ₀ .

Next, when D _in = 16, all the digital input data α _{1 to} α ₁₅ become logic "H", and the switch S
_{1,9 to S15,9} are turned off. Instead, only β ₁ of the digital input data β _{1 to} β ₁₅ becomes the logic “L”. Therefore, the 16 switch circuits S in the first row
_{Since 1, j} (excluding j = 9) are simultaneously turned on, each current I ₀ from the FET T _{1, j} (excluding j = 9) flows to the current addition point P, and analog Voltage V
_o becomes 16RI ₀ .

When D _in is 17 to 31, β ₁
At the same time but remains at logic "L", since the digital input data alpha ₁ to? ₁₅ is increased in order according to the value of the number of the logic "L" is (D _in -16), analog voltage V _o is 1
7RI _{0 to} 31RI ₀ .

Thus, the Fs arranged in the central block
Each current I ₀ of ET T _{i, 9} is selectively flown to the current addition point P according to the logic of the digital input data α _{1 to} α ₁₅ corresponding to the decoded output of the lower 4 bits of the converted binary data D _in , The respective currents I ₀ of the remaining FETs T _{i, j} (excluding j = 9) arranged in the first row to the fifteenth row are output to decoded upper 4 bits of the converted binary data D _in. By selectively flowing to the current addition point P according to the logic of the corresponding digital input data β _{1 to} β ₁₅ , D /
A conversion is realized.

Incidentally, the digital input data α _{1 to} α ₁₅ ,
The relational expression between β _{1 to} β ₁₅ and the analog voltage V _o is V _o = RI ₀ {α ₁ + ... + α ₁₅ } +16 RI ₀ {β ₁
+ …… + β ₁₅ }… (2).

As described above, according to this embodiment, the lower 4 bits of the converted binary data D _in are arranged from the FETs T _{i, 9} arranged in a central block which traverses in the vertical direction at the center of the semiconductor chip. set by the current I _0, an integer multiple of the value of the upper 4 bits or 16, FET T i of each row i which are arranged in the lateral direction of the semiconductor chip. Thus set in the current I ₀ of _j, The FETs T _{i, j, which} are equal-weight current sources corresponding to the value of the converted binary data D _in , are selected almost uniformly in the semiconductor chip, and D / A conversion is performed. As a result, even if all the FETs T _{i, j} arranged and formed in the semiconductor chip are not completely uniform in the manufacturing process, these non-uniformities are dispersed, so that the converted binary data D analog for _in voltage V
The linearity of _o improves.

In this embodiment, the case where the converted binary data D _in of m = 8 bits is D / A converted has been described, but the number of bits is not limited. That is,
Generally, the m-bit converted binary data D _in is divided into upper g bits and lower h (h = m−g) bits, and (2 ^m −1) transistors serving as equal weight current sources are
The individual currents of the (2 ^g −1) transistors arranged in a matrix of (2 ^g −1) rows and (2 ^h +1) columns and further arranged in the central column of (2 ^h +1) columns. Is switched by the decoded data of the lower h-bit converted binary data, and the current of the transistor group of each row except the transistor group located in the central column is switched by the decoded data of the upper g-bit converted binary data. D / A conversion can be realized by causing the total current I _s corresponding to the binary data D _in to flow to the current addition point P.

Further, another embodiment will be described. The overall circuit configuration of this embodiment is the same as that of FIGS. 1 to 4, but the order of on / off control of the switch circuits S _{i, j} by the digital input data α _{1 to} α ₁₅ , β _{1 to} β ₁₅ is changed. It is a thing. That is, in the above embodiment, the digital input data α ₁
Located relation to? ₁₅ and the switch circuit S _{1, 9} to S _15,9 are corresponding to each order, further, the digital input data β ₁ ~β ₁₅
And the switch circuits S _{1, j to} S _{15, j of the first to} fifteenth rows
(However, j = 9 is excluded) is set to correspond to each row in order, but in another embodiment, as shown in FIG. 5, α ₁ is S _8,9 and α ₂ is S _9,9 , α ₃ is S _7,9 ,
alpha ₄ is S _{10, 9,} alpha ₅ is S _{6, 9,} alpha ₆ is S _{11, 9,} alpha ₇ is S
_5,9 , α ₈ is S _12,9 , α ₉ is S _4,9 , α ₁₀ is S _13,9 , α
₁₁ is S _3,9 , α ₁₂ is S _14,9 , α ₁₃ is S _2,9 , α ₁₄ is S
_15,9, alpha ₁₅ is associated with S _{1, 9,} performs current switching of FET T i, ₉ in the central block. Further, the switch circuit S _{i, 9} associated with the FET T _{i, 9} in the central block
Except for the switch circuit in each row i, β ₁
Is S _{8, j} , β ₂ is S _{9, j} , β ₃ is S _{7, j} , β ₄ is S _{10, j} , β ₅ is S _{6, j} , β ₆ is S _11,9 , β ₇ is S _{5, j} ,
β ₈ is S _{12, j} , β ₉ is S _{4, j} , β ₁₀ is S _{13, j} , β ₁₁ is S
_{3, j} , β ₁₂ is S _{14, j} , β ₁₃ is S _{2, j} , β ₁₄ is S _{15, j} , β
₁₅ is associated with S _{1, j} and the switch circuit S for each row
FET T _{i, j} corresponding to _{i, j} (excluding j = 9)
(However, j = 9 is excluded) current switching is performed.

According to this embodiment, the lower 4-bit value of the binary data D _in to be converted is arranged in a central block which vertically traverses the center of the semiconductor chip.
T _i, and sets the respective current I ₀ from _9, the integral multiple of the upper 4 bits or 16, FET T i of each row i which are arranged in the lateral direction of the semiconductor chip, each current _j I ₀ And the currents of the FETs arranged in the upper and lower rows are alternately and sequentially switched from the currents of the FETs arranged in the central row to the current addition point P. The FEET T _{i, j, which} is the equal-load current source corresponding to the value of the data D _in , is selected almost evenly in the semiconductor chip, and D / A conversion is performed. As a result, even if all the FETs T _{i, j} arranged and formed in the semiconductor chip are not completely uniform in the manufacturing process, these non-uniformities are dispersed, so that the converted binary data D The linearity of the analog voltage V _o with respect to _in is improved.

[0050]

As described above, according to the present invention, m
The bit-converted binary data D _in is divided into arbitrary upper g bits and remaining lower h bits, and (2 ^m −1) transistors serving as equal weight current sources are divided into (2 ^g −1) rows ( 2 ^h +1) are arranged in columns of a matrix, further, (2 ^h
The individual currents of the (2 ^g −1) transistors arranged in the central column of the (+1) th column are switched by the decoded data of the converted binary data of the lower h bits, and each row except the transistor group located in this central column Of the converted binary data D _in by switching the current of the transistor group of the high-order g bits by the decoded data of the converted binary data.
By passing the total current I _s corresponding to
Since the A / A conversion is performed, the total current I _s is arranged in the lateral direction of the semiconductor chip together with the respective currents from the equal-load current source group arranged in the central block that crosses the semiconductor chip in the longitudinal direction. And the currents of the equal-load current source group of each row are evenly added. As a result, even if all the equal-load current source groups arranged in the semiconductor chip are not completely uniform in the manufacturing process, these non-uniformities are dispersed and the converted binary data D _in
It is possible to improve the linearity of the analog voltage V _o with respect to.

In this other embodiment, the FET T _{i, 9} located in the central block and the residual FE arranged in each row i are arranged.
Although T T _{i, j} (excluding j = 9) is selected and controlled alternately in the order of upper and lower rows with the center row as the first reference,
FET T located in the central block
Residual F arranged only in _{i, 9} or arranged in each row i
It may be performed only for ET T _{i, j} (excluding j = 9).

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic circuit applied to an embodiment according to the present invention.

FIG. 2 is an explanatory diagram showing the overall configuration of the embodiment by a geometrical arrangement.

FIG. 3 is a circuit diagram showing the configuration of the embodiment by applying the basic circuit of FIG. 1 to the geometrical arrangement of FIG.

4 is a circuit diagram showing the configuration of the embodiment by further applying the basic circuit of FIG. 1 to the geometrical arrangement of FIG.

FIG. 5 is an explanatory diagram showing the overall configuration of another embodiment by a geometrical arrangement.

FIG. 6 is a circuit diagram showing a configuration of a conventional example.

FIG. 7 is an explanatory diagram showing a configuration of a conventional example by a geometrical arrangement.

FIG. 8 is an explanatory diagram showing a problem of the conventional example.

[Explanation of symbols]

6 ... Current-voltage conversion circuit, 7 ... Decoder circuit, q ₀ to
q ₃ , T _{i, j} ... p-channel FET, A, A _{a1 to} A _a8 ,
A _{b1 to} A _b8 ... Reference bias circuit, S, _{Si , j} ... Switch circuit, P ... Current addition point.

Claims (4)

[Claims] 1. Corresponding to any high-order g bits of converted binary data (D _in ) of m bits (2 ^g
-1) row and the remaining lower h bits (2)
⁽ 1) equal load current source groups formed along a matrix array of ( ^h +1) columns, and (2 ^g -1) equal load elements arranged in the central column of these equal load current source groups. The constant currents individually set by the current source groups are switched by the decoded data of the lower h-bit converted binary data, and the constant load current source groups in each row except for the equal load current source groups located in the central column are individually set. A constant current is switched by the decoded data of the upper g bits of the converted binary data to flow a total current (I _s ) corresponding to the converted binary data (D _in ) to the current addition point P, and the current switching circuit. A D / A converter, comprising: a current-voltage conversion circuit for converting the total current (I _s ) at the addition point (P) into an analog voltage (V _o ). 2. The current switching circuit, based on the decoded data of the converted binary data of the lower h bits,
Current switching is performed sequentially from the equal-load current sources located in the central row of the (2 ^g −1) equal-load current source groups arranged in the central column to the equal-load current sources located on both sides thereof. The D / A converter according to claim 1, which is characterized in that. 3. The current switching circuit is located in the central row of the equal weight current source groups of each row arranged in each row based on the decoded data of the converted binary data of the upper g bits. 2. The D / A converter according to claim 1, wherein currents are sequentially switched from the load current source group to the equal load current sources located on both sides of the load current source group. 4. The current switching circuit, based on decoded data of the converted binary data of the lower h bits,
Current is sequentially switched from the equal weight current sources located in the central row of the (2 ^g −1) equal weight current sources arranged in the central column to the equal weight current sources located on both sides thereof. Based on the decoded data of the upper g bits of the converted binary data, the equal weight current source group located in the central row of the equal weight current source groups of each row arranged in each row is located on both sides of the equal weight current source group. The D / A converter according to claim 1, wherein the currents of the equal-load current sources are sequentially switched.