JPH06202614A - Image display device - Google Patents

Abstract

PURPOSE:To increase the frame frequency while increasing the number of gradations of a simple matrix system liquid crystal display panel such as, specially, an STN type. CONSTITUTION:This image display device is equipped with an A/D converting circuit 11 which obtains digital image data consisting of (k) bit for each pixel from analog image data, a field memory part 13 which divides a storage area into (k) areas, and divides and stores the image data of (k) bits for each pixel, which are obtained by the A/D converting circuit 11, in (k) corresponding areas by bit positions from the most significant digit bit to the least significant digit bit, and a display driving circuit 17 which reads the image data out of the field memory 13 at frequencies corresponding to the areas wherein the image data are stored and drives corresponding pixels of the liquid crystal display panel 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display apparatus which uses a simple matrix type liquid crystal display panel as a display section to generate display data from digital image data and outputs the display data on the display section.

[0002]

2. Description of the Related Art Image display devices for obtaining liquid crystal image data of k bits per pixel from analog image data and driving a liquid crystal display panel based on the digital image data are widely used in liquid crystal televisions and the like. There is. In this type of image display device, the digitized image data is sequentially stored in the memory on a pixel-by-pixel basis, and, for example, when one field is stored in the memory, the image data stored in the memory is sequentially read out. To drive the display of a liquid crystal display panel or the like.

[0003]

In the image display device having the above-described structure, when the number of bits k of data per pixel is increased in order to increase the number of gradations and improve the display quality, The time required for writing / reading data from / in the memory also becomes longer, and the period for displaying one scan electrode must be set longer, and the frame frequency decreases, especially when the liquid crystal display panel is a simple matrix system. On the contrary, the display quality will be significantly reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image display device capable of increasing the number of gradations and simultaneously increasing the frame frequency. .

[0005]

That is, according to the present invention, an image data supply means for supplying image data having a digital value of k bits per pixel and a storage area divided into k areas are provided. K per pixel obtained in
A field memory for storing bit image data divided into k corresponding areas from the most significant bit to the least significant bit for each bit position and storing the image data stored in the field memory. And a display drive circuit for reading and driving the corresponding pixel of the display section by reading the number of times according to the area.

[0006]

With the above arrangement, the image data stored in the field memory is sequentially read out for each area in which the image data is stored. For example, the most significant bit data in the image data of k bits per pixel is read out. 2 ^k-1 times using each position 2 bit data using the 2 ^k-2 times, ..., by performing single-frame display of the total "2 ^k -1" using the least significant bit data, Since the amount of data to be transferred itself is small, it is possible to increase the number of gradations and at the same time increase the frame frequency. In particular, the display quality can be improved in a simple matrix type liquid crystal display panel such as STN type.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration, and an analog image signal is given to an A / D conversion circuit 11. A / D
The conversion circuit 11 converts the input analog image signal into, for example, 256 rows × 240 columns per frame and 4 pixels per pixel.
It is converted to bit digital value data and output to the line memory 12.

The line memory 12 delays the image data input from the A / D conversion circuit 11 every one horizontal synchronizing period (1H) corresponding to 256 rows × 4 bits, and during this 1H.
The minute image data is rearranged for each bit position from the most significant bit to the least significant bit and output to the field memory unit 13.

The field memory unit 13 comprises an input / output controller 14 and a DRAM 15. I / O controller
Reference numeral 14 denotes the image data input from the line memory 12 in accordance with the field inversion signal which is inverted for each field.
While writing in the RAM 15, the written image data is read out and output to the display drive circuit (shown as “D / D” in the figure) 17.

At this time, the DRAM 15 writes / reads the image data according to the designated address from the address controller 16 which controls the address based on the field inversion signal.

The display drive circuit 17 includes a field memory unit 13
The liquid crystal display panel 18 of the STN simple matrix system is sequentially driven and controlled based on the image data read from the image data, and the image data is displayed and output.

FIG. 2 shows a detailed circuit configuration in the field memory unit 13. As shown in the figure, the input / output controller 14 includes an inverter 14a and gate circuits 14b to 14e.
Composed of. The DRAM 15 is composed of two DRAMs 15a and 15b having a storage capacity of one screen, that is, 256 rows × 240 columns × 4 bits.

The field inversion signal is directly input to the gate circuits 14b and 14e of the input / output controller 14 as a gate signal, and also inverted via the inverter 14a and input to the gate circuits 14c and 14d as a gate signal.

Image data from the line memory 12 is written to the DRAM 15b via the gate circuit 14b and to the DRAM 15a via the gate circuit 14c. And D
The image data read from the RAM 15b is the gate circuit 14d.
The image data read from the DRAM 15a is sent to the display drive circuit 17 of the next stage via the gate circuit 14e.

The DRAM 15a and the DRAM 15b are
In both cases, the same address is designated according to the designated address from the address controller 16, and while one of them is writing data, the other is reading data. By repeating this alternately and repeatedly according to the field inversion signal, the input of the image data from the line memory 12 and the output of the image data to the display drive circuit 17 are continued without interruption.

Next, the actual operation of the above embodiment will be described.

Now, it is assumed that the A / D conversion circuit 11 samples analog image data and converts it into digital value image data as shown in FIG. That is,
The image data obtained here is for one horizontal synchronization period (1H).
It consists of 256 pixels, 4 bits per pixel, the most significant bit is Di (1 ≦ i ≦ 256), the second most significant bit is Ci, the third most significant bit is Bi, and the least significant bit is Ai.
And Then, the A / D conversion circuit 11 generates 4-bit pixel data (D1, C1, B1, A1) (D2, C2) within 1H.
, B2, A2) ... (D256, C256, B256, A2
56) line memory 1 as sequential image data
Output to 2.

The line memory 12 stores these 4-bit image data, delays them by 1H, replaces the data during the delay, and outputs them to the next 1H.

That is, in the line memory 12, FIG.
The input image data is rearranged by aligning it at each bit position of each pixel as shown in (4) and is output in units of 4 bits during the next 1H period. First, the most significant bit is (D1,
D2, D3, D4) (D5, D6, D7, D8) ...
(D253, D254, D255, D256) and then output the second significant bit (C1, C2, C3, C).
4) (C5, C6, C7, C8) ... (C253, C25
4, C255, C256).

Hereinafter, the third bit and the least significant bit are similarly output. Note that the image data shown in FIG. 3 (2) is not exactly the image data shown in FIG. 3 (1) being rearranged, but is the image data input 1H before that. is there.

The output of the line memory 12 is directly output to the 2 through the input / output controller 14 in the field memory unit 13.
It is written in either one of the two DRAMs 15a and 15b.
The operation of writing image data in the DRAM 15a (15b) will be described below.

Now, let the first column of the original image data be X1,
X1 for the 2nd row, Xl for the 1st row
It is represented by (1 ≦ l ≦ 240). First row X1
When the image data of 256 pixels is input to the DRAM 15a (15b), the address controller 16 operates as shown in FIG.
First, the column (row) address “j” (however,
“J” is a natural number in the range 1 ≦ j ≦ 60) fixed to “1”, and the row (column) address is “1” to “64”.
Up to the most significant bit (D
1, D2, D3, D4) (D5, D6, D7, D8)
.. (D253, D254, D255, D256) in DRAM15
Write to a (15b).

Next, the address controller 16 operates as shown in FIG.
As shown in (3), the column address “j” is fixed to “+60” and fixed to “61”, and the row address is updated and designated from “1” to “64” in the same manner as described above, and the pixel data of the pixel data Second bit (C1, C2, C3, C4) (C5, C
6, C7, C8) (C253, C254, C255, C
256) is written in the DRAM 15a (15b).

Similarly, as shown in FIG. 3C, the address controller 16 fixes the column address by "+60" and fixes it to "121", and then updates the row address from "1" to "64". Then, the third most significant bits (B1, B2, B3, B4) (B5, B6, B7, B) of the above pixel data.
8) ... (B253, B254, B255, B256) DR
In the AM 15a (15b), as shown in FIG. 3C, the column address is further fixed to "+60" and fixed to "181", and the row address is updated and designated from "1" to "64". Least significant bit of data (A1, A2, A3
, A4) (A5, A6, A7, A8) ... (A253
, A254, A255, A256) to the DRAM 15a (15b)
To write to.

This completes the writing of the original image data into the DRAM 15a (15b) for the first column X1.
Then, for the second column X2, the third column X3, and the fourth column X4 of the original image data, column addresses "1" and "6" are also applied.
The row address of each of "1", "121", and "181" is set to "6".
From 5 ”to“ 128 ”, from“ 129 ”to“ 192 ”,
While sequentially designating the update from "193" to "256", it is written in the DRAM 15a (15b) in the same manner as above. And
After writing the 4th column X4 of the original image data,
Next, the column addresses are respectively incremented by "+1" to "2" and "6".
2 "," 122 ", and" 182 ", writing is performed for the fifth column X5 to the eighth column X8 of the original image data.

Thereafter, the above operation is repeated in the same manner,
237th column X237 to 240th column X of the original image data
The column address of the DRAM 15a (15b) is "60" for 240
When the writing to "120", "180", and "240" is completed, the writing of the image data for one screen to the DRAM 15a (15b) is completed.

FIGS. 4 (1) to 4 (3) are shown in FIGS.
The operation of (3) is shown with the time width widened. The image data output from the A / D conversion circuit 11 for 256 rows × 4 bits is delayed for each horizontal synchronization period (1H), and the highest rank is obtained in the meantime. It can be seen that bits are rearranged for each bit position and written to the DRAM 15a (15b) from the least significant bit.

FIG. 5 shows a storage state of the DRAM 15a (15b) in which the image data for one screen is written in this way. Figure 5
As shown in (1), the DRAM 15a (15b) has column addresses "1 to 60" according to the number of bits "4" per pixel.
"61-120""121-180""181-24
The image data is divided into four areas of "0", and the image data is sequentially written in each area by dividing the bit position of each pixel.

In this case, as shown in FIG. 5B, for each address of each address, for example, at the address of the column address "1" and the row address "1", the first image of the first column X1 of the original image data is displayed. 1
The data of the same bit position among the four adjacent pixel data are collectively written so that the most significant bits D1 to D4 of the pixels of the fourth to fourth rows are written.

Next, reading of image data from the DRAM 15a (15b) and display on the liquid crystal display panel 18 by the display drive circuit 17 based on the read image data will be described.

At the beginning of reading image data for one screen,
As shown in FIG. 3 (4), the address controller 16 fixes the column address j'to "1", and then updates the row address from "1" to "64" within the period of (1/16) H. Then, the most significant bits (D1, D2, D3, D4) (D5, D6, D7) of each pixel in the first column X1 of the original image data
, D8) ... (D253, D254, D255, D256)
Is read from the DRAM 15a (15b) and sent to the display drive circuit 17 via the input / output controller 14.

The display drive circuit 17 includes an input / output controller 14
The 4-bit image data sequentially read from the DRAM 15a (15b) via the serial-parallel conversion is performed, for example, (D1,
Display drive circuit 17 when D2, D3, D4) is read
The signals are output to Y1 to Y4 of the signal electrodes to drive the display. Therefore, the row address "1" of the DRAM 15a (15b)
The display electrodes of Y1 to Y256 of the display driving circuit 17 are driven to display by inputting 4-bit data 64 times corresponding to "64".

Next, the address controller 16 sets the row address to "65" while the column address j'is fixed at "1".
To "128", "129" to "192",
Then, specify the sequential update from "193" to "256",
Most significant bit (D1, D2, D3, D4) of each pixel of the second column X2 to the fourth column X4 of the original image data
(D5, D6, D7, D8) (D253, D254,
D255, D256) is read from the DRAM 15a (15b).

Further, the address controller 16 is shown in FIG.
As shown in (4), the column address j ′ is fixed by “+1” and fixed to “2”, and then the row addresses are changed from “1” to “64”, “65” to “128”, as described above. From "129" to "192", and "193"
To "256" are sequentially designated to be updated, and the most significant bits (D1, D2, D3, D4) of each pixel of the fifth column X5 to the eighth column X8 of the original image data are ...
(D253, D254, D255, D256) to the DRAM 15a
The data is sequentially read from (15b).

As described above, the address controller 16 is configured as shown in FIG.
As shown in (4) and (5), the column address j'of the DRAM 15a (15b) is sequentially updated and set by "+1" until it becomes "60", four columns for each column, and the original image data. Until the 240th column, X240, the most significant bit (D1, D2, D3, D4) of each pixel in each column is ...
(D253, D254, D255, D256) to the DRAM 15a
Read from (15b).

The most significant bits (D1, D2, D) of each pixel in each column from the first column X1 to the 240th column X240 of the original image data read out as described above.
3, D4) ... (D253, D254, D255, D256)
Is sent to the display drive circuit 17 as it is.

As shown in FIG. 3 (5), the display drive circuit 17 outputs these image data as a result for one column of the adjustment, (1/1
6) Liquid crystal display panel 18 in sequence at the timing delayed by H
, And each pixel on the panel is driven to display.

As described above, the column address of the DRAM 15a (15b) is updated and set from "1" to "60", and each pixel of each column from the first column X1 to the 240th column X240 of the original image data is set. Read the most significant bit, LCD display panel
The operation displayed at 18 is repeated eight times as shown in FIG.

After the display using only the most significant bit of each pixel data is repeated eight times, the address controller 16 updates the column address j'of the DRAM 15a (15b) from "61" sequentially by "+1" each time. Set "120"
4 columns of original image data for each column, and until the 240th column X240 of the original image data,
Second-order bits (C1, C2, C) of each pixel in each column
3, C4) ... (C253, C254, C255, C256)
Is read from the DRAM 15a (15b).

The second bit (C1, C2, C) of each pixel in each column from the first column X1 to the 240th column X240 of the original image data read as described above.
3, C4) ... (C253, C254, C255, C256)
Is sent to the display drive circuit 17 as it is. Display drive circuit 17
Outputs this image data to the liquid crystal display panel 18 at a timing delayed by (1/16) H for one column of the adjustment, and drives each corresponding pixel on the panel for display drive.

As described above, the column address of the DRAM 15a (15b) is updated and set from "61" to "120", and each pixel of each column from the first column X1 to the 240th column X240 of the original image data is set. The operation of reading the second bit and displaying it on the liquid crystal display panel 18 is repeated four times as shown in FIG.

Similarly, the column address of the DRAM 15a (15b) is updated and set from "121" to "180", and the first column X1 to the 240th column X of the original image data is set.
The 3rd most significant bit (B1
, B2, B3, B4) (B253, B254, B255)
, B256) is read out and displayed on the liquid crystal display panel 18 is repeated twice as shown in FIG.

Thereafter, the column address of the DRAM 15a (15b) is updated and set from "181" to "240", and each pixel of each column from the first column X1 to the 240th column X240 of the original image data is set. Least significant bit (A1, A2, A
3, A4) (A253, A254, A255, A256)
Is read out and is displayed on the liquid crystal display panel 18 only once as shown in FIG.

As described above, the display driving circuit 17 uses the most significant bit of each pixel data for the liquid crystal display panel 18 as shown in FIG. A display operation is performed twice in one field by using the data of the third place and once by using the least significant bit in one field.

As a result, weighting is performed according to the bit position from the most significant bit to the least significant bit forming each pixel data, and the time division driving is performed many times within one field. It is possible to increase the number of gradations of each pixel while suppressing the data transfer amount per pixel to 1 bit and significantly reducing the image data data transfer amount and increasing the frame frequency. In particular, it can be made suitable for a simple matrix type liquid crystal display panel.

[0047]

As described above, according to the present invention, the image data supplying means for supplying the image data of the digital value of k bits per pixel and the storage area are divided into k areas, and the image data K per pixel obtained by the supply means
A field memory for storing bit image data divided into k corresponding areas from the most significant bit to the least significant bit for each bit position and storing the image data stored in the field memory. A display drive circuit for reading and driving the corresponding pixels of the display unit by reading the number of times according to the area in which the image data stored in the field memory is sequentially read out for each of the stored areas. Each of the most significant bit data in the k-bit image data is used for 2 ^k-1 times, each second-order bit data is used for 2 ^k-2 times, etc., and each least significant bit data is used once. by performing the frame display of the 2 ^k -1 ", since the amount of data itself is less likely to transfer that can increase the frame frequency at the same time increasing the number of gradations, in particular such as STN form It is possible to provide a preferable image display device in the pure matrix mode liquid crystal display panel.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed circuit configuration around a field memory unit shown in FIG.

FIG. 3 is a diagram for explaining the operation according to the embodiment.

FIG. 4 is a view for explaining the operation according to the embodiment.

FIG. 5 is a view for explaining the operation according to the embodiment.

FIG. 6 is a view for explaining the operation according to the embodiment.

[Explanation of symbols]

11 ... A / D conversion circuit, 12 ... Line memory, 13 ... Field memory section, 14 ... Input / output controller, 15 (15a, 15
b) ... DRAM, 16 ... Address controller, 17 ... Display drive circuit, 18 ... Liquid crystal display panel.

Claims (1)

[Claims] 1. An image data supply means for supplying image data of a digital value of k bits per pixel, and a storage area divided into k areas, and k bits per pixel obtained by the image data supply means. Image data of
A field memory that stores the most significant bit to the least significant bit by dividing it into k corresponding areas for each bit position, and the number of times the image data stored in this field memory is stored according to the stored area. An image display device comprising: a display driving unit that reads out and drives the corresponding pixel of the display unit.