JPH06201767A - Driver and semiconductor testing device - Google Patents

Abstract

PURPOSE:To generate the test signal over the wide range of the signal voltage level by using a transistor having small withstand voltage between a collector and an emitter. CONSTITUTION:A constant current is fed to differential circuits Qb, Qc via a vertically arranged transistor Qa controlling the output high level of a driver, a constant current is fed to an emitter follower Qd, a DC bias is applied to vertically stacked transistors Qa, Qb, Qc, Qd respectively using the detected low level as a reference, then the output voltage range of the driver can be widened while the maximum voltage between a collector and an emitter of the transistor Q8 is suppressed to the maximum output amplitude of the driver.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver for generating a test signal to an element under test, and a semiconductor test apparatus including the driver as a constituent element. A driver that can output a test signal as a signal voltage level over a wide range without using a high emitter-to-emitter breakdown voltage, and a driver itself can be easily made into a monolithic IC. The present invention relates to a semiconductor testing device including the semiconductor testing device.

[0002]

2. Description of the Related Art To test a device under test such as a so-called LSI, a semiconductor test device generates a test signal for the device under test, and a response signal from the device under test to the test signal is sent to the semiconductor test device. The quality of various electrical input / output characteristics of the device under test can be known by taking it in and comparing it with an expected value signal generated inside the device. By the way, in recent years, the number of input / output pins in the device under test has increased and the operating speed has increased,
With the diversification of input / output signal levels, it is a fact that the semiconductor test apparatus itself is required to easily deal with such situations. That is, there is a demand for downsizing of the device itself, high speed operation, generation of various test signal levels, and the like. In particular, among the various components, it is the current situation that the driver (driving circuit) for actually generating the test signal to the device under test is required to achieve those items. This is because the device under test has a large number of input / output pins, but the driver is provided for each input / output pin, and the test is simultaneously performed on the large number of input / output pins. This is because the ratio of the entire driver in the semiconductor test device is extremely large.

Here, the final stage output circuit of the driver according to the prior art will be briefly described. FIG. 6 shows its basic configuration. In this case, the collector-emitter voltage in each of the transistors Q2, Q4, Q6, Q8 is greatly influenced by the output voltage range of the driver itself. That is, for example, the output voltage range is set to -2 to + 9V, and the transistors Q2 and Q are
Assuming that each of Q4, Q6 and Q8 operates in the saturation region, a voltage of 1 to 12V is actually applied between the collector and emitter of each of the transistors Q2, Q4, Q6 and Q8 (however, , Transistors Q2, Q4
(When the collector-emitter voltage in each saturation region of Q6 and Q8 is set to 1 V or more). In other words, in this case, each of the transistors Q2, Q4, Q6, Q8 is required to have a withstand voltage of 12 V or more as its collector-emitter withstand voltage (BVce). In FIG. 6, I
o and Is are constant current sources whose current values are variable,
R1 and R2 are differential circuits (transistors Q4 and Q2, respectively).
(Including 6).

Incidentally, as for the technology of this type, for example, "I-E-E International Test Conference 1991" (IEEE INTER
NATIONAL TEST CONFERENCE 1991) “High Performance Spin Electronics Employing Gallium Arsenic IC and Hybrid”
Circuit packaging technology ”(HIGH
PERFORMANCE PIN ELECTRONICS EMPLOYING GaAsIC AND H
YBRID CIRCUIT PACKAGING TECHNOLOGY) is known. In addition to this, “SONY Semiconductor IC Da
"Ta Book 1990" includes "CXB110" as a laser driver.
8Q ”is described.

[0005]

By the way, the driver according to the prior art is mainly configured as a hybrid IC from the viewpoints of collector-emitter breakdown voltage and easy circuit adjustment by trimming. In order to deal with various requirements, the driver is a monolithic I
It needs to be configured as C. However, when the driver is configured as a monolithic IC, the operating speed of the driver itself is almost proportional to the cutoff frequency of the transistor itself, whereas the collector-emitter breakdown voltage of the transistor itself is inversely proportional to the cutoff frequency. The facts have become something that must be taken into account. Fig. 7 shows a concrete example of collector-emitter breakdown voltage-cutoff frequency characteristics in a monolithic IC transistor (○, △, and □ indicate semiconductor manufacturers). Breakdown voltage BVce is cutoff frequency f _TMAX
It can be seen that it is almost inversely proportional to. Therefore,
From this fact, if an attempt the operation speed of a driver itself, but must be used having a large cut-off frequency f _TMAX as a transistor, having a large cut-off frequency f _TMAX its collector- It is clear that the withstand voltage BVce between the emitters is small and a large withstand voltage BVce between the collector and the emitter cannot be secured. That is, when a transistor having a large cutoff frequency f _TMAX is used as the transistor, the driver itself can operate at high speed, but on the other hand, its output voltage range is limited to within the collector-emitter breakdown voltage BVce. Therefore, it is impossible to deal with the test of the device under test having a large input / output signal level.

A first object of the present invention is to use a transistor having a high collector-emitter breakdown voltage as a transistor and to make it easy to form a monolithic IC by itself. The purpose of the present invention is to provide a driver that can be generated as a voltage level having a wide range. A second object of the present invention is, in addition to the above first object, is to provide a driver that can easily generate test signals of various levels for various devices under test. A third object of the present invention is to provide a semiconductor test apparatus in which the apparatus itself is downsized, the operation speed is increased, and the output voltage range is wide. In addition to the third object, a fourth object of the present invention is to provide a semiconductor test apparatus capable of easily testing various devices under test.

[0007]

A first object of the present invention is basically to provide a differential circuit in which each differential pair transistor is configured as first and second vertically stacked transistors, and the differential circuit. The first and second load resistors corresponding to the first and second vertically stacked transistors, and the third vertically stacked transistor that controls the output high level of the driver itself,
An emitter follower formed by a fourth vertically stacked transistor from which the output of the driver itself is taken out, and a first constant current flowing through the differential circuit through the third vertically stacked transistor and the first and second load resistors. A current source, a second constant current source for supplying a variable current to the emitter follower, a low / high level detection circuit for detecting either a low level or a high level of the output voltage of the driver itself, and the low / high level At least a bias generation circuit that individually generates a DC bias voltage according to the output voltage level at the base of the upper transistor in each of the first to fourth vertically stacked transistors on the basis of the detection level from the detection circuit. It is achieved by merging.

The above-mentioned second object is basically the above-mentioned differential circuit in which each differential pair transistor is configured as first and second vertically stacked transistors, and the above-mentioned differential circuit as a load of the differential circuit. First and second corresponding to first and second vertically stacked transistors
A second load resistor, a third vertically stacked transistor for controlling the output high level of the driver itself, an emitter follower by a fourth vertically stacked transistor from which the output of the driver itself is taken out, the third vertically stacked transistor and A first constant current source for supplying a variable constant current to the differential circuit via first and second load resistors, a second constant current source for supplying a variable current to the emitter follower, and an output voltage of the driver itself. A low / high level detection circuit for detecting either a low level or a high level, and the above-mentioned first to fourth based on a detection level from the low / high level detection circuit and an external device under test type setting signal. The number of bias generation circuits that individually generate a DC bias voltage according to the output voltage level is reduced at the base of the upper transistor in each of the vertically stacked transistors of It is achieved by allowed to be provided.

The third object is basically to configure each of the differential pair transistors as first and second vertically stacked transistors as a driver for generating a test signal to the device under test. A differential circuit, first and second load resistors corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a third vertically stacked circuit for controlling the output high level of the driver itself. A transistor, an emitter follower formed by a fourth vertically stacked transistor from which the output of the driver itself is taken out, and a variable constant current flowing through the differential circuit through the third vertically stacked transistor and the first and second load resistors. 1 constant current source, a second constant current source for supplying a variable current to the emitter follower, and low / high level detection for detecting either low level or high level of the output voltage of the driver itself. And road, based on the detection level from the low / high level detection circuit, the base of the upper transistor in cascode transistors each of the first to fourth,
This is achieved by providing a driver including at least a bias generation circuit that individually generates a DC bias voltage according to the output voltage level as a component.

The fourth object is basically to configure each of the differential pair transistors as first and second vertically stacked transistors as a driver for generating a test signal to the device under test. A differential circuit, first and second load resistors corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a third vertically stacked circuit for controlling the output high level of the driver itself. A transistor, an emitter follower formed by a fourth vertically stacked transistor from which the output of the driver itself is taken out, and a variable constant current flowing through the differential circuit through the third vertically stacked transistor and the first and second load resistors. 1 constant current source, a second constant current source for supplying a variable current to the emitter follower, and low / high level detection for detecting either low level or high level of the output voltage of the driver itself. The output voltage level to the base of the upper transistor in each of the first to fourth vertically stacked transistors, based on the detection level from the low / high level detection circuit and the external device under test type setting signal. This is achieved by providing a driver including at least a bias generation circuit that individually generates a corresponding DC bias voltage as a component.

[0011]

[Function] The point is to replace the transistor that constitutes a driver with a high breakdown voltage with a vertically stacked transistor, and change the collector-emitter voltage of each transistor that constitutes the vertically stacked transistor to the output voltage level of the driver. The variable setting is made according to. More specifically, when the bias circuit generates a bias voltage according to the output voltage level of the driver and then applies it to the base of the upper transistor of the vertically stacked transistor,
The voltage applied to the vertically stacked transistors is divided by the upper and lower transistors to a predetermined level, so that the collector-emitter voltage of each of these transistors can be suppressed small. Further, when the bias voltage is generated, when the type of the device under test is taken into consideration, test signals of various levels can be generated. Therefore, when the semiconductor tester is equipped with the above-described driver as a constituent element, its size, high-speed operation, and output voltage range can be increased, and further, various signal levels can be obtained. The various devices under test can be easily tested.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. Before starting a detailed description of the present invention, first, a method of adjusting a collector-emitter voltage in a vertically stacked transistor according to the present invention will be specifically described with reference to FIG. Taking a specific voltage value as an example, the minimum value of the collector-emitter voltage Vce for operating the transistor in a sufficient saturation region is 1 V, the voltage range input to the base of the transistor is 0 to 12 V, Input voltage amplitude Vswing is 9
Assuming V, there is only one transistor Q in FIG.
The voltage distribution in the case of 1 is shown, but as can be seen from this, the collector-emitter voltage Vce of the transistor Q1 is 13 V at maximum. On the other hand, FIG. 2B shows the voltage distribution when two transistors Q1 and Q2 are vertically stacked in order to keep the collector-emitter voltage Vce small.
In this case, if the bias voltage Vbias to the base of the transistor Q2 is variably set according to the input voltage Vin, the collector-emitter voltage Vce of the transistor Q1.
Can be suppressed to 10 V at the maximum. That is, FIG.
In the case of the configuration shown in (b), the collector-emitter voltage Vce of the transistor Q1 is the voltage limited to the input voltage level applied to the base of the transistor Q2, and further the base of the transistor Q1. It will be limited to the amplitude of the input voltage applied to. Therefore, FIG.
In FIG. 2A, the collector-emitter voltage Vce withstand voltage of the transistor Q1 needs to be 13 V or more, but in the vertically stacked transistor of FIG.
The withstand voltage Vce between the emitters is set to 10 V or more. Thus, the method of adjusting the collector-emitter voltage has been described by taking a specific voltage value as an example, but the adjusting method can be applied to voltage values other than the above.

Now, the present invention will be described in detail with reference to FIG.
Shows a circuit configuration of an example of a driver according to the present invention. In this case, the driver uses the constant current source I
o, Is, differential pair transistors Q4, Q6, load resistors R1, R2, transistor Q2 for setting the driver high level, emitter follower transistor Q8, and collectors of transistors Q2, Q4, Q6, Q8. Control the base potential of these transistors Q1, Q3, Q5, Q7 and the transistors Q1, Q3, Q5, Q7 vertically stacked in order to keep the emitter-to-emitter voltage Vce low. The bias generating circuit 101 and the low level detecting circuit 103 for detecting the low level of the output of the driver are included. Transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, as a pair
Q8 is the vertically stacked transistors Qa, Qb, Qc,
Qd is configured, and if the DC voltage input to the base of the upper transistor is changed according to the input voltage level of the lower transistor, the collector-emitter voltage of the lower transistor is changed. Vce can be kept small. At this time, the output amplitude of the driver is represented by the product of the load resistance R2 and the constant current Io, and the desired driver output amplitude is obtained by controlling the constant current control terminal Vcs. The high level of the driver output is the set voltage VH input to the base of the transistor Q2.
The voltage value is controlled by F and drops by the base-emitter voltage of the transistors Q2 and Q3.

Here, taking a concrete voltage value as an example, to explain more concretely, as in the case of FIG. 2, the collector-emitter voltage Vce for operating the transistor in a sufficient saturation region is obtained. If the minimum value is 1V, the output voltage range of the driver is -3 to 9V, and the maximum output voltage amplitude Vswing is 9V, in the case of the condition (1), the output amplitude Vswing is 9V,
When the output voltage level is 0 to 9 V, by biasing each base voltage of the upper transistor of the vertically stacked transistors to the voltage value of the condition (1), the collector-emitter voltage Vce of the lower transistor at the maximum can be set. Is 10V. Next, in the case of the condition (2), the output amplitude Vswing
Is 9 V and the output voltage level is -3 to 6 V, by biasing each base voltage of the upper transistors of the vertically stacked transistors to the voltage value of the condition (2), the condition (1)
As in the case of, the collector-emitter voltage Vce of the lower transistor is 10 V at maximum. That is, by variably setting the base voltage of the upper transistor in the vertically stacked transistors according to the output voltage level, the collector-emitter voltage Vce of the lower transistor is not limited to the output voltage range. By the way, in FIG.
Based on the detected low level from the low level detection circuit 102, the bias generation circuit 101 generates bias voltages V _BS1 , V _BS1 .
_BS2, V _BS3 but are generated, upon detecting a high level of driver at a high level detection circuit (not shown), sense bias voltage V _BS1 bias generating circuit 101 based on a high level, V _BS2, V _BS3 May be generated.

FIG. 3 also shows the overall structure of an example of the semiconductor test apparatus according to the present invention, which includes the driver configured as described above as a constituent element. As shown in the figure, a control computer (for controlling the entire device) 1 as a part of the device, a monitor (for displaying various data) 2, a printer (for printing test programs, test results, etc.) 3, a reference signal generator (specifically). 4 and the tester bus 15 are commonly provided to a large number of input / output pins of the device under test 14, and the other parts are provided corresponding to the input / output pins. That is, the timing generator 5, the pattern generator 6,
Fail memory 7, digital comparator 8, waveform formatter 9, driver 10, analog comparator 11
The part including the reference voltage generator 12 is provided corresponding to the input / output pin. The operation of the device under test 14 will be described below.
The test is performed by simultaneously applying a test signal to each of the input / output pins. For convenience of description, the test operation corresponding to one input / output pin will be described below. That is, in the reference signal generator 4, the reference clock 4a as the time reference of the test waveform is generated as its cycle variable based on the frequency setting signal 15a from the control computer 1, and in the timing generator 5, the control computer again. Timing setting signal 15 from 1
By dividing the reference clock 4a based on b and delaying it as necessary, phase signals 5a, 5b, 5c having a desired cycle and time delay are generated. Further, in the pattern generator 6, at the timing of the phase signal 5b from the timing generator 5, the pattern data signal 6a and the expected value signal 6 defined by the pattern generation data 15c from the control computer 1 are generated.
b is generated. Furthermore, in the waveform formatter 9, the test waveform 9a for testing the device under test 14 is generated by logically synthesizing the pattern data signal 6a at the timing of the phase signal 5a. , The waveform setting level signal 12a from the reference voltage generator 12 in the driver 10
According to the above, the waveform is shaped into the high-level and low-level test waveforms 10a, and then applied as a test signal to the corresponding input / output pin of the device under test 14 via the transmission line 13. On the other hand, in response to the test signal, a response waveform 14a is output from the input / output pin. The response waveform 14a is transmitted through the transmission line 13 to the analog comparator 11 at the timing of the phase signal 5c and the reference voltage generator. By being compared with the comparison reference voltages 12b and 12c from 12 respectively, the comparison result 11a on the waveform level can be obtained from the analog comparator 11. This comparison result 11a is compared by the digital comparator 8 at the timing of the expected value signal 6b corresponding to the normal response waveform and the phase signal 5c from the pattern generator 6, and the pass / fail judgment result 8a in response to the test signal is obtained. Is what you get. The pass / fail judgment result 8a is temporarily stored in the fail memory 7. However, after all the tests for the device under test 14 have been completed, the pass / fail judgment result 8a together with the results from the fail memories corresponding to other input / output pins are sent via the tester bus 15. In addition to being collected by the control computer 1 as 15d, comprehensive pass / fail judgment processing for the device under test 14 is performed. Therefore,
By applying, as the driver 10 having the above-described configuration, the one including the above-described vertically stacked transistor, bias generation circuit, and the like, a semiconductor test apparatus capable of high-speed operation and having a wide output voltage range can be realized. is there.

FIG. 4 also shows a circuit configuration of an example of the driver according to the present invention, in which the type of the device under test is taken into consideration. 1 have the same reference numerals as those in FIG. 1, but as shown in the figure, a mode select signal indicating the type of the device under test is newly introduced into the bias generation circuit 101 in this example. In addition, the bias voltage generated by the bias generation circuit 101 is switched accordingly. For example, CMOS type device, T
In the case of the TL system element, the mode select signal is set to "0", and then the bias voltage is set in the bias generation circuit 101 so that the bias voltage is generated as a high potential. After being regarded as "1",
The bias generation circuit 101 is set so that the bias voltage is generated as a low potential. In this way, when the bias voltage is set and controlled according to the type of the device under test, the output voltage range of the driver for the device under test can be easily automated.

Finally, the same reference numerals are given to the same components as those shown in FIG. 1, and the circuit configuration of another example of the driver according to the present invention will be described with reference to FIG. The one in is configured as a collector output type. As in the case of FIG. 1, the individual transistors as the essential constituent elements are vertically stacked, and the upper transistor Q is formed according to the driver output level.
The base potentials of 1, Q3 and Q5 are the bias generation circuit 101.
The collector-emitter voltage Vce of the transistor is not limited to the output voltage range by being controlled by. It is needless to say that the high level detection circuit in place of the low level detection circuit 102 and the mode select signal can also be introduced in this example.

[0018]

As described above, according to the first and fifth aspects of the present invention, the transistor having a high collector-emitter breakdown voltage is not used as the transistor, and the transistor itself can be easily formed into a monolithic IC. A driver capable of generating a test signal to a test element as a signal voltage level over a wide range, and according to claims 2 and 6, in addition to the effect thereof, various levels of various levels for various elements under test. A driver that can easily generate test signals
Further, according to claims 3 and 7, the semiconductor test apparatus in which the apparatus itself is downsized, the operation speed is increased, and the output voltage range is wide,
Furthermore, according to claims 4 and 8, in addition to such effects, semiconductor test devices capable of easily testing various devices under test are obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of an example of a driver according to the present invention.

2A and 2B are views for explaining a method of adjusting a collector-emitter voltage in a vertically stacked transistor according to the present invention.

FIG. 3 is a diagram showing a configuration of an example of a semiconductor test apparatus including a driver according to the present invention as a component.

FIG. 4 is a diagram showing a circuit configuration of an example of a driver according to the present invention, in which a type of a device under test is taken into consideration.

FIG. 5 is a diagram showing a circuit configuration of another example of the driver according to the present invention.

FIG. 6 is a diagram showing a configuration of a final stage output circuit of a driver according to a conventional technique.

FIG. 7 is a diagram showing an example of collector-emitter breakdown voltage-cutoff frequency characteristics in a transistor for a monolithic IC.

[Explanation of symbols]

1 ... Control computer, 4 ... Reference signal generator, 5 ... Timing generator, 6 ... Pattern generator, 7 ... Fail memory, 8 ... Digital comparator, 9 ... Waveform formatter, 10 ... Driver, 11 ... Analog comparator, 1
2 ... Reference voltage generator, 14 ... Device under test, 10
1 ... Bias generation circuit, 102 ... Low level detection circuit,
Q1-Q8 ... Transistor, R1, R2 ... Load resistance, I
0, Is ... Constant current source

Claims (8)

[Claims] 1. A driver for generating a test signal to a device under test, wherein each of the differential pair transistors includes a first and a second transistor.
A differential circuit configured as a second vertically stacked transistor, first and second load resistors corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a driver itself. Via the third vertically stacked transistor for controlling the output high level, the emitter follower by the fourth vertically stacked transistor from which the output of the driver itself is taken out, the third vertically stacked transistor and the first and second load resistors. A first constant current source for supplying a variable constant current to the differential circuit, a second constant current source for supplying a variable current to the emitter follower, and detection of low level or high level of the output voltage of the driver itself. Low / high level detection circuit
A bias generation circuit that individually generates a DC bias voltage according to the output voltage level at the base of the upper transistor in each of the first to fourth vertically stacked transistors with reference to the detection level from the low / high level detection circuit. And a driver including at least. 2. A driver for generating a test signal to a device under test, wherein each of the differential pair transistors includes a first and a second transistor.
A differential circuit configured as a second vertically stacked transistor, first and second load resistors corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a driver itself. Via the third vertically stacked transistor for controlling the output high level, the emitter follower by the fourth vertically stacked transistor from which the output of the driver itself is taken out, the third vertically stacked transistor and the first and second load resistors. A first constant current source for supplying a variable constant current to the differential circuit, a second constant current source for supplying a variable current to the emitter follower, and detection of low level or high level of the output voltage of the driver itself. Low / high level detection circuit
Based on the detection level from the low / high level detection circuit and an external device under test type setting signal,
A driver comprising at least a base of an upper transistor in each of the fourth vertically stacked transistors, and a bias generation circuit for individually generating a DC bias voltage according to an output voltage level. 3. A test signal is generated for the device under test, and the response signal from the device under test for the test signal is compared with a separately generated expected value signal to obtain a test signal for the device under test. Is a semiconductor tester for testing various electrical input / output characteristics of the differential pair transistor, and each of the differential pair transistors is a first and second vertically stacked transistor as a driver for generating a test signal to the device under test. A differential circuit configured, first and second load resistances corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a first control output level of the driver itself. Via the third vertical stack transistor, the emitter follower of the fourth vertical transistor from which the output of the driver itself is taken out, the third vertical transistor and the first and second load resistors. A first constant current source for supplying a variable constant current to the differential circuit, a second constant current source for supplying a variable current to the emitter follower, and detection of low level or high level of the output voltage of the driver itself. And a DC bias corresponding to the output voltage level at the base of the upper transistor in each of the first to fourth vertically stacked transistors based on the detection level from the low / high level detection circuit. A semiconductor test apparatus comprising a driver including at least a bias generation circuit for individually generating a voltage. 4. A device under test is generated by generating a test signal for the device under test and comparing a response signal from the device under test with respect to the test signal with a separately generated expected value signal. Is a semiconductor tester for testing various electrical input / output characteristics of the differential pair transistor, and each of the differential pair transistors is a first and second vertically stacked transistor as a driver for generating a test signal to the device under test. A differential circuit configured, first and second load resistances corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a first control output level of the driver itself. Via the third vertical stack transistor, the emitter follower of the fourth vertical transistor from which the output of the driver itself is taken out, the third vertical transistor and the first and second load resistors. A first constant current source for supplying a variable constant current to the differential circuit, a second constant current source for supplying a variable current to the emitter follower, and detection of low level or high level of the output voltage of the driver itself. Low / high level detection circuit, and the base of the upper transistor in each of the first to fourth vertically stacked transistors based on the detection level from the low / high level detection circuit and the external device under test type setting signal. In addition, the semiconductor testing device is provided with a driver including at least a bias generation circuit for individually generating a DC bias voltage according to the output voltage level. 5. A driver for generating a test signal to a device under test, wherein each of the differential pair transistors includes a first and a first transistor.
A differential circuit configured as a second vertically stacked transistor, first and second load resistors corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a driver itself. A third vertically stacked transistor that controls the output high level, and the third vertically stacked transistor and the first and second transistors.
A constant current source for supplying a variable constant current to the differential circuit via a second load resistor, a low / high level detection circuit for detecting either a low level or a high level of the output voltage of the driver itself, and the low / high level detection circuit. A bias generation circuit for individually generating a DC bias voltage corresponding to the output voltage level at the base of the upper transistor in each of the first to third vertically stacked transistors with reference to the detection level from the high level detection circuit. At least a driver provided. 6. A driver for generating a test signal to a device under test, wherein each of the differential pair transistors includes a first transistor and a first transistor.
A differential circuit configured as a second vertically stacked transistor, first and second load resistors corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a driver itself. A third vertically stacked transistor that controls the output high level, and the third vertically stacked transistor and the first and second transistors.
A constant current source for supplying a variable constant current to the differential circuit via a second load resistor, a low / high level detection circuit for detecting either a low level or a high level of the output voltage of the driver itself, and the low / high level detection circuit. A DC bias voltage corresponding to the output voltage level is applied to the base of the upper transistor in each of the first to third vertically stacked transistors with reference to the detection level from the high level detection circuit and the external device under test type setting signal. A driver comprising at least a bias generating circuit which is individually generated. 7. A device under test is produced by generating a test signal for the device under test and comparing a response signal from the device under test with respect to the test signal with a separately generated expected value signal. Is a semiconductor tester for testing various electrical input / output characteristics of the differential pair transistor, and each of the differential pair transistors is a first and second vertically stacked transistor as a driver for generating a test signal to the device under test. A differential circuit configured, first and second load resistances corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a first control output level of the driver itself. 3 vertically stacked transistors, a constant current source for supplying a variable constant current to the differential circuit via the third vertically stacked transistors and the first and second load resistors, and low level and high level of the output voltage of the driver itself. A low / high level detection circuit for detecting any of the bells, and an output voltage to the base of the upper transistor in each of the first to third vertically stacked transistors based on the detection level from the low / high level detection circuit. A semiconductor test apparatus comprising a driver including at least a bias generation circuit for individually generating a DC bias voltage according to a level. 8. A device under test is generated by comparing a response signal from the device under test with the test signal to a device under test while the response signal from the device under test is separately generated. Is a semiconductor tester for testing various electrical input / output characteristics of the differential pair transistor, and each of the differential pair transistors is a first and second vertically stacked transistor as a driver for generating a test signal to the device under test. A differential circuit configured, first and second load resistances corresponding to the first and second vertically stacked transistors as a load of the differential circuit, and a first control output level of the driver itself. 3 vertically stacked transistors, a constant current source for supplying a variable constant current to the differential circuit via the third vertically stacked transistors and the first and second load resistors, and low level and high level of the output voltage of the driver itself. A low / high level detection circuit that detects any of the bells, and the first to third vertically stacked transistors based on the detection level from the low / high level detection circuit and an external device under test type setting signal. A semiconductor test apparatus comprising a driver including at least a base of each upper transistor and a bias generation circuit for individually generating a DC bias voltage according to an output voltage level.