JP2691182B2 - Latch-up measurement method for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit latch-up measuring method and a voltage generating circuit for realizing the method.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, since a PN junction and an NPN junction are complicated and complicated, when the voltage value between specific terminals exceeds a certain level, the entire integrated circuit may become conductive. , Such a phenomenon is called latch-up.

For example, the CMOS inverter shown in FIG. 1 has a structure using a silicon wafer as shown in FIG. 2. The equivalent circuit of a parasitic transistor by this is as shown in FIG. 3, and the output voltage V _out is the power supply voltage. When it is higher than V _DD , both transistors of PNP and NPN are turned on, and I ₁ is the first transistor Tr ₁
When it flows to the emitter of the second transistor Tr ₂ , it induces a collector current I ₂ , which raises the potential of the base of the second transistor Tr ₂ , and the current increase associated therewith induces an emitter current I ₄ in the second transistor Tr ₂ . , I ₄ further raises the base potential of the first transistor Tr ₁ and induces a collector current I _6, which in turn increases the currents of the two transistors Tr ₁ and Tr ₂ .
A conductive state is established between V _{DD and} V _ss .

In the case of the CMOS structure, since latch-up occurs according to the same principle as that of the thyristor, it is stated that the latch-up in the CMOS structure is caused by the parasitic thyristor.

Since such a latch-up phenomenon should be originally avoided in an integrated circuit, a latch-up test is conducted in the integrated circuit, and the latch-up phenomenon is conducted when any voltage is applied between the terminals. It is required to test if the condition occurs.

Generally, when performing a latch-up test, a so-called constant current injection method in which a constant current is applied between terminals,
A so-called over-power supply method in which a power supply voltage that is originally required in an integrated circuit is applied to the terminal to which a power supply voltage that is originally required is applied, that is, a capacitor is charged in advance and the charge is injected into each terminal. , The so-called electrostatic pulse application method,
Etc. are used. Of these, the over-power supply method is related to power supply terminals, and it is impossible to arbitrarily select and test between terminals of an integrated circuit.

In this respect, the constant current injection method and the electrostatic pulse application method are convenient in that a quoted terminal is set and a latch-up test is performed, and the constant current injection method is the most commonly used method. However, the influence of the test circuit for measurement is extremely small.

However, even when the latch-up is not generated by the constant current injection method, the latch-up may be generated by the electrostatic pulse applying method. Therefore, actually, the latch-up test by the electrostatic pulse applying method should be adopted. The reality is that it is unavoidable.

On the other hand, the electrostatic pulse application method cannot avoid the disadvantage that the test result is significantly affected by the stray inductance of the line of the circuit under test.

By the way, it is publicly known that the voltage applied to the device under test is sequentially changed by using a programmable power supply control unit or the like (for example, Japanese Patent Laid-Open No. 3-1 / 1993).
94607), on the other hand, in the IC test apparatus, selecting a plurality of power supply voltages as appropriate is also
It is already publicly known (for example, Japanese Patent Laid-Open No. 60-2267).
However, in the electrostatic pulse applying method, it is appropriate to apply what voltage and in what order in order to realize the latch-up measurement that is not affected by the stray inductance. In regards to, no sufficient research has been conducted so far.

[0011]

After all, the electrostatic pulse applying method is nothing but applying a high voltage to an arbitrary terminal of an integrated circuit, but the present invention applies each voltage and its period to each power supply terminal of the integrated circuit. A method for performing a latch-up test by applying a voltage having a waveform appropriately selected according to a predetermined order and changing each voltage and its time by appropriately changing it according to the target integrated circuit and the type of terminal. Another object of the present invention is to provide a voltage output device for realizing this and to realize latch-up measurement that is not affected by stray inductance.

[0012]

In order to solve the above-mentioned problems, the latch-up test method of the present invention uses the first period T ₁
Is a positive initial voltage V ₁ , a second period T ₂ is a lower negative voltage V ₂ , a third period T ₃ is a higher voltage V ₃ than the initial voltage, and the final 4 period T ₄
Is applied to the integrated circuit with a voltage having a voltage V ₄ that is substantially equal to the initial voltage, and V ₁ , V ₂ , V ₃ , V ₄ and T ₁ , depending on the type of the integrated circuit and the target terminal,
The latch-up measuring method for an integrated circuit is based on changing the values of T ₂ , T ₃ , and T ₄ .

The above method is characterized in that in the latch-up test shown in FIG. 4, the power supply 1 applied to the integrated circuit 2 uses a power supply which generates a voltage having a waveform shown in FIG. The power supply 1 is characterized by realizing this.

[0014]

In the present invention, the voltage shown in FIG.
Although it is characterized in that it is applied to the power supply 1 shown in Fig. 5, the application of such a voltage is not determined by theoretical calculation, and as a result of actual power involving trial and error, the application of the voltage shown in Fig. 5 causes It is derived from the fact that the latch-up test is possible.

Here, to explain the purpose of applying each voltage, the voltage V ₁ is an initial voltage for initially bringing the integrated circuit into an operating state, and generally latch-up occurs from a conductive state. Although it has been set in view of the above, by measuring the current of the integrated circuit corresponding to the voltage V ₁ and comparing it with the current corresponding to the voltage V ₄ later, it is determined whether or not latch-up has occurred. You can do it.

That is, the voltage V ₁ is a voltage for bringing the integrated circuit into an operating state and determining the success or failure of latch-up together with the voltage V ₄ applied later.

The voltage V ₂ is a negative voltage for causing latch-up, but it has been found that the larger the negative value is (the lower the voltage is), the more easily the latch-up occurs.

The basis of such a phenomenon is CMOS
The capacitance between the base and the collector of the odd bipolar transistor which causes latch-up in the integrated circuit of the structure is increased by the negative voltage V ₂ , so that the critical off-voltage rise of the thyristor formed by the odd bipolar transistor is increased. It is possible that the rate has dropped, but no clear phenomenon in this regard has been clarified.

When the negative value of the voltage V ₂ is larger than a certain limit value (hereinafter referred to as “limit value V _2S ”), the value of the voltage V ₃ thereafter is a predetermined reference value (hereinafter, referred to as “the limit value V _2S ”). Reference value V _3S ”), a latch-up phenomenon may occur regardless of the value.

On the other hand, when the magnitude of the negative voltage V ₂ is smaller than the predetermined value, latch-up does not always occur, and the magnitude of the voltage V ₃ and the voltage V _{2 are different} from each other. The time constant at the transient voltage showing the sawtooth wave when changing to V ₃ (however, between the power supply voltage and the integrated circuit,
Due to the presence of the resistance R and the capacitance C, the transient voltage draws a so-called exponential curve, and its time constant is usually CR. ), The success or failure of latch-up will be influenced.

As described above, the negative voltage V ₂ is a voltage that determines the success or failure of latch-up, and the positive voltage V ₃ is within the limit that latch-up cannot occur unless it exceeds the reference value V _3S . , The success or failure of the latch-up is affected, and when the voltage V ₂ is higher than the limit value V _2S (small as a negative value), the success or failure of the latch-up is affected by the value of the voltage V ₃ and the rising edge of the voltage V _2. More than
The voltage V ₃ is a voltage that determines the success or failure of latch-up together with the voltage V ₂ .

The voltage V ₄ is a voltage for determining whether or not latch-up has occurred, and as described above, the voltage V 4
Response current I ₁ of the integrated circuit at the stage the application of the ₁
And the response current I _{4 at the} stage of applying the voltage V ₄ are substantially equal, latch-up does not occur, and conversely, when the response current I ₄ is larger than the response current I _1. , It turns out that latch-up has occurred.

The measuring circuit 6 in FIG. 4 measures the response current for each input voltage, and the oscilloscope display of FIG. 6 is used to inspect the waveform of the applied voltage or response current.

In the present invention, in addition to the applied voltages V _{1 to} V ₄ , the periods T _{1 to} T ₄ for applying these voltages are appropriately selected and set. However, the application of the voltage V ₁ is applied to the integrated circuit. The first period T ₁ in which the application is performed can be arbitrarily set as long as the above is merely for normal operation.

[0025] When the second period T ₂ longer is the application of a latch most affecting negative voltage V ₂ to the success or failure of up but tends to occur latch-up, exceeds a predetermined period of time (usually 10 [mu] s), the latch It does not affect the success or failure of the up.

The third period _{T 3} applies a voltage _{V 3} is also
When the voltage V ₂ is at a level higher than the limit value V _2S (small as a negative voltage value), it affects the success or failure of latch-up, but when this also exceeds a certain period (10 μs), it usually occurs. , Does not affect the success or failure of latch-up.

Since the application of the voltage V ₄ is for measuring the success or failure of latch-up, the fourth period T ₄ for applying the voltage can be appropriately set for the convenience of measurement.

In FIG. 6, the response current I ₃ corresponding to the voltage V ₃ and the voltage V ₄ when the latch-up occurs,
I ₄ is shown by a dotted line, and I ₃ and I ₄ when no response is given
Is shown by a solid line.

As described above, in the present invention, the success or failure of the latch-up is measured by measuring the response current (or the terminal voltage of the resistor connected to the integrated circuit) that conducts the integrated circuit. The success or failure of latch-up can be accurately determined without being affected by the stray capacitance.

[0030]

EXAMPLE An example of a power supply capable of generating the voltage waveform shown in FIG. 5 will be described below.

[0031]

Example 1 In Example 1, as shown in FIG. 7, one side of a DC power source with voltages V ₁ , V ₂ , V ₃ and V ₄ was connected to a common end, and each switch on the other side was connected by a relay. In this embodiment, the voltage generator is used by sequentially turning them on.

[0032] In FIG. 7, by the relay, the voltage _{V 1, V 2, V 3} , respectively each time switch only to be connected to a DC power source of the constant voltage _{V 4 T 1, T 2,} T 3, T
_In the case of sequential connection in accordance with No. ₄ , the voltage waveform shown in FIG. 5 is automatically obtained.

[0033]

Second Embodiment In the second embodiment, as shown in FIG.
₁ for a first DC power supply having a first conductor or a voltage value V
Has ₁ -V _2, the direction of applying the first power source and a second DC power supply are opposite connected selectively in series via a first switch, said first conductor and the second DC power source , A second conductor or a _third DC power supply having a voltage value V ₃ -V ₂ and applying the same direction as the first DC power supply is selectively connected in series via a second switch, a second conductor and the third DC power source, a third conductor or has a voltage value V ₃ -V _4, the direction of applied and a fourth direct current power supply is a first DC power supply and the opposite direction through the third switch In the voltage generator by selectively connecting in series, initially all switches are
Select the first conductor, the second conductor, and the third conductor, and select the first period T
₁ is turned on, the first switch is turned on for the second period T ₂
At the second DC power source side, and then the second switch from the second conducting wire to the third DC power source side so as to conduct in the third period T ₃ , and further the third switch from the third conducting wire to the third conducting wire. 4 is an example of a latch-up measurement method for an integrated circuit by transferring to a 4 DC power supply side and conducting in a fourth period T ₄ .

That is, in the second embodiment, the selection switches are connected in series one after another, but initially all the switches are selected to the first conducting wire, the second conducting wire, and the third conducting wire side, and the first period T after conducting only _1, the first switch 41 time _{T 2}
However, when it is transferred to the second power supply side, a voltage of V ₁ − (V ₁ −V ₂ ) = V ₂ is generated from the entire series circuit,

Next, a second switch 42, when was transferred from the second conductor to the third power source side, from the whole of the series circuit _{(V 3 -V 2) + V} 2 = voltage _{V 3} occurs , Then the third
When the switch 43 is moved from the third conducting wire to the fourth power supply side, V ₃ − (V ₃ −V ₄ ) is obtained from the entire series circuit.
= V ₄ voltage is generated.

The interval between the time when the first switch is switched and the time when the third switch is switched is set to the second period T ₂
When the switching time between the second switch 42 and the third switch 43 is the third period T ₃ and the pull-up time after switching the third switch is the fourth period T ₄ , it is shown in FIG. A voltage waveform will be obtained.

[0037]

Third Embodiment In a third embodiment, as shown in FIG. 9, a first DC power supply having a voltage value V ₁ , a second DC power supply having a voltage value V ₁ -V ₂ , a voltage value V ₃ -V ₂ Of the third DC power supply having the voltage value V ₃ -V ₄ and the first DC power supply having the voltage value V ₃ −V ₄
The direct current power source and the third direct current power source are in the same direction, the second direct current power source and the fourth direct current power source are in the opposite directions, and they are connected in parallel through switches and resistors having the same resistance value, respectively. In a voltage generating circuit characterized in that a voltage generating resistor is connected to an output side of a parallel circuit, a switch connected to a first DC power supply is turned on, and a first period T
_{After 1} has passed, turn on the switch connected to the second DC power supply.
N, after the second period T ₂ has passed, the switch connected to the third DC power source is turned ON, and after the third period T ₃ has passed, the switch connected to the fourth DC power source is finally turned ON, and It is an embodiment of a latch-up measuring method for an integrated circuit, which is characterized in that four periods T ₄ are passed.

That is, in the third embodiment, the parallel resistance r is provided by, for example, the first switch 41 and the second switch 42.
When turned on, both switches and the first DC power supply 2
A closed circuit is formed by the first and second DC power supplies 22, and if the parallel resistance r does not exist, an excessive current flows,
This is because the circuit will be short-circuited.

Further, each parallel resistance is set to the same resistance value r, as will be described later, when the first switch, the second switch, the third switch and the fourth switch are sequentially turned on, the respective resistances are set. This is because a voltage proportional to V ₁ , V ₂ , V ₃ , and V ₄ can be obtained for R.

In the third embodiment, first the first switch 4
When 1 is turned on, the current flowing through the resistor R is V
₁ / (r + R).

Next, when the first switch and the second switch 42 are turned on, the current conducted through the resistor R is V ₂ / (r + 2R) according to Kirlihoff's law.

Similarly, the first switch 41 and the second switch 4
2, when the third switch 43 is turned on, the current flowing through the resistor R is V ₃ / (r + 3R).

Finally, all of the first switch 41, the second switch 42, the third switch 43, and the fourth switch 44 are turned on.
When N, the current flowing through the resistor R is V ₄ /
(R + 4R).

That is, the time when the first switch 41 is first turned on is the first period T ₁ and the time when the first switch 41 and the second switch 42 are turned on is the second period T ₂ ,
The time during which the switch 41, the second switch 42, and the third switch 43 are turned on is the third period T _3, and the first switch 41
The time to ON all through fourth switch 44 to the fourth period _{T 4,} the _{V 1 (r + R) /} R, the _{V 2 (r + 2R) /} R, the _{V 3 (r + 3R) /} R, V
₄ is corrected by (r + 4R) / R times, the voltage across the resistor R has a voltage waveform shown in FIG.

[0045]

As described above, when the latch-up test method is executed using the voltage generating source of the present invention,
The values of V ₂ , V ₃ and T ₂ , T ₃ that may cause latch-up are set according to the integrated circuit to be tested and the terminal voltage, and voltage values and application times similar to this are detected in the future, On the contrary, an important standard for preventing latch-up will be obtained.

Moreover, in the present invention, since the measurement by charging the capacitor with electric charge is not performed unlike the conventional electrostatic pulse applying method, the test result is not affected by the stray inductance and the test results vary from measurement to measurement. There is no possibility of causing the drawbacks.

Therefore, the reference value of the latch-up test can be made extremely stable, and the latch-up test can be performed very easily, and the value of the present invention is great.

[0048]

[Brief description of the drawings]

FIG. 1 Circuit diagram of CMOS inverter

FIG. 2 is a side view showing the structure of a CMOS inverter.

FIG. 3 is an equivalent circuit diagram of a CMOS inverter.

FIG. 4 is an overall circuit diagram showing a situation of a latch-up test.

FIG. 5 is a graph showing a waveform of a voltage applied in the present invention.

FIG. 6 is a graph showing a difference in response currents I ₃ and I ₄ with respect to V ₃ and V _{4 in the} case where latch-up occurs and the case where latch-up does not occur (dotted line indicates a case where latch-up occurs, The solid line shows the case where latch-up has not occurred)

FIG. 7 is a circuit diagram showing an embodiment of the circuit configuration of a voltage power supply that produces the voltage waveform shown in FIG. 5 in the present invention.

FIG. 8 is a circuit diagram showing an embodiment of a circuit configuration of a voltage power supply that produces the voltage waveform shown in FIG. 5 in the present invention.

9 is a circuit diagram showing an embodiment of the circuit configuration of a voltage power supply that produces the voltage waveform shown in FIG. 5 in the present invention.

[Description of sign]

 1: Power Supply 2: Integrated Circuit 21: First Power Supply 22: Second Power Supply 23: Third Power Supply 24: Fourth Power Supply 31: First Conductor 32: Second Conductor 33: Third Conductor 41: First Switch 42: Second 2 switches 43: 3rd switch 44: 4th switch 5: resistance 6: measurement circuit

Claims (4)

(57) [Claims] 1. The first period T ₁ is a positive initial voltage V _1, and
During the second period T ₂ , a negative voltage V lower than this is applied.
_2, and the third period T ₃ is higher than the initial voltage V
_3, and a voltage having a waveform having a voltage V ₄ that is substantially equal to the initial voltage is applied to the integrated circuit during the final fourth period T ₄ , and the voltage V ₁ ,
A method for measuring latch-up of an integrated circuit based on changing the values of V ₂ , V ₃ , V ₄ and T ₁ , T ₂ , T ₃ , T ₄ . 2. _{One of} the constant-voltage DC power supplies of V ₁ , V ₂ , V ₃ , and V ₄ is connected to a common end, and only the switches on the other side of the constant-voltage DC power supplies are sequentially arranged as described above. V ₁ , V ₂ ,
The first period T ₁ and the second period V ₂ are applied to the respective DC power sources of V ₃ and V ₄ .
The latch-up measuring method according to claim 1, wherein the connection is made according to the time of the period T ₂ , the third period T ₃ , and the fourth period T ₄ . 3. A first DC power supply having a voltage value V ₁ and a second DC power supply having a first conductor or a voltage value V ₁ -V ₂ and applied in a direction opposite to the first power supply. Are selectively connected in series via a first switch, and the first conductor and the second DC power supply have the second conductor or the voltage value V ₃ -V ₂ , and the applying direction is the first DC power supply. Third in the same direction
A DC power source is selectively connected in series via a second switch, and the second conductor and the third DC power source have a third conductor or a voltage value V ₃ -V ₄ , and the direction of application is the first. A direct current power source and a fourth direct current power source in the opposite direction are selectively connected in series via a third switch, and initially all the switches are selected on the side of the first conducting wire, the second conducting wire and the third conducting wire, After conducting in the first period T ₁ , the first switch is moved to the second DC power source side in the second period T ₂ , and then the second switch is moved from the second conducting wire to the third DC power source side. , The third period T ₃
2. The latch-up measuring method for an integrated circuit according to claim 1, wherein the third switch is made conductive, the third switch is moved from the third conductor to the side of the fourth DC power supply, and the third switch is made conductive in the fourth period T ₄ . 4. A first DC power supply having a voltage value V ₁ , a second DC power supply having a voltage value V ₁ -V _2, and a voltage value V ₃ -V _2.
Third DC power supply having a fourth having a voltage value _V 3 -V ₄
Among the DC power supplies, the first DC power supply and the third DC power supply are in the same direction, the second DC power supply and the fourth DC power supply are in the opposite directions, and the switches and the resistors having the same resistance value are respectively used. Connected in parallel, a voltage generating resistor is connected to the output side of the parallel circuit, and a switch connected to the first DC power supply is turned ON, and after a lapse of the first period T ₁ , the second DC power supply is connected. Turn on the switch to be connected for the second period T
_{After 2} has passed, turn on the switch connected to the third DC power supply.
The latch-up of the integrated circuit according to claim 1, wherein after the third period T ₃ has passed, the switch connected to the fourth DC power source is finally turned on to allow the fourth period T ₄ to pass. Measuring method.