JP2777399B2 - Variable delay circuit, timing generator using the circuit, and LSI tester - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, a timing generator and an LSI tester using the circuit, and more particularly to a variable delay circuit suitable for LSI and a timing using the circuit. It relates to a generator and an LSI tester.

2. Description of the Related Art As disclosed in Japanese Patent Application Laid-Open No. 63-131720, a conventional variable delay circuit is provided with a differential pair transistor for inputting a digital signal and a grounded base pair on the collector side of the transistor pair. The digital output is taken from the collector side of the grounded base circuit pair, and the base potential of the grounded base circuit pair is varied, thereby changing the base-collector capacitance of the differential pair transistor for inputting the digital signal, and outputting from the input. Until the delay time was controlled.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the variable delay width per stage of the delay circuit is determined by the voltage dependence of the base-collector capacitance of the transistor, and the delay circuits are connected in multiple stages to obtain a large variable range. When the variable delay amount is set to zero, the residual delay time from input to output increases, so that the delay time variation with temperature and power supply variation is reduced, and the LSI with a built-in delay circuit and its There has been a difficult problem in maintaining the timing of a device using LSI with high accuracy.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable delay circuit in which a residual delay time is small and a delay amount can be weighted by a circuit incorporated in an LSI, and a timing generator and an LSI tester using the circuit.

[MEANS FOR SOLVING THE PROBLEMS] The object is to provide an input differential gate that receives a differential signal, an output differential gate that receives a differential output signal from the input differential gate, A first differential transistor pair connected in parallel to a differential output signal line between a moving gate and an output differential gate, and receiving a differential output signal on the differential output signal line; A second input which receives an output signal from the first differential transistor pair and an external control signal;
And a second differential transistor pair having an input capacitance control differential gate, which is connected in series with the transistor, and turning on the control signal to cause the first differential transistor to pass through the second transistor. When the control signal is turned off and the control signal is turned off, the second transistor is operated so that the first differential transistor pair does not operate, thereby changing the input capacitance of the first differential transistor pair. It is achieved by configuring to make it.

[Operation] When a differential signal as an input signal is input to the input differential gate, and is output from the output differential gate via the differential output signal line, the input differential signal is input from the differential output signal line. The differential output signal from the gate is configured to be input to the input capacitance control differential gate. The input capacitance control differential gate functions as a capacitive load,
When the input capacitance at the input capacitance control differential gate is variably controlled by an external control signal, the differential output signal from the input differential gate results in the throughput being slowed down according to the input capacitance. From the output differential gate, a differential signal as an input signal can be output with a desired delay while its pulse width is preserved.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 10.

FIG. 1 is a block diagram showing one embodiment of a variable delay circuit according to the present invention. In FIG. 1, a variable delay circuit includes an input differential gate 10a for inputting input signals 1a and 1b, and an output differential for inputting output signals 2a and 2b of the input differential gate 10a and outputting output signals 3a and 3b. It comprises a gate 10b and an input capacitance control differential gate 11 which receives output signals 2a and 2b of the input differential gate 10a and is controlled by a control signal 4.

A, b, and c in FIG. 2 are operation waveform diagrams of the input signals 1a and 1b, the output signals 2a and 2b of the input differential gate 10a, and the output signals 3a and 3b of the output differential gate 10b. is there. The operation of FIG.
This will be described with reference to a, b, and c of FIG. First, when the control signal 4 is at the "L" level, the input signal 1 having the waveform shown in FIG.
When a and 1b are input to the input differential gate 10a, the output signals 2a and 2b of the input differential gate 10a have the waveforms shown by the solid lines in FIG. Output signals 2a and 2b of this waveform are output differential gate 10b
And an output signal 3 having a waveform shown by a solid line in FIG.
a and 3b are obtained. Next, when the control signal 4 is set to “H” level, the input capacitance of the differential input terminal of the input capacitance control differential gate 11 increases. Therefore, the waveforms of the output signals 2a and 2b of the input differential gate 10a become the waveforms indicated by the dotted line in FIG. 2b because the input capacitance of the input capacitance control differential gate 11 is charged and discharged. The output signals 2a and 2b of this waveform are input to the output differential gate 10b, and the output signals 3a and 3 of the waveform shown by the dotted line in FIG.
b is obtained. Thus, the output signal of the input differential gate 10a is
The waveforms of the output signals 3a and 3b of the output differential gates 2a and 2b have different slew rates due to the change in the input capacitance of the input capacitance control differential gate 11, and the output signals 2a and b and the output signals 3a and 3b Since the intersections of the waveforms are shifted in time, the propagation time from the input signals 1a, 1b to the output signals 3a, 3b changes, and the delay time can be controlled. Further, even if the rise time and the fall time of the waveform differ depending on the input capacitance, the pulse width of the input waveform is preserved because of the differential input configuration.

FIG. 3 is a circuit diagram showing one embodiment of the input capacitance control differential gate 11 of FIG. In FIG. 3, the input capacitance control differential gate 11 includes transistors 12a, 12b, 12c, 12d, 12e, and 12f.
And resistors 13a, 13b, 13c and a constant current source 14. In this configuration, first, when the control signal 4 is at the “L” level, the current I of the constant current source 14 has the base potential (V _BB2 ) of the transistor 12f higher than the base potential of the transistor 12e. It flows to 12c and 12f. Therefore, no current flows through the transistors 12a and 12b, and the transistors 12a and 12b are cut off. Therefore, the input capacitance of the output signals 2a and 2b at that time is mainly the base-collector capacitance C _BC
It is. Next, when the control signal 4 is at the "H" level, the current I of the constant current source 14 is higher than the resistance of the resistor 13 because the base potential of the transistor 12e is higher than the base potential of the transistor 12f.
a, 13b and transistors 12a, 12b, 12e. Therefore, depending on the state of the output signals 2a, 2b, the transistors 12a, 12b
The current I flows through either of the two. When a current I flows through the transistors 12a and 12b, a voltage gain A _V from the base to the collector is obtained.
Occurs. Accordingly, the input capacitance of the output signals 2a and 2b is multiplied by (1 + A _V ) by the base-collector capacitance C _BC by the Miller effect to become (1 + A _V ) C _BC . As described above, the input capacity of the output signals 2a and 2b can be controlled by the control signal 4. Since the time for charging and discharging the input capacity is proportional to the input capacity, the delay time can be controlled. Therefore,
In the case of the above-described configuration of the input capacitance differential gate 11, for example, the delay circuit disclosed in Japanese Patent Application Laid-Open No. 61-242409, particularly the defect found in FIG. 1 and FIG. a transistor Q ₁ which is connected to the input signal, to the transistor Q ₂ to which is connected to the control signal are connected in parallel, the voltage level applied to the transistor Q _1, Q _2, the load capacitance generated respectively The problem that the (current values flowing through the respective transistors) change and the delay amount cannot be controlled with good accuracy has been eliminated by the variable delay circuit according to the present invention. Incidentally, as similar to the variable delay circuit according to the present invention,
A variable delay circuit disclosed as FIG. 3 in Japanese Patent Application Laid-Open No. 59-22436 is known.
Is greatly different from the configuration described above, and is disadvantageous when the variable delay circuit is configured as a monolithic IC.

FIG. 4 is a circuit diagram showing another embodiment of the input capacitance control differential gate 11 of FIG. 1 which is not directly related to the present invention.
In FIG. 4, the input capacitance control differential gate 11 includes transistors 12m, 12n, 12p, resistors 13f, 13g, and a constant current source 14. With this configuration, first, when the control signal 4 is at the “L” level, the transistor 12m is cut off, and the current I flows through one of the transistors 12n and 12p depending on the state of the output signal 2a or 2b. Therefore, a voltage gain A _V from the base to the collector of the transistors 12n and 12p is generated, and the input capacitance of the output signals 2a and 2b is multiplied by (1 + A _V ) between the base-collector capacitance C _BC by the Miller effect, and (1 + A
_V ) C _BC . Next, when the control signal 4 is at "H" level, the current I flows through the transistor 12m,
n and 12p are cut off. Therefore, the voltage gain from the base to the collector of the transistors 12m and 12p becomes zero, and the input capacitance as viewed from the base to which the output signals 2a and 2b are input becomes the base-collector capacitance _CBC . As described above, since the input capacitance of the output signals 2a and 2b can be controlled by the control signal 4, variable delay can be achieved.

FIG. 5 is a block diagram showing, for reference, a variable delay circuit not directly related to the present invention. In FIG. 5, a variable delay circuit is an input differential gate 1 for inputting input signals 1a and 1b.
0a, an output differential gate 10b that receives the output signals 2a, 2b of the input differential gate 10a and outputs output signals 3a, 3b, and a control signal that receives the output signals 2a, 2b of the input differential gate 10a. And AND gates 15a and 15b controlled by the control circuit 4. This variable delay circuit is a circuit in which the input capacitance control differential gate 11 of the embodiment of FIG. 1 is replaced with AND gates 15a and 15b.
The input capacitance of the AND gates 15a and 15b is changed by the control signal 4, and the delay time can be varied by the control signal 4 as in the embodiment of FIG.

FIG. 6 is a circuit diagram showing one embodiment of the AND gate 15a (15b) of FIG. In FIG. 6, the AND gate 15a (15
b) includes transistors 12g, 12h, 12i, 12j, 12k, and 12l, and a resistor 13
The control signal 4 is connected to the base of the transistor 12j, and one of the output signals 2a (2b) is connected to the base of the transistor 12g.
In this configuration, when the control signal 4 is at "L" level, the current I of the constant current source 14 flows through the transistors 12l and 12i and the resistor 13e, and the transistor 12g to which the output signal 2a (2b) is connected is cut off. State, so the input capacitance is
This is the collector-to-collector capacitance _CBC . Next, when the control signal 4 is at "H" level, the transistors 12g, 12h, 12k and the resistors 13d, 1
A current I flows through 3e. Therefore, a voltage gain A _V is generated between the base and the collector of the transistor 12g, and the input capacitance of the output signal 2a (2b) becomes (1 + A _V ) C _BC due to the Miller effect. As described above, since the input capacitance can be varied by the control signal 4, the delay time of the output signal 2a (2b) can be controlled.

FIG. 7 is a block diagram showing still another embodiment of the variable delay circuit not directly related to the present invention. In FIG. 7, a variable delay circuit includes an input differential gate 10a for inputting input signals 1a and 1b, and an output differential for inputting output signals 2a and 2b of the input differential gate 10a and outputting output signals 3a and 3b. Gate 10b,
It comprises a variable gain differential gate 16 which receives the output signals 2a and 2b of the input differential gate 10a and is controlled by the control signal 4. This variable delay circuit is a circuit in which the input capacitance control differential gate 11 of FIG. The input capacitance of the variable gain differential gate 16 changes according to the control signal 4, so that the delay time can be varied similarly to the embodiment of FIG.

FIG. 8 is a circuit diagram showing one embodiment of the variable gain differential gate 16 of FIG. In FIG. 8, the variable gain differential gate 16 includes transistors 12Q and 12R, resistors 13h and 13i, and a constant current source 17, and has a configuration in which the control signal 4 controls the current I of the constant current source 17. In this arrangement, the voltage gain A _V transistor 12Q, 12R and resistance 13h of the resistance value R _L, differential gate consisting 13i becomes the following equation.

_{A V = R L / 2R e} ... (1) provided that R _e transistors 12Q, a 12R emitter resistor. Here transistors 12Q, an emitter resistor R _e of 12R is given by the following equation.

_{R e = 26mV / (I /} 2) = 56mV / I ... (2) Therefore, the voltage gain A _V can be controlled by the current I of the constant current source 17. When the voltage gain A _V changes, the input capacitance viewed from the bases of the transistors 12Q, 12R changes due to the Miller effect, and the output signals 2a, 2
b Therefore, the delay time of the output signals 3a, 3b can be varied.

In the above embodiment, the input capacitance control differential gate 11 is one,
Although the number of the AND gates 15a and 15b has been described as two, the present invention is not limited by the number, and the output signal 2a for individually controlling and controlling the control signals 4 of the plurality of input capacitance control differential gates 11 is described. , 2b can be varied to control the delay time. If the voltage gain A _V by the transistor is further increased, the input capacitance change ratio becomes the voltage gain A _V
, The variable width of the delay time can be increased.

The AND gate 15 of the embodiment shown in FIGS.
a, 15b and differential gates used for input and output are normal ECL
The input capacitance control differential gate 11 of the embodiment shown in FIG. 3 and FIG.
6 can be made by changing the wiring of the AND gate 15a (15b) in FIG. Although the transistor of the above embodiment has been described as a bipolar transistor, the GaAs MESF
An ET or a hetero bipolar transistor may be used, and the present invention is not limited by the active element used.

FIG. 9 is a block diagram showing an embodiment of a timing generator using a variable delay circuit according to the present invention. In FIG. 9, the timing generator includes a synthesizer 20 for generating a reference clock 20a, a counter 18 for counting the reference clock 20a of the synthesizer 20, and a count end signal 18a of the counter 18 in one cycle of the reference clock. And a variable delay circuit 19 of the present invention for delaying. With this configuration, the reference clock 20a generated by the synthesizer 20
Is counted by the counter 18, and a counting end signal 18a is output. The variable delay circuit 19 outputs a signal obtained by analogly delaying the count end signal 18a of the counter 18 within one cycle of the reference clock 20a as a timing signal 19a. According to the present embodiment, the variable delay circuit 19 according to the present invention is the same as the counter 18.
Since it can be configured on an LSI, the size of the timing generator can be reduced.

FIG. 10 is a block diagram showing an embodiment of an LSI tester using a variable delay circuit according to the present invention. FIG. 10 shows an example of an LSI tester using the variable delay circuit according to the present invention for internal timing adjustment. The LSI tester includes a timing generator 21, a pattern generator 22, and a waveform formatter 23.
, A digital comparator 24, the variable delay circuits 19a and 19b of the present invention, a driver 25, and an analog comparator 26
This is a configuration for testing the device under test 27.

In the above configuration, the timing signal 21a generated by the timing generator 21 and the test pattern 22a generated by the pattern generator 22 are synthesized by the waveform formatter 23, and become a test waveform 23a, and the device under test via the driver 25. Give to 27. As a response to the test waveform 23a, the output signal 27a from the device under test 27 is compared with a voltage by the analog comparator 26, and converted into digital values of "0" and "1". A comparison test is performed using the expected value created by a certain pattern generator 22. An LSI tester that performs such a test checks whether the logic circuit responds within a prescribed time, together with a test that checks whether the logic operates correctly. In order to improve the time accuracy of the latter test, variable delay circuits 19a and 19b are provided between the timing generator 21, the waveform formatter 23, and the digital comparator 24 to correct delay time variations caused by manufacturing variations. I have.

According to the present embodiment, the timing generator 21, the pattern generator 22, the waveform formatter 23, the digital comparator 24, the driver 25
, An analog comparator 26, and variable delay circuits 19a, 19b
Can be configured on the LSI, and the delay amount of the variable delay circuits 19a and 19b can be controlled in a wide range, so that a small LSI tester with high accuracy can be realized at low cost.

[Effects of the Invention] According to the present invention, the input capacitance of the gate of the ECL logic LSI having the gate array structure can be controlled, so that the delay time between the input and the output can be varied, and the signal difference between the input differential gate and the output can be obtained. Since the signal only passes through the moving gate, there is an effect that the residual delay time when the delay amount is set to zero can be reduced. In addition, since the signal is handled differentially, even if the rise and fall times of the signal have different capacity dependencies, there is an effect that the pulse width of the input signal is preserved and the delay is variable. Further, since the change ratio of the input capacitance can be controlled by the voltage gain, there is an effect that an arbitrary delay time is easily generated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a variable delay circuit according to the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, and FIG.
4 is a circuit diagram of an embodiment of the input capacitance control differential gate shown in FIG.
FIG. 5 is a circuit diagram of an input capacitance control differential gate not directly related to the present invention, FIG. 5 is a block diagram showing a variable delay circuit not directly related to the present invention for reference, and FIG. 6 is an AND of FIG.
7 is a circuit diagram of an embodiment of a gate, FIG. 7 is a block diagram showing still another embodiment of a variable delay circuit not directly related to the present invention, and FIG. 8 is an embodiment of a variable gain differential gate of FIG. FIG. 9 is a block diagram showing an embodiment of a timing generator according to the present invention, and FIG. 10 is an LSI according to the present invention.
FIG. 3 is a block diagram illustrating an example of a tester. 10a …… Input differential gate, 10b …… Output differential gate, 11…
… Input capacitance control differential gate, 12a-12f, 12m-12p …… Transistor, 15a, 15b… AND gate, 16… Variable gain differential gate, 18… Counter, 19,19a, 19b… Variable delay Circuit, 20 ... synthesizer, 21 ... timing generator,
22 …… Pattern generator, 23 …… Waveform formatter, 24…
... Digital comparator, 25 ... Driver, 26 ... Analog comparator, 27 ... Device under test.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Akio Osaki 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Hitachi, Ltd. Production Technology Laboratory (56) References JP-A-59-22436 (JP, A) JP-A-61-242409 (JP, A) JP-A-62-250713 (JP, A) JP-A-61-49517 (JP, A)

Claims (3)

(57) [Claims] 1. An input differential gate receiving a differential signal, an output differential gate receiving a differential output signal from the input differential gate, and between the input differential gate and the output differential gate. A first differential transistor pair connected in parallel to the differential output signal line of
And a second differential transistor pair having a second transistor to which an output signal from the first differential transistor pair and an external control signal are input are connected in series. Operating the first differential transistor pair via the second transistor by turning on the control signal;
By turning off the control signal, the second transistor is operated so that the first differential transistor pair does not operate, thereby varying the input capacitance of the first differential transistor pair. Characteristic variable delay circuit. 2. A timing generator, wherein a counter is connected to the input side of the variable delay circuit according to claim 1. 3. The variable delay circuit according to claim 1, wherein at least a generation timing of a test waveform to the device under test and a comparison timing between a response from the device under test and a preset expected value are respectively set. An LSI tester configured to be capable of variable delay.