JPH0620130B2 - MIS transistor and manufacturing method thereof - Google Patents

Description

The present invention relates to a MIS transistor and a manufacturing method thereof.

The so-called scaling rule is famous as an index of miniaturization of MIS transistors. The scaling law requires a reduction in operating voltage and an increase in impurity concentration as well as miniaturization of size. The decrease of the operating voltage is a measure for keeping the internal electric field constant, and the increase of the impurity concentration is intended to decrease the width of the depletion layer. However, due to the diffusion potential due to the band gap of the semiconductor, the above two items are required. Scaling is not always smooth. That is, in order to reduce the width of the depletion layer by 1 / k (essential for suppressing the short channel effect), the substrate impurity concentration must be increased by k ² , and the threshold voltage V _T is kept constant. It may be an adverse effect such as a loss of mobility or a decrease in mobility. Further, the electric field in the gate insulating film is inevitably high, which is a serious problem in terms of reliability. Furthermore, MI of such a conventional structure
The electrical characteristics of the S transistor strongly depend on the substrate impurity concentration. However, as the scale down is performed, the absolute amount of impurities related to each transistor is reduced to 1 / k, which is a big problem in large-scale LSI as variation in element characteristics due to fluctuation. And before that, controlling the impurity profile is more difficult than other parameters.

As a means for avoiding such a problem, a method of forming a transistor in which a low impurity concentration thin film is formed by epitaxial growth after forming a high concentration impurity layer on the substrate surface, or a gate oxide film is formed by ion implantation or the like. There has been considered a method of compensating for impurities by introducing impurities of a type opposite to the substrate impurities into the substrate interface. By adopting such a method, the width of the depletion layer just below the gate can be made small and the surface impurity concentration can be kept low. Also, the electric field in the gate need not be too high. However, in any case, redistribution of impurities due to various subsequent thermal steps is unavoidable, and the process sensitivity becomes very high. In particular, the latter method requires control of impurities in a high concentration region, and therefore has a problem of control. Therefore, if the fluctuation of the impurity distribution is taken into consideration, it is very difficult to apply it to a large-scale circuit.

FIG. 1 is a sectional view of an example of a conventional MIS transistor.

Source and drain regions 2 and 3 of opposite conductivity type are provided on the one conductivity type semiconductor substrate 1, a gate insulating film 4 is provided on the surface thereof, and a gate electrode 5 is formed on the gate insulating film 4 to form a MIS transistor. The broken line 6 indicates the expansion of the depletion layer, and L indicates the channel width.

As shown in the figure, the channel width L is reduced due to the expansion of the depletion layer 6, and a short channel effect is produced. The short channel effect is caused by the influence of the source or the drain on the internal potential that should be controlled by the gate. Therefore, the influence of each electrode of the gate, substrate, source, and drain on the potential of each point in the interface between the semiconductor substrate and the gate insulating film and in the depletion layer when no charge is generated inside (for example, in the off state) The degree is basically determined by the distance to each electrode. For the above reason, in order to prevent the short channel effect, the distance to the gate or the substrate should be at least at each point near the source / drain midpoint.
It must be shorter than the distance to the source or drain. Therefore, in the short channel, scaling of the gate insulating film thickness Tox and the depletion layer width W _D is important.

As can be seen from the above consideration, in order to effectively suppress the short channel effect, basically Needs to be satisfied. If it is attempted to satisfy this, the conventional MIS transistor has a drawback that it is accompanied by the great difficulty as described above.

An object of the present invention is to eliminate the above-mentioned drawbacks, to determine the basic characteristics only by the spatial structure, and to realize extremely fine dimensions without being affected by the impurity concentration of the semiconductor substrate immediately below the channel.
An object is to provide an S transistor and a manufacturing method thereof.

The MIS transistor of the present invention comprises a source and drain region provided on a semiconductor substrate of one conductivity type, a gate electrode provided on the source and drain region via a gate insulating film, and a gate electrode below the gate insulating film. A semiconductor layer of one conductivity type which is provided between the source region and the drain region and has a near-intrinsic low impurity concentration, an insulating film provided below the semiconductor film, and below the insulating film and The semiconductor layer is formed so as not to come into contact with the semiconductor film and includes a one-conductivity-type semiconductor layer having an impurity concentration higher than that of the semiconductor substrate.

A method of manufacturing a MIS transistor according to the present invention includes a step of forming a silicon nitride film on a semiconductor substrate of one conductivity type, selectively removing the silicon nitride film to form an opening, and removing impurities of one conductivity type from the opening. A step of forming a one-conductivity-type semiconductor layer having a higher impurity concentration than that of the semiconductor substrate by introducing, an step of forming an insulating film on at least a part of the surface of the one-conductivity-type semiconductor layer, and the silicon nitride film. A step of removing, a step of depositing a near-intrinsic low conductivity one-conductivity-type silicon film on the surface of the semiconductor substrate and the insulating film, and a single crystal of the silicon film formed in contact with the semiconductor substrate A step of heat-treating the silicon film by using the portion as a seed to single crystal the silicon film on the insulating film; forming a gate insulating film on the surface of the silicon film on the insulating film; and forming a gate electrode on the gate insulating film. Formation That step and configured to include a step of forming source and drain regions in alignment with the gate electrode in the silicon film.

Next, examples of the present invention will be described.

First, an embodiment of the MIS transistor of the present invention will be described.

FIG. 2 is a sectional view of an embodiment of the MIS transistor of the present invention.

In this embodiment, the source and drain regions 12 and 13 are provided on the one conductivity type semiconductor substrate 11, the gate electrode 15 is provided on the source and drain regions via a gate insulating film 14, and the gate and A semiconductor film 19 provided under the insulating film and between the source region 12 and the drain region 13, an insulating film 18 provided under the semiconductor film, and not under the insulating film and in contact with the semiconductor film 19. And the one-conductivity-type semiconductor layer 17 having an impurity concentration higher than that of the semiconductor substrate 11.

In the above structure, the semiconductor layer 19 is formed at a low concentration close to that of an intrinsic semiconductor. The channel will be formed in the semiconductor layer 19. Then, the semiconductor substrate 11 is formed under the channel.
Since the semiconductor layer 17 having a higher impurity concentration is provided, the depletion layer thickness is equivalently determined only by the structure and does not depend on the drain bias. Therefore, the condition for preventing the short channel in this structure is that the thickness of the insulating film 18 is Tsub, the thickness of the semiconductor film 19 is Tsi, and the thickness of the gate insulating film 14 is Tox. Becomes

FIG. 3 is a diagram showing an energy band of the embodiment shown in FIG.

In the figure, numbers 11, 14, 15, 17, 18, 19
Correspond to the numbers shown in FIG. Also, E _C
Shows conduction band, E _F is the Fermi level, Ei is Miggyappu, E _V is the level of the upper end of the valence band, respectively. As described above, the semiconductor film 19 is a low-concentration region close to an intrinsic semiconductor, and the insulating film 18 exists thereunder, so that impurities hardly enter due to the thermal process. For this reason, there is no bending of the band, and a linear potential distribution is obtained as shown in FIG. It should be noted that this figure (a) shows the case where the gate voltage is 0 volt. Therefore, V _T of this embodiment if the work function of the gate metal and the potential difference between the Fermi level E _F and mid gap Ei substrate and B the same as that of the source and drain, Will be given in. As can be seen from equation (3), V _T is determined only by the geometrical shape of the MIS transistor if equation (2) is satisfied. In FIG. 3 (b), the gate voltage is V
_It shows that the transistor has turned on beyond _T. Further, even when the drain voltage is applied, the equivalent depletion layer width does not change, so that the basic electrical characteristics of the transistor are ultimately determined only by its geometrical shape.

As can be seen from the above operation principle, since the impurity profile does not determine the electrical characteristics, it is possible to eliminate the problems such as the decrease in mobility, variations in element characteristics, and non-linearity, which are alleviated, and at the same time, the relaxation of the gate electric field is expected. Moreover, in this structure, most of the source and drain regions are in contact with the low-concentration substrate, so that the parasitic capacitance is much smaller than in the case where the entire surface has the same structure as that under the gate metal. Further, back channel leakage, which is often a problem in a simple SOI structure, can be effectively suppressed by applying a negative substrate bias.

Next, an example of the method of manufacturing the MIS transistor of the present invention will be described. In the following description, one conductivity type will be described as P type. In the case of N type, all conductivity types may be reversed.

4 (a) to 4 (f) are cross-sectional views showing the order of steps for explaining the method for manufacturing the MIS transistor of the present invention.

First, as shown in FIG. 4 (a), the impurity concentration is 1 × 10 ¹⁵
A field oxide film 20 is formed on the P-type semiconductor substrate 11 of / cm _{3 by} a normal LOCOS method.

Next, as shown in FIG. 4 (b), a thickness of 10 is obtained by thermal oxidation.
After the insulating film 18 having a thickness of about 0Å is grown, the silicon nitride film 21 is deposited to a thickness of about 3000Å by the CVD method. Then, in the future, the silicon nitride film 21 in the portion where the gate electrode 15 is located is selectively removed to form an opening, and a boron dose of 1
High concentration semiconductor layer 17 by ion implantation at about 0 ¹⁵ / cm ₃
To form. If the ion implantation energy is selected to be about 20 KeV, the semiconductor layer 17 is formed only in the opening portion.

Next, as shown in FIG. 4 (c), the insulating film 18 has a thickness of 3
After thermal oxidation until it reaches 00Å, all nitride film 2
1 is removed, and then etching is performed under the condition that the insulating film 18 is etched by about 100 Å. Then, the semiconductor layer 1
An insulating film 18 having a thickness of about 200 Å remains on top of 7.

Next, as shown in FIG.
It is deposited to a thickness of 0Å and selectively removed so that it exists only between the field oxide films 20. Deposited silicon layer 19
The part directly contacting the semiconductor substrate 11 is a single crystal, and the part contacting the insulating film 18 is a polycrystal. Next, a beam annealing method using a laser beam or an electron beam or LESS (Lateral Epitaxy by Seeded Soli
-dification) method is used to single crystallize the polycrystalline silicon portion using the single crystal portion as a seed.

Next, as shown in FIG. 4 (e), the gate insulating film 14 is grown to a thickness of about 200Å on the surface of the semiconductor film 19, and the gate electrode 15 is formed thereon. The gate electrode 15 is formed of, for example, boron-doped polysilicon. The gate electrode 15 is masked and arsenic is ion-implanted to form source and drain regions 12 and 13.

Next, as shown in FIG. 4 (f), a silicon oxide film 22 is grown by a CVD method to form a contact hole, and then a metal wiring 23 is formed.

The MIS transistor of the present invention can be manufactured as described above. The structure shown in FIG. 4 (f) is equivalent to the structure shown in FIG. 2 and has the same operation and effect. According to the manufacturing method of the present invention, the minimum channel length can be reduced to about 0.1 μm, and the semiconductor layer 17 and the insulating film 1 can be miniaturized.
And 8 can be formed by self-alignment.

As described in detail above, according to the present invention, the basic characteristics are determined only by the spatial structure, and it is possible to obtain a MIS transistor having an extremely fine size without being affected by the impurity concentration of the semiconductor substrate immediately below the channel. The effect is great.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an example of a conventional MIS transistor, FIG. 2 is a cross-sectional view of an embodiment of the MIS transistor of the present invention, and FIG. 3 is a diagram showing energy bands of the embodiment shown in FIG. 4 (a) to 4 (f) are sectional views showing the order of steps for explaining one embodiment of the method for manufacturing a MIS transistor of the present invention. 1 ... Semiconductor substrate, 2, 3 ... Source and drain regions, 4 ... Gate insulating film, 5 ... Gate electrode, 11 ...
One-conductivity type semiconductor substrate, 12, 13 ... Source and drain regions, 14 ... Gate insulating film, 15 ... Gate electrode,
17 ... One conductivity type semiconductor layer, 18 ... Insulating film, 19 ...
Semiconductor film, 20 ...... field oxide film, 21 ...... silicon nitride film, 22 ...... silicon oxide film, 23 ...... metal wire, _{E C} ...... lower level of the conduction band, _{E F} ...... Fermi level, Ei ... … Mid gap, E _V …… The upper level of the valence band.

Claims (2)

[Claims] 1. A source and drain region provided on a semiconductor substrate of one conductivity type, a gate electrode provided on the source and drain region via a gate insulating film, and below the gate insulating film. A one conductivity type semiconductor film having a low impurity concentration which is provided between the source region and the drain region and is close to the intrinsic region, an insulating film provided below the semiconductor film, and a semiconductor film provided below the insulating film and at the semiconductor film. A MIS transistor, which is provided so as not to come into contact with the semiconductor substrate and includes one conductive type semiconductor layer having a higher impurity concentration than the semiconductor substrate. 2. A step of providing a silicon nitride film on a semiconductor substrate of one conductivity type, selectively removing the silicon nitride film to form an opening, and introducing an impurity of one conductivity type from the opening. Forming a one conductivity type semiconductor layer having a higher impurity concentration than the substrate, forming an insulating film on at least a part of the surface of the one conductivity type semiconductor layer, and removing the silicon nitride film, Depositing a near-intrinsic low conductivity one-conductivity type silicon film on the surface of the semiconductor substrate and the insulating film; and using a single crystal portion of the silicon film formed in contact with the semiconductor substrate as a seed A step of heat-treating the silicon film to make the silicon film on the insulating film into a single crystal; a step of forming a gate insulating film on the surface of the silicon film on the insulating film and forming a gate electrode on the gate insulating film. , The silicon film MIS transistor fabrication method characterized by comprising the step of forming the source and drain regions in alignment with the gate electrode.