JPH0620007A - Lsi layout device extracting method - Google Patents

Abstract

PURPOSE:To provide a highly precise device parameter calculating method which can select a calculation expression based on a prescribed grammar with no intervension of manual operations nor addition of a layout pattern. CONSTITUTION:The graphic data 1 are inputted and a device type 3 is selected. The calculation expression candidates are selected out of those designated by a user (11) in a calculation expression selection process 14. Then a device shape is analyzed in a device analysis process 5. A calculation expression is decided in a calculation expression selection process 8 if the device has a simple rectangular shape. If the device has a trapezoidal shape, the number 7 of graphics is decided and the corresponding calculation expression is decided in the process 8. Then the device parameter is calculated based on the decided calculation expression. The result of this calculation is turned into the data to be transferred to the net list processing in a net list parameter production process 10. In such a constitution, the extracting precision of the device parameter can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection information (hereinafter referred to as a netlist) for verifying electrical connection of an LSI layout and a method for extracting device parameters.

[0002]

2. Description of the Related Art As shown in FIG. 13, an LSI layout device extraction method is composed of a layer extraction section 12, a device parameter calculation section 13, and a netlist creation section 14.

In the layer extraction portion 12, a device area is extracted from the overlap of the LSI layout mask layers, and a layer is assigned to the extracted shape. That is, one layer is assigned to one set of overlays.

The device parameter calculation unit 13 calculates device parameters such as channel length and channel width from the graphic information such as the area and perimeter of the extracted graphic.

The netlist creating section 13 refers to the result of the device parameter and adds information in the process of restoring the connection information.

FIG. 14 shows a detailed flow of processing for one device figure of parameter calculation (12 in FIG. 13) in the conventional system.

In the conventional system, based on only the type of device to be extracted, for example, the classification of MOS, BJT, etc. (19 in FIG. 14), a single calculation built into the system is used ( It is possible to allow the user to freely specify the calculation formula to some extent by the method of calculating the device parameter (21 in FIG. 14) (21 in FIG. 14) or by the user specification 23.
A method of assigning one calculation formula to one layer in 20 parts for one layer therein is used to perform uniform calculation.

[0008]

In the conventional method, devices having the same mask making process are extracted as the same layer,
The device parameters were calculated by a single formula regardless of the application and the required accuracy. For example,
The formulas for calculating the channel length and channel width of a MOS device created in the shape (here, type 1) shown in FIG. 2 are distinguished from the formulas for calculating the MOS device (type 2) shown in FIG. I couldn't.

Even in the conventional system in which the user can assign the calculation formula, in order to accurately recognize, the type 1 and the type 2 device extraction layers are manually identified in order to identify them separately. The pseudo layout pattern (24 in FIG. 4) was input in advance, and it had to be defined in another layer by the layer extraction 12 before entering the calculation process 13.

According to this method, since an extra layer is used to input the pseudo layout pattern, the pseudo layout pattern is input for each device having a different shape. Enter.

Therefore, the management of the layer number for the actual pattern becomes troublesome. In addition, since the input of the pseudo layout is manually relied on for each device, human error is likely to occur, and there is a problem that the error is hard to be detected only because of the problem of calculation accuracy. .

The object of the present invention was made in view of the above-mentioned problems, and it is a highly accurate calculation formula using a predetermined grammar without human intervention and without adding layers to a layout pattern. And to provide a method for calculating device parameters.

[0013]

A feature of the present invention is that an LSI
A layer is assigned to one set of mask pattern information of the layout mask layer group as an extracted device figure, and a device including a channel length and a channel width is obtained from figure information including an area and a perimeter of the extracted figure. In an LSI layout device extraction method for calculating a parameter and restoring the connection information of an LSI layout by referring to the result of the parameter, the complexity of the shape of the extracted device figure is determined by the number of simple rectangles or trapezoids forming a device. And a function that can independently specify a calculation formula for calculating the device parameter corresponding to the number of the simple rectangles or trapezoids of the extracted device figure, To have.

Also, a function of determining the complexity of the shape of the extracted device figure by a predetermined grammar by designating the number of areas of simple rectangles or trapezoids forming a device, and the trapezoid of the extracted device figure It is possible to have a function of independently designating a calculation formula for calculating the device parameter corresponding to the number of areas.

[0015]

The present invention will be described in detail with reference to the drawings. The present invention is applied to the device parameter calculation portion 13 shown in FIG.

The device parameter calculation part 13 of the present invention
The detailed flow of the above is shown in FIG.

First, the graphic data 1 shown in FIG. 1 can be specifically expressed as follows. FIG. 5 shows a concept of extracting a device shape from an actual layout pattern.

The patterns 25 and 26 are the extracted device shapes, respectively. Type 2 with complicated device shape
At the time of this extraction, such a transistor is expressed as a set of a plurality of trapezoids as shown in FIG.

In the user designation 11, the number of figures forming the device can be designated based on a predetermined grammar. For example, as shown in FIG. 7, it is specified that the calculation formula can be changed depending on the number of trapezoids forming the device.
In FIG. 7, the device definition 27 assigns a layer name of nch-aa as a device gate figure in which the device type corresponds to a layer name. The device parameter equation 28 can be extracted from the basic information of the layer graphic (here, NCH SD LENGTH is the source + drain length of the device graphic, CRICUMFER).
ENCE OFGATE represents the perimeter of the device. ), It is the part that describes the calculation formula how to calculate the channel length and the channel width.

The number of figures, which is a feature of the present invention, is KOS.
It is represented by the variable U. The calculation formula 29 is a calculation formula in the case of a simple rectangle, and the calculation formula 30 is a calculation formula in the case of a device composed of a plurality of trapezoids.

The device figure input 2 is used to input this one device at a time. By the process 3, as in the conventional method,
Determine the device type. Based on the flow determination 3, the calculation formula selection 14 from the input from the user specification 11
Narrow down the calculation formula candidates. The shape is further analyzed by the device graphic analysis 5. First, it is determined whether or not the device is a type 1 device in the determination 6 whether the device is a simple rectangle.

If it is the type 1, in the calculation formula selection 28,
The calculation formula for Type 1 is read from the user input, and the calculation 9
Then, the device parameter value is calculated. If the type is other than type 1, it is determined how many trapezoids the device is made of by the number 7 of figures, and the process branches depending on the type of user-specified 11. A predetermined calculation formula is selected in calculation formula selection 2 and calculation is performed. The calculation result is created by the netlist parameter creation 10 as data to be passed to the netlist processing 14. This process is repeated for all devices.

The following describes how a specific device is selected and calculated.

For example, the transistor shown in FIG.
It is composed of two trapezoids. This corresponds to the calculation formula 30 shown in FIG. 7. According to the flow of the present invention, the calculation formula selection 14 narrows down to a transistor, and the calculation formula is selected by the number 7 of figures and the calculation formula selection 28 to calculate the device parameter value.

Further, consider a resistance element made of polysilicon as shown in FIG. It is assumed that the user estimates that the channel width becomes thicker than the case where the adjacent pattern is a simple rectangle due to the resistance bending, and specifies as shown in FIG. According to the method of the present invention, the calculation formula selection 14 is a resistance so that the number of figures is 7, and the calculation formula selection 28 is 10 figures.
Select and calculate the above formula.

Next, a second embodiment of the present invention will be described.

In the analysis of the graphic complexity of the present invention, the calculation formula is selected according to the graphic area instead of the above-mentioned number of graphics. Figure 10
Shows the flow of processing. Compared with the previous embodiment, the area 31
Is the changed part.

The user makes the designation shown in FIG. When the capacitor shown in FIG. 12 is input, the calculation formula 32 of FIG. 11 is selected as the layout pattern 34 and the calculation formula 33 of the layout pattern 35 is selected depending on the area.

[0029]

As described above, the shape of the device is analyzed by executing the device figure analysis process during the device parameter calculation process, and the optimum formula for the device is selected from the user's specifications by the shape determination process. To do.

Therefore, according to the present invention, the device parameters can be accurately extracted without adding a pseudo layout pattern to the LSI layout. from now on,
As the miniaturization of LSI layout design progresses, the accuracy of the device of the actual layout pattern with respect to the estimation becomes a problem at the time of verification. In addition, the shape of the device may be limited due to the problem of chip space.
Considering that the sag near the pattern boundary and the distortion depending on the shape occur due to the interference at the time of exposure, the method according to the present invention that allows the user to freely assign the calculation formula according to the design shape is an effective method. Has the effect of providing.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a detailed processing flow of a layout device extraction method of the present invention.

FIG. 2 is a pattern diagram showing a simple rectangular transistor.

FIG. 3 is a pattern diagram showing a transistor composed of polygons.

FIG. 4 is a pattern diagram showing a pseudo pattern input example.

FIG. 5 is a diagram showing an image of device figure extraction.

FIG. 6 is a pattern diagram showing a polygonal transistor having a trapezoidal shape.

FIG. 7 is a diagram showing an example of user designation of transistors.

FIG. 8 is a pattern diagram showing a resistance element.

FIG. 9 is a program list showing an example of user designation of resistors.

FIG. 10 is an explanatory diagram showing a processing flow of the second embodiment.

FIG. 11 is a diagram showing an example of user designation of capacity.

FIG. 12 is a pattern diagram showing a capacitive element.

FIG. 13 is an explanatory diagram showing a processing flow of a layout device extraction method according to the present invention and a conventional example.

FIG. 14 is an explanatory diagram showing a detailed processing flow of a conventional layout device extraction method.

[Explanation of symbols]

 1 Graphic data 2 Device graphic input 3 Device type 4 Calculation formula selection 1 5 Device graphic analysis 6 Simple rectangle or 7 Number of graphics 8 Calculation formula selection 2 9 Calculation 10 Netlist parameter creation 11 User specification 12 Layer extraction 13 Device parameter Calculation 14 Netlist creation

Claims (2)

[Claims] 1. A layer length is assigned to a set of mask pattern information of an LSI layout mask layer group as an extracted device figure, and a channel length is calculated from figure information including the area and perimeter of the extracted figure. LS that calculates device parameters including the channel width and the channel width and restores the connection information of the LSI layout by referring to the results of the parameters.
In the I-layout device extraction method, a function of determining the complexity of the shape of the extracted device graphic by a predetermined grammar that specifies the number of simple rectangles or trapezoids that make up the device, and the simple extraction of the extracted device graphic An LSI layout device extracting method, which has a function of independently designating a calculation formula for calculating the device parameter corresponding to the number of rectangles or trapezoids. 2. A function of determining the complexity of the shape of the extracted device figure by a predetermined grammar by designating the number of areas of simple rectangles or trapezoids forming a device, and the trapezoid of the extracted device figure. 2. The LSI layout device extracting method according to claim 1, further comprising a function of independently designating a calculation formula for calculating the device parameter corresponding to the number of areas.