JPH10162047A - Circuit extraction device and method therefor, and simulation information generation system and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract a circuit information capable precisely reproducing the drain current and the gate capacity of actual device in a circuit simulation. SOLUTION: A transistor part shape-recognition means 1 recognizes the shape of a transistor part from a mask layout data 11 and generates transistor part shape data 12. A transistor size calculation means 2 obtains an equivalent transistor size, by which drain current matches with drain current in the real device and outputs it as transistor size data 14. A correction capacity generation means 3 obtains the difference of gate capacity between circuit simulation using the equivalent transistor size and the actual device, and virtually generates correction capacity having a capacity value equivalent to the obtained difference. An net list output means 4 reflects transistor size data 14 and correction capacity data 17 on a net list 18 as circuit information used for circuit simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit extracting device and a circuit extracting method for extracting circuit information from a mask layout used in designing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, large scale integrated circuits (LSIs) typified by microprocessors have been rapidly increasing in performance and integration with progress in process technology and design technology. In order to realize a high-performance, highly integrated LSI, it is required to design a circuit with high accuracy.
n) Tools play an important role.

A circuit simulator is one of the CAD tools that are deeply involved in the design accuracy. A circuit simulator is designed for a designed LSI, and includes connection information of elements such as MOS transistors, capacitance, resistance, and inductance, and characteristic information such as transistor size (transistor width, transistor length), capacitance, resistance, and inductance. Based on the netlist including the above, simulation is performed assuming a real device (an actually manufactured LSI). The netlist can be extracted from a designed LSI mask layout by a circuit extracting device, for example.

FIG. 14 shows a conventional LSI simulation using a circuit extracting device and a circuit simulator.
The following description is directed to an example in which the MOS transistor shown in FIG.

FIG. 14 shows an example of a MOS transistor mask layout. As shown in FIG.
The OS transistor 90 includes four terminals: a gate 91, a source 92, a drain 93, and a substrate 94. 9
Reference numerals 5 and 96 are contacts for connection to the source 92 and the drain 93, respectively. W is the transistor width (gate width), and L is the transistor length (gate length).

First, a netlist as shown in FIG. 15 is extracted from the mask layout shown in FIG. 14 by a circuit extracting device. The netlist shown in FIG.
It describes the S-transistor 90 and includes data on transistor size (transistor width W, transistor length L).

Next, a circuit simulator shown in FIG.
The circuit simulation is performed based on the netlist shown in FIG. The circuit simulator determines the drain current and the gate capacitance of the MOS transistor 90 shown in FIG. 14 based on the transistor size data included in the netlist shown in FIG. 15, and reproduces the operation of the actual device.

[0008]

However, there have been the following problems in the prior art.

In the conventional circuit extracting apparatus, a netlist in which the drain current and the gate capacitance of the MOS transistor can be accurately reproduced in the circuit simulation by the circuit simulator cannot be extracted from the mask layout.

In an actual device, even if the transistor size (transistor width, transistor length) is equal, if the shape of the transistor portion (gate) is different, the drain current and the gate capacitance of the MOS transistor are not necessarily equal. However, in a normal circuit simulator, MOS transistors having the same transistor size (transistor width and transistor length) are treated as having the same drain current and gate capacitance.

FIG. 16 is a diagram showing another example of a MOS transistor mask layout, and shows a MOS transistor 90A in which a transistor portion (gate) 91 is bent. Here, the MOS transistor 9 shown in FIG.
0 and the MOS transistor 90A shown in FIG. 16, the transistor width W and the transistor length L are assumed to be equal. In this case, in the actual device,
Although the drain current and the gate capacitance are different between the MOS transistor 90 and the MOS transistor 90A due to the difference in the shape of the transistor portion 91, the circuit simulator determines that the MOS transistor 90 and the MOS transistor 90A are different.
A is treated as having the same drain current and gate capacitance.

[0012] In the netlist, to improve the accuracy of the drain current in the circuit simulation, the MOS
When the transistor size of the transistor is corrected, the accuracy of the gate capacitance is reduced in the circuit simulation. On the other hand, when the transistor size of the MOS transistor is corrected in order to increase the accuracy of the gate capacitance, the accuracy of the drain current decreases.

That is, conventionally, it has not been possible to generate a netlist in which both the drain current and the gate capacitance can be accurately adjusted to an actual device, and therefore, there is a problem that a highly accurate circuit simulation cannot be performed. there were.

In view of the above-mentioned problems, the present invention provides a circuit extracting apparatus and a circuit extracting method for extracting circuit information used for circuit simulation from a mask layout. It is an object to make it possible to extract circuit information that can be reproduced.

[0015]

Means for Solving the Problems In order to solve the above problems, means according to the first aspect of the present invention extracts circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit. As an apparatus for extracting a circuit, a transistor included in the semiconductor circuit, based on the shape of the transistor including a curve, recognized from the mask layout, based on the shape of the transistor including a curve, and an equivalent transistor whose gate capacitance matches in a circuit simulation and an actual device. A size is calculated, and a correction current source having a current value corresponding to a difference between a drain current in a circuit simulation using the equivalent transistor size and a real device is virtually generated, and the equivalent transistor size and the correction current source are calculated. Data for circuit simulation It is an circuit information.

According to the first aspect of the present invention, the difference in the gate capacitance between the circuit simulation and the actual device due to the difference in the shape of the transistor portion, the shape of the transistor portion having a curve, and the like is determined by the equivalent transistor size. Can be eliminated by
The difference in the drain current between the circuit simulation and the actual device due to the difference in the shape of the transistor part, the shape of the transistor part having a curve, and the adjustment of the gate capacitance according to the equivalent transistor size is corrected. This can be eliminated by virtually generating the current source. For this reason, even when a mask layout in which the shape of a transistor portion is represented by a curve is to be subjected to circuit extraction, such as a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, an equivalent transistor size and a correction current source are obtained. Therefore, the equivalent transistor size and the correction current source in consideration of the finished shape can be extracted as circuit information used for circuit simulation. By using the equivalent transistor size and the data of the correction current source as circuit information used for circuit simulation, it is possible to accurately reproduce both the drain current and the gate capacitance of the transistor in the circuit simulation.

The invention according to claim 2 is based on the first aspect.
As a circuit extracting device for extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, a transistor is recognized from the mask layout, and the transistor is recognized. A transistor portion shape recognizing means for recognizing the shape of the transistor portion of the transistor including a curve included in the shape, and a gate capacitance of the transistor in a circuit simulation based on the shape of the transistor portion recognized by the transistor portion shape recognizing device. Means for calculating an equivalent transistor size that matches the gate capacitance of the transistor in an actual device; and a circuit simulation using the equivalent transistor size obtained by the transistor size calculation means. It determines the difference between the drain current of the transistor in the tio emission and actual device, in which and a correction current source generating means for generating virtually the correction current source having a current value corresponding to the calculated difference.

In order to solve the above-mentioned problem, a measure taken by the invention according to claim 3 is to extract a circuit for extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit. As a simulation information generation system including a device and parameter extraction means for extracting parameters used for circuit simulation from information such as process information of the semiconductor circuit, the circuit extraction device includes a transistor included in the semiconductor circuit, Based on the shape of the transistor including the curve, recognized from the mask layout,
An equivalent transistor size that matches the gate capacitance between the circuit simulation and the actual device, and outputs the obtained equivalent transistor size as circuit information to be used in the circuit simulation. It is assumed that the equivalent transistor size obtained by the above is used as an input, and a parameter that matches the drain current of the transistor in a circuit simulation using the equivalent transistor size and an actual device is extracted.

According to the third aspect of the present invention, the difference in the gate capacitance between the circuit simulation and the actual device caused by the difference in the shape of the transistor portion and the shape of the transistor portion having a curve is obtained by the circuit extraction device. The equivalent transistor size can be eliminated by using it as circuit information, and the shape of the transistor part is different, the shape of the transistor part has a curve, etc., and the gate capacitance is adjusted according to the equivalent transistor size. The difference between the drain current in the circuit simulation and the drain current in the actual device is determined by the parameter extraction means so that the parameter in the circuit simulation using the equivalent transistor size and the parameter in the actual device match the drain current of the transistor. It can be eliminated by out. Therefore, even in the case of a mask layout in which the shape of the transistor portion is represented by a curve, such as a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, both the drain current and the gate capacitance of the transistor in the circuit simulation are required. It can be reproduced with high accuracy.

According to a fourth aspect of the present invention, there is provided a circuit extracting method for extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit. For a transistor having a transistor, based on the shape of the transistor including the curve, which is recognized from the mask layout, based on the shape of the transistor, the equivalent transistor size is determined so that the gate capacitance matches between the circuit simulation and the actual device. By virtually generating a correction current source having a current value corresponding to the difference between the drain current in the circuit simulation used and the actual device, circuit information using the equivalent transistor size and the data of the correction current source in the circuit simulation And .

According to the fourth aspect of the present invention, the difference in the gate capacitance between the circuit simulation and the actual device due to the difference in the shape of the transistor portion, the shape of the transistor portion having a curve, etc. Can be eliminated by
The difference in the drain current between the circuit simulation and the actual device due to the fact that the shape of the transistor part is different, the shape of the transistor part has a curve, and the fact that the drain current is adjusted by the equivalent transistor size is corrected. This can be eliminated by virtually generating the current source. For this reason, even when a mask layout in which the shape of a transistor portion is represented by a curve is to be subjected to circuit extraction, such as a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, an equivalent transistor size and a correction current source are obtained. Therefore, the equivalent transistor size and the correction current source in consideration of the finished shape can be extracted as circuit information used for circuit simulation. By using the equivalent transistor size and the data of the correction current source as circuit information used for circuit simulation, it is possible to accurately reproduce both the drain current and the gate capacitance of the transistor in the circuit simulation.

The invention according to claim 5 is based on claim 4.
As a circuit extraction method for extracting circuit information used for circuit simulation from a mask layout that takes into account the finished shape of a semiconductor circuit after manufacturing, a transistor is recognized from a mask layout,
A transistor part shape recognizing step of recognizing the shape of the transistor part of the recognized transistor including a curve included in the shape.Based on the shape of the transistor part recognized in the transistor part shape recognizing step, the transistor A transistor size calculation step of determining an equivalent transistor size such that a gate capacitance matches the gate capacitance of the transistor in the actual device; and a circuit simulation using the equivalent transistor size determined by the transistor size calculation step and the actual device. A correction current source generating step of obtaining a difference between the drain currents of the transistors and virtually generating a correction current source having a current value corresponding to the obtained difference.

[0023] Further, a solution taken by the invention of claim 6 is a circuit extracting step of extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit; A parameter extracting step of extracting a parameter used for a circuit simulation from information such as process information. The method for generating a simulation includes a step of extracting a circuit included in the semiconductor circuit from the mask layout. A step of obtaining an equivalent transistor size such that gate capacitances match in a circuit simulation and an actual device based on the shape of the transistor having a curve, and wherein the parameter extracting step is performed by the circuit extracting step. Equivalent transition The drain current of the transistor in the circuit simulation and actual devices using Tasaizu is one that has a step of extracting parameters to match.

According to the sixth aspect of the present invention, the difference in the gate capacitance between the circuit simulation and the actual device due to the difference in the shape of the transistor portion, the shape of the transistor portion having a curve, and the like is determined by the circuit extraction step. The equivalent transistor size can be eliminated by using it as circuit information, and the shape of the transistor part is different, the shape of the transistor part has a curve, etc., and the gate capacitance is adjusted according to the equivalent transistor size. The difference in the drain current between the circuit simulation and the actual device caused by the above-described problem is determined by extracting a parameter that matches the drain current of the transistor between the circuit simulation using the equivalent transistor size and the actual device in the parameter extraction step. It can be eliminated by. For this reason, even when a mask layout in which the shape of a transistor portion is represented by a curve is targeted, such as a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, the drain current and the gate of the transistor in an actual device in a circuit simulation. Both capacities can be accurately reproduced.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a circuit extracting apparatus according to a first embodiment of the present invention. As shown in FIG. 1, a circuit extraction device 10 according to the present embodiment includes a transistor part shape recognizing unit 1, a transistor size calculating unit 2, a correction capacitance generating unit 3,
And a netlist output means 4.

In this embodiment, the transistor size (transistor width, transistor length) is calculated based on the drain current of the actual device, and the difference between the gate capacitance obtained from the calculated transistor size and the gate capacitance of the actual device is corrected. The accuracy of the circuit simulation is improved by reflecting the capacitance in the netlist.

First, the flow of data between components in the circuit extracting apparatus 10 shown in FIG. 1 will be described.

The transistor part shape recognizing means 1 reads the mask layout data 11, performs recognition of the MOS transistor and the shape of the transistor part, and outputs transistor part shape data 12. The transistor size calculation means 2 reads the transistor part shape data 12, obtains an equivalent transistor width and an equivalent transistor length, which will be described later, from an analytical expression 13a by referring to a calculation or reference table 13b, and outputs it as transistor size data 14. The correction capacitance generation means 3 reads the transistor part shape data 12 and the transistor size data 14, obtains a correction capacitance, which will be described later, from an analytical expression 15a by referring to a reference or a reference table 15b, and outputs it as correction capacitance data 17. The netlist output means 4 reads the transistor size data 14 and the correction capacitance data 17 and outputs a netlist 18.

Next, the operation of each component in the circuit extracting apparatus 10 shown in FIG. 1 will be described in detail.

First, the operation of the transistor section shape recognition means 1 will be described.

The transistor part shape recognizing means 1 reads the mask layout data 11, and recognizes a MOS transistor having four terminals of a gate, a source, a drain and a substrate from the read mask layout data 11. When the MOS transistor is recognized, the shape of the transistor portion of the recognized MOS transistor is recognized.

FIG. 2 is a simplified diagram of a mask layout of a MOS transistor, showing the types of shapes of a transistor portion. In FIG. 2, reference numeral 60 denotes a diffusion region;
1 is a polysilicon region. The transistor unit 62
Generally, it is defined as a region where the diffusion region 60 and the polysilicon region 61 overlap (in FIG.
Is shaded). In the description of the present embodiment, it is assumed that the shape of the transistor portion 62 is roughly classified, for example, as shown in FIGS. In FIG. 2, as examples of the shape of the transistor portion, (a) is a linear shape, (b) is a 90-degree bent shape, (c) is a discontinuous shape, (d) is a 45-degree bent shape, and (e) The parentheses indicate the transistor length variations.

The transistor section shape recognizing means 1 obtains the vertex coordinates of the transistor section 62 and compares the X and Y coordinates of the obtained vertex coordinates to obtain the transistor section 6.
Recognize shape 2. And the recognized transistor part 6
2 is classified into, for example, one of FIGS. 2 (a) to 2 (e).

The transistor shape recognizing means 1 outputs the recognition result as transistor shape data 12. Table 1 shows an example of the transistor part shape data 12.

[0036]

[Table 1]

In the example shown in Table 1, the transistor part shape data 12 includes a transistor identification number, a transistor part shape classification code, and transistor part vertex coordinates. The transistor identification number is a number assigned to each recognized MOS transistor. The transistor part shape classification code is a code for classifying the shape of the transistor part 62. In the example of Table 1, the linear shape shown in FIG. 2A is "a", and the 90-degree bent shape shown in FIG. Are set as "b", and the discontinuous type shown in FIG. 2 (c) is set as "c". The transistor part vertex coordinates are coordinate information (X, Y) composed of two-dimensional X and Y coordinates representing each vertex of the transistor part 62, which is used when calculating the transistor size. Since there is a difference in the number of vertices depending on the shape of the transistor unit 62, the number of coordinate information also differs depending on the shape of the transistor unit 62. For example, the classification code a (the linear shape shown in FIG. 2A) has four pieces of coordinate information, and the classification code b (the 90-degree bent shape shown in FIG. 2B) has six pieces of coordinate information.

Next, the operation of the transistor size calculating means 2 will be described.

As described above, the transistor size calculation means 2 calculates the transistor size (transistor width, transistor length) based on the drain current of the actual device. The calculated transistor size is called equivalent transistor size (equivalent transistor width, equivalent transistor length).

The transistor size calculation means 2 first reads the transistor part shape data 12. Next, in order to make the drain current equivalent to the drain current of the actual device, the analysis formula 13a or the reference table 1 is used for each MOS transistor of the read transistor shape data 12.
Using 3b, an equivalent transistor width W and an equivalent transistor length L are calculated so that the drain current becomes equivalent to the drain current of the actual device.

Here, to make the drain current equivalent to the drain current of the actual device means to match the relationship between the transistor size, the shape of the transistor portion 62, and the drain current which differ for each manufacturing process. That is, the circuit simulator determines the drain current based on the given transistor size and the capability of the manufacturing process. As described in the section of the problem, the circuit simulator simulates the difference in the drain current due to the difference in the shape of the transistor unit 62. Cannot be reflected in the results. For this reason,
To improve the apparent accuracy of the circuit simulator,
The difference in drain current due to the difference in the shape of the transistor portion 62 is reflected in the transistor size to make the drain current equivalent to the drain current of the actual device.

As the value of the drain current of the actual device,
A value obtained by a process simulator, a device simulator, or the like that can reflect an actual measurement value or a difference in the shape of the transistor portion in a simulation result is used.

If the obtained drain current of the actual device can be converted into a function, the analytical expression 13a is used. If the function is difficult, the reference table 13b is used.

First, the case where the analytic expression 13a is used will be described. When the analytic expression 13a is used, the target MO
S transistor transistor shape classification code (Table 1)
) Is selected from the analytic formula 13a, and the dimensions such as the length of each side of the transistor portion are obtained from the apex coordinates (shown in Table 1) of the transistor portion of the MOS transistor. By substituting the dimensions into an analytical expression selected from analytical expressions 13a, an equivalent transistor width W and an equivalent transistor length L of the MOS transistor are obtained.
Is calculated.

For the transistor part shapes shown in FIGS. 2A to 2E, an analytical expression 13a for obtaining an equivalent transistor width W and an equivalent transistor length L is, for example, as follows. FIG. 2 (a) (W, L) = (W1, L1) (b) (W, L) = (W1 + W2 + Kx.times.Wx, L1) (c) (W, L) = (W1 + W2 + Kx) × Wx, L1) (d) (W, L) = (W1 + W2 + W3 + Kx × Wx + Ky × Wy, L1) (e) (W, L) = (W1, L1), (W2, L2), (Kx × Wx, Ky × (L1 + L2) / 2) (1) where W1, W2, W3, Wx, and Wy are the transistor widths of the respective portions represented by the length of the center line of the transistor portion 62,
L1 and L2 are the transistor lengths of the respective parts, as shown in FIG.
To (e). Kx and Ky are correction coefficients for reflecting the difference in drain current due to the difference in the shape of the transistor section 62 on the transistor size. Note that the difference in drain current due to the difference in the shape of the transistor portion 62 differs depending on the LSI manufacturing process.
The correction coefficients Kx and Ky differ depending on the LSI manufacturing process.

A MOS transistor having a transistor shape as shown in FIGS. 2A to 2D is represented by a circuit 70 composed of one transistor as shown in FIG. For the MOS transistor having a transistor section shape in which the transistor length changes as shown in FIG. 4, the transistor section 62 is divided for each transistor length, and a plurality of transistors 70a, 70b, 70c connected in parallel as shown in FIG. Is represented by a circuit 70. Each divided transistor can be treated in a circuit simulation in the same manner as a non-divided transistor. Therefore, as shown in equation (1), FIG.
For the transistor part shape shown in (e), it is necessary to calculate three sets of equivalent transistor widths W and equivalent transistor lengths L, respectively. 3 and 4, 71 is a gate,
72 is a source, 73 is a drain, and 74 is a substrate.

It should be noted that an arbitrary function using each dimension of the transistor section 62 as a variable may be used as the analytical expression 13a. For example, for the transistor portion shapes shown in FIGS. 2A to 2E, the equivalent transistor width W is obtained by the following equation. The same applies to the equivalent transistor length L. FIG. 2 (a) W = functiona (W1, L1) (b) W = functionb (W1, W2, Wx, L1) (c) W = functionc (W1, W2, Wx, L1) (d) W = functiond (W1, W2, W3, Wx, Wy, L1) (e) ... W = functione (W1, W2, Wx, L1, L2) (2) functiona to functione are equivalent transistors in each transistor shape, respectively. This is a function representing the width W.

Next, the case where the reference table 13b is used will be described. In the reference table 13b, for example, a table that describes an equivalent transistor width W and an equivalent transistor length L corresponding to each dimension of the transistor section 62 is prepared for each transistor section shape classification code. The transistor size calculation means 2 searches the reference table 13b using information such as the transistor part shape classification code and the transistor part vertex coordinates of the transistor part shape data 12, and reads out a predetermined equivalent transistor width W and a predetermined equivalent transistor length L.

Table 2 is a table showing an example of a table prepared in the reference table 13b. In Table 2, the transistor width W1 for the transistor portion shape shown in FIG.
The equivalent transistor width W for the combination of W2 is described.

[0050]

[Table 2]

When the reference table 13b is used, if there is no appropriate dimension value in the prepared table, the equivalent transistor width W and the equivalent transistor length L are approximately obtained by interpolation or extrapolation.

Therefore, when the reference table 13b is used, the equivalent transistor size (equivalent transistor width and equivalent transistor length) is determined more accurately as more data is prepared assuming the shape and transistor size of the transistor section 62. be able to.

The data of the equivalent transistor size (equivalent transistor width, equivalent transistor length) obtained as described above is output as transistor size data 14. Table 3 shows an example of the transistor size data 14. In Table 3, equivalent transistor width W and equivalent transistor length L for each transistor identification number
It is shown.

[0054]

[Table 3]

Next, the operation of the correction capacity generating means 3 will be described. The correction capacitance generating means 3 includes a transistor 62
And the transistor size calculation means 2
Then, a difference in gate capacitance between the circuit simulation and the actual device, which is caused by adjusting the transistor size, is obtained, and a correction capacitance having a capacitance value corresponding to the obtained difference is virtually generated. Specifically, the capacitance value of the correction capacitance is obtained by subtracting the gate capacitance calculated based on the equivalent transistor size calculated by the transistor size calculation means 2 from the measured value of the gate capacitance and the like.

First, the correction capacity generating means 3 reads the transistor shape data 12 obtained by the transistor shape recognizing means 1 and the transistor size data 14 obtained by the transistor size calculating means 2.

Next, the gate capacitance of each MOS transistor is calculated based on the equivalent transistor width and the equivalent transistor length included in the transistor size data 14.
There are three types of gate capacitance: gate-source capacitance, gate-drain capacitance, and gate-substrate capacitance, each of which is determined based on the analytical expression 15a or the lookup table 15b. Then, the obtained gate capacitance and the actually measured value data 16
The difference from the gate capacitance of the actual device of the device is determined, and this difference is used as the capacitance value of the correction capacitance.

In the following description, the capacitance between the gate and the source, the capacitance between the gate and the drain, and the capacitance between the gate and the substrate of the actual device are Cgs1, Cgd1, and Cgb1, respectively, and are based on the equivalent transistor width W and the equivalent transistor length L. The obtained gate-source capacitance, gate-drain capacitance, and gate-substrate capacitance are represented by Cgs2 and Cgd, respectively.
2, Cgb2.

The gate capacitances Cgs1, Cgd1, and Cgb1 of the actual device included in the measured value data 16 are not only differences in gate capacitance due to differences in transistor size and manufacturing process capability, but also differences in gate capacitance due to differences in the shape of the transistor portion 62. Are observable, and are obtained by actual measurement, process simulation, device simulation, and the like.

Table 4 is a table showing an example of the actually measured value data 16. The measured value data 16 is prepared for each shape of the transistor section 62, and Table 4 shows the gate capacitance of the actual device for the linear transistor shape shown in FIG.

[0061]

[Table 4]

On the other hand, the gate capacitance based on the equivalent transistor width W and the equivalent transistor length L is obtained as follows.

First, the case where the analytical expression 15a is used will be described. The analytic expression 15a includes the gate-source capacitance Cgs2,
Arbitrary functions that represent the equivalent transistor width W and the equivalent transistor length L, which represent the gate-drain capacitance Cgd2 and the gate-substrate capacitance Cgb2, respectively, are prepared. That is, each gate capacitance is expressed as follows in the analytical expression 15a. Cgs2 = functiongs (W, L) Cgd2 = functiongd (W, L) Cgb2 = functiongb (W, L) (3) Functiongs, functiongd, and functiongb are functions representing gate capacitance. As a function representing the gate capacitance,
For example, a function used for a gate capacitance model of a MOS transistor built in a circuit simulator is used.

The correction capacitance generation means 3 calculates a predetermined gate capacitance by substituting the equivalent transistor width W and the equivalent transistor length L of the transistor size data 14 into the analytical expression 15a.

Next, a case where the reference table 15b is used will be described. The look-up table 15b stores the gate and gate for the combination of the equivalent transistor width W and the transistor length L.
Source-to-source capacitance Cgs2, gate-to-drain capacitance Cgd2,
And a gate-substrate capacitance Cgb2. Table 5
Is a table showing an example of the reference table 15b.

[0066]

[Table 5]

The correction capacitance generating means 3 searches the reference table 15b using the equivalent transistor width W and the equivalent transistor length L of the transistor size data 14, and reads out a predetermined gate capacitance. If there is no value matching the combination of the equivalent transistor width W and the equivalent transistor length L in the lookup table 15b, the gate capacitance is approximately obtained by the interpolation method or the extrapolation method.

Next, a correction capacitance is determined from the gate capacitance of the actual device and the gate capacitance determined based on the equivalent transistor size. The gate-source correction capacitance is ΔCgs,
Assuming that the gate-drain correction capacitance is ΔCgd and the gate-substrate correction capacitance is ΔCgb, each correction capacitance is obtained by the following equation. ΔCgs = Cgs1−Cgs2 ΔCgd = Cgd1−Cgd2 ΔCgb = Cgb1−Cgb2 (4)

(Specific Calculation Example) The calculation of the correction capacitance will be described using specific numerical values. Here, the MOS transistor recognized from the mask layout data 11 by the transistor part shape recognizing means 1 has a linear transistor part shape as shown in FIG. 2A, and both the transistor width W1 and the transistor length L1 1.0
(Μm).

First, the equivalent transistor width W of the MOS transistor is calculated by the transistor size calculating means 2.
And the equivalent transistor length L are obtained. Here, it is assumed that the equivalent transistor width W and the equivalent transistor length L are obtained as in the following equation according to the analytical equation 13a shown in equation (1).

(W, L) = (W 1, L 1) = (1.0, 1.0)

Next, the capacitance value of the correction capacitance is calculated by the correction capacitance generation means 3. The gate capacitance of the actual device is
If it is determined according to the actual measurement value data 16 shown in Table 4, Cgs1 = 1.01 Cgd1 = 1.01 Cgb1 = 1.01 On the other hand, the gate capacitance based on the equivalent transistor size can be calculated from, for example, the analytical expression 15a as follows: Cgs2 = functiongs (W, L) = functiongs (1.
0,1.0) = 1.0 Cgd2 = functiongd (W, L) = functiongd (1.
0,1.0) = 1.0 Cgb2 = functiongb (W, L) = functiongb (1.
(0,1.0) = 1.0. Therefore, from equation (4), the correction capacitance is given by ΔCgs = Cgs1−Cgs2 = 1.01-1.0 = 0.01 ΔCgd = Cgd1−Cgd2 = 1.01−1.0 = 0.01 ΔCgb = Cgb1−Cgb2 = 1.01-1.0 = 0.01.

The capacitance value of each correction capacitance obtained as described above is output as correction capacitance data 17. Table 6
Is a table showing an example of the correction capacitance data 17. In Table 6, three correction capacitances ΔCgs,
ΔCgd and ΔCgb are described.

[0074]

[Table 6]

Since the gate capacitance has a characteristic that the capacitance value varies depending on the applied voltage, a netlist for further improving the accuracy of the circuit simulation can be obtained by considering the analysis formula 15a or the reference table 15b in consideration of this characteristic. Can be generated.

Next, the operation of the netlist output means 4 will be described in detail.

The net list output means 4 reads the transistor size data 14 and the correction capacitance data 17 and
From the transistor size data 14, the equivalent transistor size of each MOS transistor (equivalent transistor width W,
The equivalent transistor length L) is read out, and the MOS transistor having the equivalent transistor size is described in the netlist 18. Also, from the correction capacity data 17, each MO
The correction capacitance of the S transistor, that is, the gate-source correction capacitance ΔCgs, the gate-drain correction capacitance ΔCgd, and the gate-substrate correction capacitance ΔCgb are read, and the read correction capacitances are described in the netlist 18.

FIG. 5 shows a net list 18 according to the present embodiment.
3 is a circuit diagram showing a connection relationship of MOS transistors described in FIG. In FIG. 5, reference numeral 80 denotes a gate-source correction capacitance, 81 denotes a gate-drain correction capacitance, and 82 denotes a gate-substrate correction capacitance.

FIG. 6 is a diagram showing an example of the net list 18 generated by the net list output means 4. FIG.
, The line beginning with “M” indicates a MOS transistor, the first item is a transistor identification number,
Item 5 is the terminal number of the MOS transistor, and item 6 is the MOS transistor
Transistor type, 7th term is equivalent transistor width, 8th
The term is the equivalent transistor length. The row beginning with “C” indicates the capacity (correction capacity in this case), the first term is the capacity identification number, the second and third terms are two terminals to which the capacity is connected, and the fourth term is the capacity value. is there.

As described above, according to the circuit extracting apparatus of the present embodiment, the drain current is adjusted to the actual value by obtaining the equivalent transistor size (equivalent transistor width and equivalent transistor length), and the gate current is adjusted. Since the capacitance is adjusted to the actual value by virtually determining the correction capacitance, it is possible to output a netlist that can accurately reproduce the physical quantities of both the drain current and the gate capacitance in the circuit simulation.

In this embodiment, the transistor size calculation means 2 and the correction capacity generation means 3 are configured to selectively use the analysis formula and the reference table. However, the configuration using only one of the analysis formula and the reference table is used. It may be.

In this embodiment, only the MOS transistor and the correction capacitance are described in the netlist. In addition to this, information on the shape (area, peripheral length) of the source and drain of the transistor, Parasitic capacitance such as wiring capacitance, wiring resistance, contact resistance, parasitic resistance such as source resistance and drain resistance, or parasitic inductance may be extracted from the mask layout and described in the netlist.

Further, in the present embodiment, the net list is generated by the net list output means 4, but the transistor size data 14 and the correction capacitance data 17 themselves can be used as output data of the circuit extracting apparatus according to the present embodiment. Good.

FIG. 7 is a block diagram showing a configuration of a modification of the circuit extracting apparatus according to the present embodiment. In FIG.
The circuit extracting device 10A is a circuit extracting device 1 shown in FIG.
0 does not include the netlist output means 4 and directly outputs the transistor size data 14 obtained by the transistor size calculation means 2 and the correction capacitance data 17 obtained by the correction capacitance generation means 3 to the outside. ing. When using the extraction device 10A of the circuit shown in FIG. 7, by replacing all the transistor size data with the transistor data 14 and adding the correction capacitance data 17 to the conventional netlist,
A netlist 18A similar to the netlist 18 output from the circuit extracting device shown in FIG. 1 can be generated. At this time, the transistor size data 14 output from the conventional netlist and circuit extraction device 10A is used.
In some cases, the transistor identification numbers do not always coincide with each other in the correction capacitance data 17. In this case, the correspondence may be obtained by using software for comparing the netlists.

(Second Embodiment) FIG. 8 is a block diagram showing a configuration of a circuit extracting apparatus according to a second embodiment of the present invention. As shown in FIG. 8, the circuit extracting device 20 according to the present embodiment includes a transistor part shape recognizing means 6 capable of recognizing the shape of a transistor part with respect to a mask layout in consideration of a finished shape, a transistor size calculating means 7, , Correction capacity generation means 8 and netlist output means 9
The first embodiment differs from the first embodiment in that a netlist can be extracted from a mask layout in consideration of a finished shape. The netlist output unit 9 is the same as the netlist output unit 4 included in the circuit extracting device 10 according to the first embodiment shown in FIG.

FIGS. 9 (a) to 9 (e) show FIGS.
M manufactured based on the mask layout shown in FIG.
FIG. 3 is a simplified diagram illustrating a shape of an OS transistor.

In general, a mask layout consists of a combination of straight lines. However, when an actual device is manufactured based on a mask layout as shown in FIG. 2, for example, FIG.
It is finished in the shape including the curve as shown in. This difference between the mask layout and the finished shape has a subtle effect on the operation of the actual device. As the manufacturing process becomes finer, the difference between the mask layout and the finished shape increases. Therefore, the influence of the finished shape on the operation of the actual device increases as the process becomes finer and cannot be ignored.

In the present embodiment, in consideration that the difference between the mask layout and the finished shape affects the operation of the actual device, the mask layout is converted in advance in consideration of the finished shape of the actual device, and the converted mask layout is obtained. On the other hand, by obtaining the equivalent transistor size and the correction capacitance, the accuracy of the circuit simulation is further improved as compared with the first embodiment.

First, the flow of data between components in the circuit extracting apparatus 20 shown in FIG. 8 will be described.

The transistor part shape recognizing means 6 reads the converted mask layout data 21 and recognizes the MOS transistor and the shape of the transistor part.
The transistor shape data 22 is output. The transistor size calculation means 7 calculates the transistor shape data 22
Is read, and the calculation or reference table 2 is calculated from the analytical expression 23a.
3b, an equivalent transistor width and an equivalent transistor length are obtained and output as transistor size data 24. The correction capacitance generating means 8 reads the transistor part shape data 22 and the transistor size data 24,
The correction capacity is calculated from the analytical expression 25a or the reference table 25 is calculated.
b, and output as the correction capacity data 27. The netlist output means 9 reads the transistor size data 24 and the correction capacitance data 27 and outputs a netlist 28.

The converted mask layout data 21 is generated from an original mask layout by using a function of a process simulator capable of simulating a finished shape after a manufacturing process in detail.

Next, the operation of the transistor portion shape recognizing means 6 will be described in detail. The difference from the transistor section shape recognizing means 1 included in the circuit extracting device 10 according to the first embodiment shown in FIG. 1 is that even if the contour of the transistor section is a curve, the shape can be recognized.

The transistor part shape recognizing means 6 reads the converted mask layout data 21 and recognizes a MOS transistor having four terminals of gate, source, drain and substrate. In the mask layout data 21 after conversion, the mask layout of the MOS transistor is shown in FIG.
(A) to (e). As in the first embodiment, the transistor portion 62 (hatched in FIG. 9) is defined as a region where the diffusion region 60 and the polysilicon region 61 overlap.

After recognizing the MOS transistor, the transistor portion shape recognizing means 6 recognizes the shape of the transistor portion 62 of the recognized MOS transistor. Then, the recognized shape of the transistor portion 62 is changed, for example, as shown in FIG.
To (e). In FIG. 9, as examples of the shape of the transistor portion 62, (a) is a linear shape, (b) is a 90-degree bent shape, (c) is a discontinuous shape, (d) is a 45-degree bent shape, e) shows the transistor length variation type, respectively.

The transistor part shape recognizing means 6 outputs the recognition result as transistor part shape data 22. The transistor part shape data 22 represents a curve fitted when the original mask layout is converted and the converted mask layout data 21 is generated, in addition to the transistor identification numbers and the transistor part shape classification codes shown in Table 1. It consists of an equation and the coordinates of the start point and the end point of the curve. The start point coordinates and the end point coordinates of the curve are coordinate information (X, Y) composed of two-dimensional X and Y coordinates used when a transistor size is obtained later.

Next, the operation of the transistor size calculation means 7 will be described in detail. The difference from the transistor size calculation means 2 included in the circuit extraction device 10 according to the first embodiment shown in FIG. 1 is that the transistor section shape data 22 including the curve equation and the start point coordinates and end point coordinates of the curve are also accurate. The point is that the equivalent transistor size can be calculated well.

The transistor size calculation means 7 first reads the transistor shape data 22. Next, for each MOS transistor of the read transistor shape data 22, the equivalent transistor width W and the equivalent transistor length L such that the drain current becomes equivalent to the drain current of the actual device are obtained by analyzing the analytical expression 23a or the reference table 23b. Determine using

The analytic expression 23a is different from the circuit according to the first embodiment shown in FIG. 1 in that an analytic expression is provided for each of the transistors having the same shape, and for each of the start point coordinates and the end point coordinates of the outline curve. Is different from the analytical expression 13a in the extraction device 10 of FIG. Therefore, by using the analytic expression 23a, the equivalent transistor size at which the drain current is accurately reproduced is calculated for each of the transistors having the same shape and having different contour curve expressions and different start point coordinates and end point coordinates of the curves. be able to.

Further, the reference table 23b is also represented by the analytical expression 23a.
Similarly, for the transistors having the same shape, a table is provided for each of the contour curve formulas and the start point coordinates and end point coordinates of the contour curve.

Next, the operation of the correction capacity generating means 8 will be described in detail. The difference from the correction capacitance generation means 3 included in the circuit extraction device 10 according to the first embodiment shown in FIG. 1 is that the transistor section shape data 22 including the contour curve equation and the start point coordinates and the end point coordinates of the curve are accurate. The point is that the correction capacity can be calculated well.

As in the case of the transistor size calculation means 7, the specific calculation operation is as follows: the expression of the contour curve, the analytical expression 25a considering the start point coordinates and the end point coordinates of the contour curve, and the reference table 2
5b.

As described above, according to the circuit extracting apparatus of this embodiment, the equivalent transistor size and the correction capacitance can be obtained for the mask layout converted in consideration of the finished shape of the actual device. ,
In the circuit simulation, it is possible to extract a netlist that can reproduce the drain current and the gate capacitance more accurately than in the first embodiment.

In this embodiment, as shown in FIG. 9, the outline is curved by performing the mask layout conversion only on the polysilicon region 61. However, the mask layout conversion is also performed on the diffusion region and the wiring region. It doesn't matter.

In the present embodiment, the transistor size calculation means 7 and the correction capacity generation means 8 are configured to use the analytic formula and the reference table, respectively. However, the configuration uses only one of the analytic formula and the reference table. It may be.

In this embodiment, only the MOS transistor and the correction capacitor are output to the netlist. In addition to this, information on the shape (area, peripheral length) of the source and drain of the transistor, Parasitic capacitance such as wiring capacitance, wiring resistance, contact resistance, parasitic resistance such as source resistance and drain resistance, or parasitic inductance may also be extracted from the mask layout and output to the netlist.

Further, in the present embodiment, the net list is generated by the net list output means 9, but as in the modification of the first embodiment shown in FIG. May be output data of the circuit extraction device according to the present embodiment.

(Third Embodiment) FIG. 10 shows a third embodiment of the present invention.
It is a block diagram showing the composition of the circuit extraction device concerning an embodiment. The circuit extraction device 30 according to the present embodiment illustrated in FIG. 10 includes a transistor part shape recognition unit 1 and a netlist output unit 4 that are common to the circuit extraction device 10 according to the first embodiment illustrated in FIG. It comprises a size calculation means 31 and a correction current source generation means 32.

In the first and second embodiments, the equivalent transistor size (equivalent transistor width and equivalent transistor length) is determined so that the drain currents match between the circuit simulation and the actual device, and the circuit based on the determined equivalent transistor size is obtained. The difference in gate capacitance between the simulation and the actual device was used as the correction capacitance.

On the other hand, in the present embodiment, the equivalent transistor size (equivalent transistor width and equivalent transistor length) is determined so that the “gate capacitance” matches between the circuit simulation and the actual device, and the equivalent transistor size is determined based on the determined equivalent transistor size. The difference between the “drain current” between the circuit simulation and the actual device is represented by a “correction current source”.

The flow of data between components in the circuit extracting apparatus 30 according to the present embodiment shown in FIG. 10 will be described.

First, the transistor part shape recognizing means 1
The mask layout data 11 is read, and the recognition of the MOS transistor and the shape of the transistor portion are performed.
The transistor shape data 12 is output. The transistor size calculation means 31 calculates the transistor part shape data 1
2 is read, an equivalent transistor width and an equivalent transistor length such that the gate capacitances match in the circuit simulation and the actual device are calculated from the analytical formula 33a or by referring to the lookup table 33b, and output as transistor size data 34. Correction current source generating means 32
Reads the transistor shape data 12 and the transistor size data 34, virtually calculates a correction current source, which will be described later, from the analytical expression 35 a or refers to the lookup table 35 b, and outputs the correction current source as the correction current source data 37. The netlist output means 4 outputs the transistor size data 3
4 and the corrected current source data 37 are read, and a net list 38 is output.

Next, the operation of each component in the circuit extracting device 30 shown in FIG. 10 will be described. Regarding the transistor part shape recognition means 1 and the netlist output means 4,
The description is omitted here because it is similar to the first embodiment.

The transistor size calculation means 31 first reads the transistor part shape data 12. Next, each MOS included in the read transistor shape data 12
For the transistor, the equivalent transistor width W and the equivalent transistor length L such that the gate capacitance becomes equivalent to the gate capacitance of the actual device are obtained by the analysis formula 33a or the reference table 3.
3b.

As the value of the gate capacitance of the actual device, an actual measurement value or a value obtained by a process simulator, a device simulator, or the like capable of reflecting a difference in the shape of the transistor portion in the simulation is used. If the obtained gate capacitance of the actual device can be converted into a function, the analysis formula 33a is used. Analysis expression 33a and lookup table 33b
Is used in the same manner as in the first embodiment, and the description is omitted here.

The correction current source generation means 32 determines that the shape of the transistor portion is different for each MOS transistor on the mask layout for which the equivalent transistor size (equivalent transistor width and equivalent transistor length) has been determined, and that the transistor size calculation means 31 The difference from the drain current of the actual device caused by the matching of the transistor size and the like is obtained, and a corrected current source having a current amount corresponding to the obtained difference is virtually generated.

More specifically, the correction is performed by subtracting the drain current calculated based on the equivalent transistor size (equivalent transistor width and equivalent transistor length) obtained by the transistor size calculation means 31 from the measured value of the drain current and the like. Obtain the current amount of the current source.

The correction current source generating means 32 first reads the transistor shape data 12 obtained by the transistor shape recognizing means 1 and the transistor size data 34 obtained by the transistor size calculating means 31.

Next, the drain current of each MOS transistor is calculated based on the equivalent transistor width and the equivalent transistor length included in the transistor size data 34. This drain current is obtained using the analytical expression 35a or the reference table 35b. Then, a difference between the obtained drain current and the actual drain current included in the measured value data 36 is obtained, and a current source having a current amount corresponding to the difference is virtually generated as a correction current source.

Table 7 is a table showing an example of the actually measured value data 36. The measured value data 36 is prepared for each shape of the transistor portion. Table 7 shows the actual drain current IDS for the linear transistor portion shape shown in FIG.

[0120]

[Table 7]

FIG. 11 is a diagram showing the connection relationship of the MOS transistors described in the netlist 38. FIG.
In the figure, 85 is a MOS transistor, and 86 is a virtually generated correction current source. As shown in FIG. 11, the correction current source 86 is provided in parallel with the MOS transistor 85, and the direction of the current of the correction current source 86 is larger than the drain current of the actual device which is obtained based on the equivalent transistor size. At this time (when the current difference is “+”), the direction of the drain current of the MOS transistor 85 is the same as that of the MOS transistor 85, and when the drain current of the actual device is smaller than the drain current obtained based on the equivalent transistor size (the current When the difference is "-"), the direction of the drain current of the MOS transistor 85 is opposite.

As described above, according to the apparatus for extracting a semiconductor circuit according to the present embodiment, the gate capacitance can be adjusted to the actual value by obtaining the equivalent transistor size (equivalent transistor width and equivalent transistor length). Since the drain current can be adjusted to the actual value by virtually finding the correction current source, a netlist that can reproduce both the physical quantity of the drain current and the gate capacity with high precision in circuit simulation is masked. It can be extracted from the layout data.

Here, the present embodiment will be compared with the first embodiment.

First, in the first embodiment, when the difference between the gate capacitance of the actual device and the gate capacitance obtained based on the equivalent transistor size is positive, this difference in the gate capacitance is determined by the virtual correction capacitance. It can be expressed, but when the difference in gate capacitance is negative, this difference in gate capacitance cannot be reflected in the netlist. This is because there is no capacity whose capacity value is negative. On the other hand, in the present embodiment, even if the difference between the drain current of the actual device and the drain current obtained based on the equivalent transistor size is positive or negative, this difference in the drain current is virtually assumed. It can be reflected in the netlist by the correction current source. This is because the sign of the difference between the drain currents can be represented by the direction of the current of the correction current source.

In the first embodiment, the gate capacitance is adjusted by the correction capacitance having a constant capacitance value.
It is difficult to handle the voltage dependence of the gate capacitance. First
In the embodiment, the gate capacitance value at the operating voltage (for example, 5 V, 3 V) of the circuit is obtained, but the actual gate capacitance changes depending on the gate voltage. On the other hand, in the present embodiment, the voltage dependency of the capacitance can be handled.

In this embodiment, the transistor size calculation means 31 and the correction current source generation means 32 are configured to use the analysis formula and the reference table, respectively. However, only one of the analysis formula and the reference table is used. It may be configured.

In this embodiment, only the MOS transistor and the correction current source are output to the netlist. In addition to these, the source and the transistor of the transistor are output.
Information on the shape (area, perimeter) of the drain, parasitic capacitance such as wiring capacitance, parasitic resistance such as wiring resistance, contact resistance, source resistance, drain resistance, or parasitic inductance is also extracted from the mask layout and output to the netlist. It is good also as composition which performs.

Further, in this embodiment, the net list is generated by the net list output means 4. However, as in the modification of the first embodiment shown in FIG. May be used as output data.

Further, as in the second embodiment, in consideration of the fact that the difference between the mask layout and the finished shape affects the operation of the actual device, the mask layout is converted in advance in consideration of the finished shape of the actual device. Then, by obtaining the equivalent transistor size and the correction current source for the converted mask layout, it is possible to further improve the accuracy of the circuit simulation.

In this case, in the circuit extracting apparatus according to the present embodiment shown in FIG. 10, the transistor section shape recognizing means 1 is made capable of recognizing the shape of the transistor section even if the contour of the transistor section is a curve. 31
Can be calculated with high accuracy even if the transistor part shape data 12 includes the equation of the curve and the coordinates of the start point and the end point of the curve (the analytical expression 33a or the reference table 33b is used to define the contour in the transistor part shape). Considering the equation of the curve and the coordinates of the start point and the end point), the correction current source generating means 32 can accurately calculate the correction current even if the transistor shape data 12 includes the equation of the curve and the start point coordinates and the end point coordinates of the curve. Source can be generated virtually (analysis expression 35a
Alternatively, the reference table 35b is made to take into account the equation of the contour curve in the transistor part shape, the start point coordinates and the end point coordinates), and the mask layout data converted in consideration of the finished shape of the semiconductor circuit instead of the mask layout data 11 is given. I just need.

(Fourth Embodiment) FIG. 12 is a diagram schematically showing a simulation information generation system according to a fourth embodiment of the present invention. As shown in FIG. 12, the simulation information generation system according to the present embodiment includes a circuit extraction device 40 and parameter extraction means 53, and a circuit simulator 55 generally generates a circuit A circuit simulation is performed using the netlist 45 extracted by the extraction device 40 and the parameter 54 extracted by the parameter extraction means 53 from the transistor characteristics 51 and the process information 52 as information.

In the first to third embodiments, a netlist 45 is generated by the circuit extracting device 40 so that both the drain current and the gate capacitance can be accurately reproduced in a circuit simulation.
Was used as before.

On the other hand, according to the present embodiment, the equivalent transistor size (equivalent transistor width and equivalent transistor length) is determined in order to match the gate capacitance with the actual value, and is reflected in the netlist 45. Is adjusted based on the equivalent transistor size (equivalent transistor width and equivalent transistor length) to adjust the parameter 54 to the value of. In other words, the information corresponding to the correction current source virtually generated in the third embodiment is reflected in the parameter 54. In FIG. 12, the flow of data of the equivalent transistor size (equivalent transistor width and equivalent transistor length) from the circuit extraction device 40 to the parameter extraction means 53 is indicated by a broken line.

FIG. 13 is a block diagram showing the configuration of the circuit extracting device 40 in the simulation information generating system according to the present embodiment. In FIG. 13, first,
The transistor part shape recognizing means 1 reads the mask layout data 11, performs recognition of the MOS transistor and the shape of the transistor part, and outputs transistor part shape data 12. Transistor size calculation means 3
1 reads the transistor part shape data 12, calculates the equivalent transistor width and the equivalent transistor length such that the gate capacitances match between the circuit simulation and the actual device from the analytical expression 33a or obtains the equivalent transistor width by referring to the reference table 33b. Output as data 34. The net list output means 4 reads the transistor size data 34 and outputs a net list 45.

The circuit extracting device 40 shown in FIG. 13 is different from the circuit extracting device 30 according to the third embodiment shown in FIG. 10 in that it does not include the correction current source generating means 32. Therefore, unlike the netlist 38 shown in FIG. 10, the netlist 45 does not include information on the correction current source. The operations of the transistor part shape recognizing means 1, the transistor size calculating means 31, and the netlist output means 4 are the same as in the third embodiment, and the description is omitted here.

The circuit extracting device 40 outputs the transistor part shape data 12 and the transistor size data 34 to the parameter extracting means 53. Parameter extraction means 53
Is the equivalent transistor size (equivalent transistor width, equivalent transistor length) in the transistor size data
, The parameters 54a, 54
b, 54c.

As described above, according to the present embodiment, the gate capacitance can be adjusted to the actual value by determining the equivalent transistor size and reflecting it in the netlist, and further, the drain current can be adjusted to the equivalent transistor size. Since the parameters can be used to correct the parameters, they can be adjusted to the actual values, so that the physical quantities of both the drain current and the gate capacitance can be reproduced with high accuracy in the circuit simulation.

Further, as in the second embodiment, in consideration of the fact that the difference between the mask layout and the finished shape affects the operation of the actual device, the mask layout is previously converted in consideration of the finished shape of the actual device. Then, the equivalent transistor size is obtained for the converted mask layout, and the parameter is corrected using the equivalent transistor size, whereby the accuracy of the circuit simulation can be further improved.

In this case, in the circuit extracting device 40 in the simulation information generating system according to the present embodiment shown in FIG.
Can be recognized even if the contour of the transistor portion is a curve, and the transistor size calculation means 31 can be equivalently accurately determined even if the transistor portion shape data 12 includes the equation of the curve and the start point coordinates and the end point coordinates of the curve. After the transistor size can be calculated (the analysis formula 33a or the reference table 33b takes into account the contour curve formula and the start point coordinates / end point coordinates in the transistor part shape), the mask layout data 11 is replaced. May be provided with mask layout data converted in consideration of the finished shape of the semiconductor circuit.

[0140]

As described above, according to the present invention, in a circuit simulation, circuit information (equivalent transistor size and correction capacity, correction current source or Parameters) can be extracted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a circuit extracting device according to a first embodiment of the present invention.

FIGS. 2A to 2E are simplified diagrams of a mask layout of a MOS transistor, and are diagrams showing types of shapes of a transistor portion.

FIG. 3 is a circuit diagram corresponding to the MOS transistors shown in FIGS.

FIG. 4 is a circuit diagram corresponding to the MOS transistor shown in FIG.

FIG. 5 is a circuit diagram showing a connection relation of MOS transistors described in a netlist according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a netlist according to the first embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a modified example of the circuit extracting device according to the first embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a circuit extracting device according to a second embodiment of the present invention.

FIGS. 9A to 9E are simplified diagrams showing a finished shape of a MOS transistor manufactured based on the mask layout shown in FIGS. 2A to 2E.

FIG. 10 is a block diagram showing a configuration of a circuit extracting device according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram showing a connection relationship of MOS transistors described in a netlist according to a third embodiment of the present invention.

FIG. 12 is a schematic diagram of a simulation information generation system.

FIG. 13 is a block diagram showing a configuration of a circuit extraction device according to a fourth embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of a mask layout of a MOS transistor.

15 is a netlist extracted from the mask layout of the MOS transistor shown in FIG.

FIG. 16 is a diagram showing another example of a mask layout of a MOS transistor, showing a MOS transistor in which a transistor portion (gate) is bent.

[Explanation of symbols]

 1,6 Transistor part shape recognizing means 2,7,31 Transistor size calculating means 3,8, Correction capacity generating means 4,9 Netlist output means 10,10A, 20,30,40 Circuit extraction device 11 Mask layout data 12 , 22 Transistor shape data 13a, 23a, 33a Analytical expressions 13b, 23b, 33b Reference tables 14, 24, 34 Transistor size data 15a, 25a, 35a Analytical expressions 15b, 25b, 35b Reference tables 16, 26, 36 Actual measured values 17 , 27 Correction capacitance data 18, 18A, 28, 38, 45 Netlist 21 Converted mask layout data 32 Correction current source generation means 37 Correction current source data 53 Parameter extraction means 54, 54a, 54b, 54c Parameters 55 Circuit simulator 62 Tra Transistor section 80, 81, 82 correction capacity 86 correction current source

Claims (6)

[Claims] 1. A circuit extracting device for extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, wherein a transistor included in the semiconductor circuit is recognized from the mask layout. Based on the shape of the transistor including the curve, an equivalent transistor size such that the gate capacitance matches in the circuit simulation and the actual device is obtained, and the drain in the circuit simulation using the equivalent transistor size and the actual device is determined. A circuit extracting apparatus, wherein a corrected current source having a current value corresponding to a current difference is virtually generated, and the equivalent transistor size and the data of the corrected current source are used as circuit information used for circuit simulation. . 2. A circuit extraction device for extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, comprising: a transistor that is recognized from the mask layout; A transistor portion shape recognizing means for recognizing the shape of the transistor portion including a curve included in the shape; and a gate capacitance of the transistor in a circuit simulation based on the shape of the transistor portion recognized by the transistor shape recognizing device. Transistor size calculating means for obtaining an equivalent transistor size that matches the gate capacitance of the transistor in the device; circuit simulation and actual data using the equivalent transistor size obtained by the transistor size calculating means And a correction current source generating means for virtually generating a correction current source having a current value corresponding to the obtained difference. apparatus. 3. A circuit extracting device for extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, and a parameter used for circuit simulation from information such as process information of the semiconductor circuit. In a simulation information generation system comprising: a parameter extraction unit for extracting, the circuit extraction device includes: a transistor included in the semiconductor circuit, based on a shape of the transistor including a curve, which is recognized from the mask layout. An equivalent transistor size that matches the gate capacitance between the circuit simulation and the actual device is obtained, and the obtained equivalent transistor size is output as circuit information used for the circuit simulation. And inputting an equivalent transistor size obtained by the extraction device, and extracting a parameter such that a drain current of the transistor matches between a circuit simulation using the equivalent transistor size and an actual device. Information generation system for simulation. 4. A method for extracting a circuit for extracting circuit information used for a circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, wherein a transistor included in the semiconductor circuit is recognized from the mask layout. Then, based on the shape of the transistor including the curve, an equivalent transistor size such that the gate capacitance matches in the circuit simulation and the actual device is obtained, and then the circuit simulation using the equivalent transistor size and the actual device are performed. By virtually generating a correction current source having a current value corresponding to a difference between drain currents, the equivalent transistor size and the data of the correction current source are used as circuit information used in circuit simulation. Extraction method. 5. A method of extracting a circuit for extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, comprising: identifying a transistor from the mask layout; A transistor portion shape recognition step of recognizing the shape of the portion including the curve of the shape, and a gate capacitance of the transistor in a circuit simulation based on the shape of the transistor portion recognized in the transistor portion shape recognition step. A transistor size calculation step for obtaining an equivalent transistor size that matches the gate capacitance of the transistor in the above step; a circuit simulation using the equivalent transistor size obtained in the transistor size calculation step; And a correction current source generating step of virtually generating a correction current source having a current value corresponding to the obtained difference. Method. 6. A circuit extracting step of extracting circuit information used for circuit simulation from a mask layout in consideration of a finished shape after manufacturing a semiconductor circuit, and a parameter used for circuit simulation from information such as process information of the semiconductor circuit. A parameter extracting step for extracting, comprising: extracting a parameter for extracting the circuit; wherein the step of extracting the circuit is based on a shape of the transistor having a curve, which is recognized from the mask layout, for the transistor included in the semiconductor circuit. A step of obtaining an equivalent transistor size such that the gate capacitances match in the circuit simulation and the actual device. The step of extracting the parameters includes: a circuit simulation using the equivalent transistor size obtained by the step of extracting the circuit. Shi Simulation information generating method characterized in that the drain current of the transistor in the emission and the actual device is provided with a step of extracting parameters to match.