JPH06196715A - Writing and erasing method for semiconductor nonvolatile memory device - Google Patents

Abstract

PURPOSE:To provide a writing and an erasing method by which a nonvolatile memory cell having excellent reliability and a long life can be obtained. CONSTITUTION:A source 3 and a substrate 1 are grounded, and a positive voltage with respect to the substrate 1 is so applied to a control gate as to generate an electric field of such a strength as required to produce a tunnel effect in an insulating film 6c and at the same time a positive voltage of the same degree as that is applied to a drain 2, and at that time electrons pass through an insulating film 6c on the source 3 side by the tunnel effect through the source 3 from the substrate 1 and are injected into a floating gate 5 to complete the writing. The control gate 7, the source 3 and the substrate 1 are grounded, and a positive voice with respect to the substrate 1 is so applied to the drain 2 as to generate an electric field of such a strength as required to produce a tunnel effect, and at that time electrons stored under the floating gate 5 (thickness directly under is 10 to 300Angstrom ) pass through the insulating films 6c on the drain 2 side from the floating gate 5 by the tunnel effect through the drain 2 and then are discharged into the substrate 1 to complete the erasing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device (hereinafter referred to as "electrically writable and electrically erasable").
The present invention relates to a writing and erasing method of a non-volatile memory).

[0002]

2. Description of the Related Art In recent years, EEPROM (Electrically Erasable Read Onl) has been used as a non-volatile memory capable of electrically writing and erasing, which has received a great deal of attention in recent years.
y Memory). To facilitate understanding of the present invention, an outline of the EEPROM will be described.

Normally, a silicon oxide (SiO2) film has a thickness of 20 to 3
Even if a voltage of about 0 V is applied, only a very small leak current flows. However, the SiO2 film exhibits such good insulating properties only when the thickness of the SiO2 film is about 500 Å or more, and the thickness of the SiO2 film is, for example, 100 to 2
If a voltage of about 20 V is applied to the SiO2 film with a thickness of about 00Å, an electric field of about 10 ⁷ V / cm or more is generated, and electrons may jump from the negative electrode side to the positive electrode side of the energy barrier of the SiO2 film. Instead, a current flows through the SiO2 film by moving through the forbidden band of the SiO2 film.

This is due to the already known Fowler-Nordhei
The m-tunnel phenomenon (hereinafter referred to as the tunnel phenomenon) is a bidirectional property in which electrons can move in either direction according to the direction of the electric field generated in the SiO2 film. An EEPROM uses this tunnel phenomenon for a memory transistor.

A floating gate type EEPROM having a field effect transistor (FET) structure will be described below as an example. FIG. 1 is a side sectional view showing a memory cell portion of a conventional n-channel EEPROM. In the figure, 1 is a P-type silicon (Si) substrate, 2 and 3 are p-type Si substrates 1 respectively.
N formed on one of the main surface portions at a predetermined distance from each other
-Type drain impurity diffusion layer (hereinafter referred to as drain) and n-type source impurity diffusion layer (hereinafter referred to as source),
Reference numeral 4 denotes SiO2 formed on the respective surfaces of the drain 2, the source 3 and the p-type Si substrate 1.

Reference numeral 5 denotes a floating gate conductor layer (hereinafter referred to as "buried") embedded in the SiO2 film 4 so as to reach above the source 3 from above the drain 2 and above the p-type Si substrate 1 between the drain 2 and the source. , 6 is composed of the SiO 2 film 4 between the drain 2 side end of the floating gate 5 and the drain 2, and its thickness is set to about 10 to 300 Å so that a tunnel phenomenon can occur. It is a tunnel SiO2 film. The thickness of the SiO2 film 4 immediately below the end of the floating gate 5 on the side of the drain 2 is 500 Å or more so that the tunnel phenomenon does not occur. Reference numeral 7 denotes a control gate conductor layer (hereinafter referred to as a control gate) embedded in a portion above the floating gate 5 in the SiO2 film 4 at a distance such that a tunnel phenomenon does not occur with the floating gate 5. ).

Next, the operation of this conventional example will be described. Here, charging the floating gate 5 with electrons is called writing, and discharging the electrons from the floating gate 5 is called erasing. First, in the case of writing, the drain 2, the source 3 and the P-type Si substrate 1 are grounded, and a p-type Si substrate is formed so that an electric field of a magnitude necessary for causing a tunnel phenomenon in the tunnel SiO2 film 6 is generated. When a positive voltage with respect to 1 is applied to the control gate 7, electrons are emitted from the p-type Si substrate 1 to the drain 2
Through the tunnel SiO2 film 6 by the tunnel phenomenon and injected into the floating gate 5. The electrons injected into the floating gate 5 charge the floating gate 5 to complete the writing. Since the floating gate 5 is surrounded by the SiO2 film 4, the electrons charged in the floating gate 5 are
Even if the positive voltage applied to the control gate 7 is removed, it is still stored in the floating gate 5.

Next, in the case of erasing, the control gate 7, the source 3 and the P-type Si substrate 1 are grounded so that an electric field having a magnitude necessary to cause a tunnel phenomenon in the tunnel SiO 2 film 6 is generated. Then, when a positive voltage is applied to the drain 2 with respect to the p-type Si substrate 1, an electric field in the direction opposite to that in the above writing is generated in the tunnel SiO2 film 6, and the electrons accumulated in the floating gate 5 are After passing through 5 through the tunnel phenomenon, it is discharged to the p-type Si substrate 1 through the drain 2, and the erasing is completed.

Further, in the case of reading, the threshold voltage of the control gate changes depending on whether or not electrons are accumulated in the floating gate 5, so that the drain 2 and the source 3 between the drain 2 and the source 3 are changed based on the change in the threshold voltage. ON state and OF
Depending on the F state, a logic signal of "1" and "0" can be obtained.

In general, tunnel Si is caused by the tunnel phenomenon.
Some of the electrons that pass through the O2 film are trapped by the traps in the tunnel SiO2 film and remain in the tunnel SiO2 film, and the number of residual electrons in this tunnel SiO2 film increases in proportion to the number of times that electrons pass through the tunnel SiO2 film. To do.

[0011]

In the memory cell of this conventional example, electrons pass through the tunnel SiO2 film 6 at the same position during writing and erasing. Therefore, tunneling is performed in proportion to the number of rewritings in which writing and erasing are repeated. SiO2 film 6
The rate of increase in the number of remaining electrons is large. Therefore, since the number of electrons enough to change the threshold voltage of the control gate 7 remains in the tunnel SiO2 film 6 with a small number of times of rewriting, and rewriting after that becomes impossible, the life of the memory cell is short. There was a problem. In addition, since the moving direction of electrons at the time of writing and the moving direction of electrons at the time of erasing are completely opposite to each other, the tunnel SiO2 film 6 is deteriorated faster than the case where the moving direction of electrons is one direction. However, there is also a problem that the reliability of the memory cell is poor.

The present invention has been made in view of the above points, and the number of electrons retained in the insulating film between the semiconductor substrate and the floating gate can be reduced by writing and erasing,
It is an object of the present invention to provide a writing and erasing method which can provide a nonvolatile memory cell having high reliability, long life, easy erasing, and high information reading speed.

[0013]

In a method of writing and erasing a semiconductor nonvolatile memory device according to the present invention, a floating gate conductor layer is a semiconductor substrate between a drain impurity diffusion layer and a source impurity diffusion layer from above a drain impurity diffusion layer. Of the first insulating film provided directly above the floating gate conductor layer within the range of 10 to 300 Å, and has the same thickness as the control gate conductor layer. And a potential lower than the positive potential applied to the control gate conductor layer to the source impurity diffusion layer and the semiconductor substrate, respectively, and floating via the first insulating film located on the drain impurity diffusion layer side. There is no injection of electrons into the gate conductive layer, and there is a flow due to the tunneling phenomenon of the first insulating film located on the source impurity diffusion layer side. Drain impurities are accumulated by accumulating electrons in the gate gate conductor layer and applying a positive potential to the drain impurity diffusion layer and applying a potential lower than the positive potential applied to the drain impurity diffusion layer to the control gate conductor layer. The electrons accumulated in the floating gate conductor layer are extracted to the drain impurity diffusion layer by the tunnel phenomenon of the first insulating film interposed between the diffusion layer and the floating gate conductor layer.

[0014]

According to the present invention, the electrons are accumulated in the floating gate conductor layer by the tunneling phenomenon of the first insulating film located on the source impurity diffusion layer side and accumulated in the floating gate conductor layer. The extraction of electrons is performed by the tunneling phenomenon of the first insulating film interposed between the drain impurity diffusion layer and the floating gate conductor layer, and the electron transfer positions in the first insulating film during writing and erasing are made different, and The part of the first insulating film in which the electron moving directions are in both directions is eliminated.

[0015]

FIG. 2 shows an n-channel type E according to an embodiment of the present invention.
FIG. 3 is a side sectional view showing a memory cell portion of an EPROM. In the figure, the same reference numerals as those of the conventional example shown in FIG. 1 indicate the same or corresponding portions, and 6c is a SiO2 film (first insulating film) formed directly under the floating gate 5, on the drain 2 and the source 3
All have the same film thickness on and above the semiconductor substrate 1 and the film thickness is set so that the tunnel phenomenon can occur.
It is a tunnel SiO2 film with a thickness of 0 to 300Å. In addition,
The control gate 7 formed on the floating gate 5 via the second insulating film is formed to have substantially the same width as the floating gate 5.

Next, the operation of this embodiment will be described. First, in the case of writing, the source 3 and the p-type Si substrate 1 are grounded, and the p-type Si substrate 1 is formed so that an electric field having a magnitude necessary to cause a tunnel phenomenon in the first insulating film 6c is generated. On the other hand, a positive voltage is applied to the control gate 7, and the drain 2 is also applied with a similar positive voltage. In this state, the control gate 7 and the drain 2 have almost the same potential and there is no potential difference.
Since an electric field is hardly generated in the insulating film 6c, electrons are not injected from the drain 2 to the floating gate 5 through the first insulating film 6c on the drain 2 side by the tunnel phenomenon, and the electrons are p-type Si substrate 1 Through the source 3 through the first insulating film 6c on the source 3 side by a tunnel phenomenon and injected into the floating gate 5. The electrons injected into the floating gate 5 charge the floating gate 5 to complete the writing.

Next, in the case of erasing, the control gate 7, the source 3 and the p-type Si substrate 1 are grounded and the first insulation on the side of the drain 2 is carried out as in the case of erasing of the conventional example shown in FIG. When a positive voltage is applied to the drain 2 with respect to the p-type Si substrate 1 so that an electric field having a magnitude necessary to cause a tunnel phenomenon in the film 6c is generated, the electrons accumulated in the floating gate 5 float. The first insulating film 6c on the drain 2 side passes from the gate 5 through the tunnel phenomenon, and the drain 2
After that, it is discharged to the P-type Si substrate 1 and the erasing is completed.

The reading operation is the same as the reading operation of the conventional example shown in FIG. 1, and therefore its explanation is omitted.

In the memory cell of this embodiment, accumulation of electrons in the floating gate conductor layer (writing in this embodiment) and extraction of electrons from the floating gate conductor layer (erasing in this embodiment) are performed. First
Since the insulating film 6c passes through the tunnel 2 at the drain 2 side and the source 3 side at different positions, the number of electrons remaining in the first insulating film 6c on the drain 2 side and the first insulating film on the source 3 side. Since the rate of increase in the number of electrons remaining in 6c in proportion to the number of rewrites is 1/2 of the rate of increase in the number of residual electrons in the memory cell of the conventional example shown in FIG. The number of times of rewriting until it becomes impossible is twice the number of times of rewriting that is possible in the case of the conventional memory cell shown in FIG. 1, and the life of the memory cell can be extended.

The first insulating film 6 on the drain 2 side is also provided.
Since the moving direction in c and the moving direction in the first insulating film 6c on the source 3 side are both unidirectional, that is, there is no portion of the first insulating film 6c in which electron moving directions are both directions, it is shown in FIG. Compared to the case of the memory cell of the conventional example in both directions, deterioration of the first insulating film 6c on the drain 2 side and the first insulating film 6c on the source 3 side, that is, the first insulating film 6c
The deterioration of the insulating film 6c can be suppressed. as a result,
The reliability of the memory cell can be improved.

In this embodiment, the source 3 is formed on the semiconductor substrate 1 on which the source 3 and the drain 2 are formed.
Also, the thickness of the first insulating film 6c formed over the surface of the semiconductor substrate 1 between the drain 2 and the drain 2 is set to 10 to 300Å which may cause a tunnel phenomenon, and the thickness of the first insulating film 6c is set to the source 3
Since the upper part and each part on the semiconductor substrate 1 are the same,
The thickness of the first insulating film 6c at the portion in contact with the semiconductor substrate 1 is the same as that at the portion in contact with the source 3 and the drain 2, and is thin,
Therefore, the capacitance between the semiconductor substrate 1 and the floating gate 5 is large, and the potential difference (electric field) between the floating gate 5 and the drain 2 becomes large when a positive potential applied to the drain 2 is raised. Easier to erase. Moreover, since the distance between the floating gate 5 and the semiconductor substrate 1 is narrow and the electric field generated in the channel of the semiconductor substrate 1 is large, a large amount of channel current can flow between the source and the drain, and information can be read from the memory cell. It can be done at high speed.

Up to now, n-channel EEPRO has been used.
Although the memory cell of M has been described as an example, the present invention is not limited to this and can be applied to a memory cell of a P-channel EEPROM.

[0023]

As described above, according to the present invention, electrons are accumulated in the floating gate conductor layer by the tunnel phenomenon of the first insulating film located on the source impurity diffusion layer side, and the floating gate conductor layer is formed. Is extracted by the tunneling phenomenon of the first insulating film interposed between the drain impurity diffusion layer and the floating gate conductor layer, that is, the accumulation of electrons in the floating gate conductor layer and the floating gate conductor layer. Since the extraction of electrons from the layer is performed at different positions of the first insulating film, the number of carriers remaining in the first insulating film on the source impurity diffusion layer side and the first insulation on the drain impurity diffusion layer side are set. The rate of increase in the number of carriers remaining in the film with respect to the number of rewrites is small, and the life of the memory cell can be extended. The in one impurity diffusion layer side 1
Since the electron moving direction in the insulating film and the electron moving direction in the first insulating film on the other impurity diffusion layer side are each one direction, deterioration of the first insulating film is suppressed and reliability of the memory cell is improved. It has the effect of improving.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a memory cell portion of a conventional n-channel EEPROM.

FIG. 2 is an n-channel EEPR according to an embodiment of the present invention.
It is a sectional side view which shows the memory cell part of OM.

[Explanation of symbols]

 1 p-type Si substrate (semiconductor substrate) 2 drain impurity diffusion layer 3 source impurity diffusion layer 4 insulating film 5 floating gate conductor layer 6c first insulating film (tunnel SiO2 film) 7 control gate conductor layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11C 16/04 H01L 27/115 7210-4M H01L 27/10 434

Claims (1)

[Claims] 1. A drain impurity diffusion layer and a source impurity diffusion layer, which are formed on a main surface portion of a semiconductor substrate at a predetermined interval from each other, on the respective surfaces of the semiconductor substrate, the drain impurity diffusion layer, and the source impurity diffusion layer. A first insulating film formed over the first insulating film, a floating gate conductor layer provided on the first insulating film, and a control gate provided on the floating gate conductor layer so as to face each other via a second insulating film. In the method for writing and erasing a non-volatile memory cell having a conductor layer, the floating gate conductor layer is located above the drain impurity diffusion layer and above the semiconductor substrate between the drain impurity diffusion layer and the source impurity diffusion layer. Is provided to reach above the source impurity diffusion layer, and the floating gate in the first insulating film is provided. The thickness immediately below the conductor layer is the same within the range of 10 to 300Å, a positive potential is applied to the control gate conductor layer, and the source impurity diffusion layer and the semiconductor substrate are respectively provided with the control gate conductor layer. By applying a potential lower than the applied positive potential, electrons are not injected into the floating gate conductive layer through the first insulating film located on the drain impurity diffusion layer side, and the source impurity diffusion layer side is formed. Electrons are accumulated in the floating gate conductor layer by the tunneling phenomenon of the first insulating film located, a positive potential is applied to the drain impurity diffusion layer, and the drain impurity diffusion layer is formed in the control gate conductor layer. A potential lower than the applied positive potential is applied to interpose between the drain impurity diffusion layer and the floating gate conductor layer. Writing and erasing method of the electrons stored in the floating gate conductor layer by tunneling the first insulating film semiconductor nonvolatile memory device, characterized in that pulling on the drain diffusion layer.