JPH06196659A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a ROM whose memory capacity can be increased without the increase of the area of memory cells. CONSTITUTION:Cell transistors 12a and 12b whose gate terminals are connected to WORD lines 1 and 2 respectively are provided. The source terminals of the cell transistors 12a and 12b are grounded. The respective cell transistors 12a and 12b are assigned for two BIT lines 1 and 2. The connection states of the BIT line 1 and the BIT line 2 are defined in accordance with the values of data to be stored. When a selection signal is applied to, for instance, the WORD line 2, the cell transistor 12b whose gate terminal is connected to the WORD line 2 is turned on and an 'L' level signal is outputted on the BIT line 2 which is connected to the drain terminal of the cell transistor 12b. An 'H' level signal, i.e., a precharged level signal, is outputted on the BIT line 1 which is not connected to the drain terminal of the cell transistor 12b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a read-only memory,
That is, a so-called ROM (Read Only Mem)
ory). In particular, the present invention relates to a ROM configuration capable of reducing the number of transistors constituting a ROM memory cell.

[0002]

2. Description of the Related Art Semiconductor memory devices, so-called semiconductor memories, are used in various types of equipment for home and industrial use. A type of semiconductor memory is a so-called read-only memory (RO).
Called M). Predetermined digital data is stored in advance in this ROM, and the user cannot write new data. However, most of RAMs (readable and writable memories) lose their stored contents when the power is cut off, whereas ROMs
Since the previously stored data is not erased, it is used to hold, for example, a microcomputer program and other certain parameters.

FIG. 2 is a circuit diagram showing a part of a memory cell which is a data storage part of a conventional ROM. As shown in FIG. 2, in the data storage portion of the conventional ROM, a plurality of WORD lines and a plurality of BIT lines are stretched in the vertical and horizontal directions, and each of the WORD line and the BIT line is extended. A cell transistor 10 that constitutes a memory cell is provided at the intersection of. This cell transistor 10
(A, b, c, d) has its gate terminal connected to one of the WORD lines and its source terminal grounded,
The drain terminal is connected or not connected to the corresponding BIT line depending on the content of the data to be stored. In FIG. 2, a portion where the drain terminal and the BIT line are connected is shown by a black circle, and a portion where they are not connected is shown by a cross. Then, each connection or non-connection point holds 1-bit data.

For example, when a selection signal is supplied to the WORD line 1 shown in FIG. 2, the selection signal is applied to the gate terminals of the cell transistors 10a and 10b shown in FIG. It becomes conductive. As a result, since the BIT line 1 of FIG. 2 is connected to the drain terminal of the cell transistor 10a, the data of “L” appears on the BIT line 1. On the other hand, since the BIT line 2 is not connected to the drain terminal of the cell transistor 10b, "H" data appears on the BIT line 2. Then, the data respectively shown are read out to the outside. Since each BIT line is precharged to the “H” level when reading data,
As described above, "H" data is output to the BIT line that is not connected to the drain terminal of the cell transistor (cell transistor 10b in the above-described example) that has become conductive.

As described above, in the conventional ROM, W
A cell transistor 10 is provided at each intersection of the ORD line and the BIT line.
Are provided and data is stored depending on whether or not each drain terminal is connected to the BIT line. That is, 1-bit data is stored at each intersection of the WORD line and the BIT line, and one cell transistor 10 is required to store the 1-bit data.

[0006]

As described above, the conventional R
In the OM, since one cell transistor is provided for 1-bit data, the area for storing 1-bit data, that is, the area of the memory cell strongly depends on the size of the cell transistor. . Therefore, in the conventional ROM, it is necessary to reduce the cell transistor in order to reduce the area of each memory cell. However, since this cell transistor drives the BIT line, a constant driving capability is required, and there is a limit to reducing it.

In order to solve this problem, for example, Japanese Patent Publication No. 57-51195 discloses a semiconductor memory device capable of reducing the number of memory cells by omitting columns of memory cells according to data. It is disclosed. However, since the storage capacity of this storage device is determined according to the value of the data to be stored, there is an inconvenience that a specific storage capacity cannot be determined until the data is determined.

The present invention has been made in view of the above problems, and an object thereof is to store a plurality of bits in one cell transistor so that a large amount of information can be stored without reducing the size of the cell transistor. ROM that can
Is to provide.

[0009]

In order to solve the above problems, the present invention provides a plurality of word lines, a plurality of bit lines, one of the word lines and the bit line. A cell transistor provided corresponding to each group with a predetermined plurality of bit lines, the gate terminal of which is connected to one word line of the corresponding group, the source terminal of which is grounded, and storage A plurality of cell transistors in which a plurality of bit lines of the corresponding set are respectively connected or not connected to a drain terminal according to the value of data to be stored, each cell transistor being connected to its gate terminal. When a selection signal is applied to the word line
A read-only semiconductor memory which outputs a signal of ground potential to the corresponding bit line connected to the drain terminal.

[0010]

The cell transistor according to the present invention is connected or not connected to a plurality of corresponding BIT lines according to the value of the data to be stored. And the connected BIT
A signal of the ground potential is output to the line. Then, another signal having a predetermined potential appears on the BIT line that is not connected to the drain terminal. Therefore, 1-bit digital data is stored depending on whether or not the BIT line is connected to the drain terminal of the cell transistor, and a plurality of bits of digital data are stored per cell transistor.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows R, which is a preferred embodiment of the present invention.
A partial circuit diagram of the data storage portion of the OM is shown. Shown in FIG. 1 is the conventional RO shown in FIG.
It is a partial circuit diagram which has a function equivalent to the circuit diagram of M. That is, it is a storage portion corresponding to two WORD lines 1 and WORD lines 2 and two BIT lines 1 and BIT lines 2.

A feature of this embodiment is that a plurality of bit lines correspond to the cell transistor 12. In this embodiment, the cell transistor 12
Two bit lines 1 and 2 correspond to a and 12b, respectively. The drain terminal of the cell transistor 12 (a, b) and the respective bit lines 1 and 2 are connected or not connected depending on the data to be stored. Figure 1
Inside, the place where the drain terminal and the BIT line are connected is shown by a black circle, and the place where it is not connected is shown by a cross. In this embodiment, since the plurality of BIT lines 1 and 2 are driven for one cell transistor 12 in this way, the number of cell transistors 12 with respect to the storage capacity is 1 compared with the conventional method shown in FIG. / 2.

Next, the operation of this embodiment will be described. For example, when the selection signal is applied to the WORD line 1, the selection signal is applied to the gate terminal of the cell transistor 12a, and the cell transistor 12a is turned on, that is, brought into conduction. As a result, the ground potential appears on the BIT line 1 connected to the cell transistor 12a. on the other hand,
The BIT line 2 which is not connected to the drain terminal of the cell transistor 12a is not driven by the cell transistor 12a and holds the precharged potential as it is. The precharge is different from the ground potential, for example, "H"
Done at the level.

In this way, the ground potential, that is, the signal of "L" level is output to the BIT line 1, and the BIT line 2
An "H" level signal is output to. This is shown in Figure 2.
The result is similar to that of the conventional ROM shown in FIG.

Similarly, when the WORD line 2 is accessed in the same manner, a signal having a value corresponding to the connection state with the drain terminal of the cell transistor 12b is output to the BIT lines 1 and 2. .

In this embodiment, the load of one cell transistor 12 (a, b) is two BIT lines 1 and 2. Therefore, although the capacity of the BIT line is doubled, each WOR
Cell transistor 12 (a, connected to D line (1, 2)
The number of b) is half that of the conventional method.
The magnitude of the load connected to the RD line (1, 2) is 1/2. Therefore, the speed of driving the WORD lines (1, 2) is higher than that of the conventional method. As a result, it is expected that the access speed of the ROM according to this embodiment will not be slower than that of the conventional method. On the other hand, since the number of cell transistors 12 is 1/2 that in the conventional method, the area occupied by the memory cells is also approximately 1/2.

As described above, according to this embodiment, the area occupied by the memory cell can be reduced to about 1/2 without reducing the size of the cell transistor.
When configuring a ROM of the same capacity, the chip area can be reduced to about half that of the conventional method. In other words, if the chip area has the same size as the conventional one, the storage capacity twice as large as that of the conventional one can be realized.

[0019]

As described above, according to the present invention, since a plurality of BIT lines are assigned to one cell transistor, a plurality of bits of digital data can be driven by one cell transistor. Can be output. Therefore, it is possible to reduce the number of cell transistors which is conventionally required for each bit of digital data. As a result, a ROM having the same capacity as that of the conventional method can be configured with a chip having a half area. In other words, if the chip area is the same as that of the conventional method, there is an effect that a ROM having a storage capacity twice that of the conventional method can be constructed.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram of a ROM according to an embodiment of the present invention.

FIG. 2 is a partial circuit diagram of a conventional ROM.

[Explanation of Codes] 12a, 12b Cell Transistor

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of bit lines, and a set of one word line among the word lines and a predetermined plurality of bit lines among the bit lines. A plurality of bit lines of the corresponding set according to the value of the stored data, the gate terminal of which is connected to one word line of the corresponding set and the source terminal of which is grounded. A plurality of cell transistors each connected or not connected to a drain terminal, and each cell transistor has a drain terminal when a selection signal is applied to the word line connected to its gate terminal. A read-only semiconductor memory, which outputs a signal of ground potential to the corresponding bit line connected to.