JPS5975486A - Mos static ram - Google Patents

Abstract

PURPOSE:To reduce the power consumption of an MOS static RAM, by controlling a word selecting period by a timing signal having a time required for the write outputted from a timing generating circuit. CONSTITUTION:When a write data Din changes, a timing generating circuit T-SG detects it, and the circuit T-SG forms a timing signal phiw being a low level for a period required for the write. Then, word lines W1, W2- in response to the address signal during the period only are selected, and the information is written in a memory cell MC corresponding to data ines D1, D2- selected already. When this write period is finished and the signal phiw is inverted to high level, the word lines W1- are brought into a non-selecting state, and the current from the load of the data lines D1- to the selected cell MC is inhibited, allowing to reduce the power consumption of the MOS static RMA.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state-of-the-art type RAM configured with MOSFETs (insulated gate field effect transistors).
Regarding (random/access/messages). .

In a MOS static RAM, if the word line is left in the selected state, the ffi current continues to flow through the selected memory cell by 3 m from the data line load, resulting in a relatively large current consumption. .

The inventor of the present application focused on the fact that the write operation can be performed in A-low and considered reducing the power consumption of the write operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS static type F-type input 28 which achieves low power consumption during a write operation.

Other objects of the invention will become apparent from the following description and Section 4-4.

Below, the invention will be described in 4-? along with examples. : Explain to phase.

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM of the same M can be a known CM.
O3 (complementary-metal-impossible-semiconductor) integrated circuit (IC
) By technology I? It is formed on a semiconductor substrate such as 11+ silicon single crystal.

Terminal Ax, △Y, I)in, Dout, V
IE and hi are used as its external terminals. Note that the power supply terminal is omitted in [4].

The memory cell MC, of which one specific circuit 1114 is shown as a representative, is a memory MOS F E'FQ ], f which is cross-wired to the gate and I'LL twins.
, u 2, and the above MO3FIE'"Ql,Q2's Dre.
There is a polygon for information retention between the f and the power supply voltage VDD.
(Multiple, -crystalline) High resistance RL formed of silicon layer, l
−? 2 is provided. And the above M OS FI
Common connection point of EGO C11, 0°2 and complementary data line 1) 0
．． 1) (Transmission game 1- between + and MOS F E
'FQ 3, cl, 1 are set up iJ et al.

The other memory cells MC also have the same (η) circuit configuration.These memory cells (j) are arranged in a matrix.The transmission gate of the memory cells arranged in the same row is The gates such as OS F)", T(J3, Ql, etc.
The input/output terminals of the memory cells arranged in the same column are connected to JJII and JJII respectively, and the input/output terminals of the memory cells arranged in the same column are a pair of complementary data (or Pino l-) DO, l:) 0 and Dl,
Each is connected to the other.

In the memory cell MC, in order to reduce power consumption, the resistor R1 is MOS f"r: i"
When Ql is turned off, the case 1 voltage of MOSFET I゛Q2 is expressed as the threshold voltage fJ, l-
The A resistance value is set to such an extent that -IJ can be maintained at -IJ. Similarly (at t, resistor R2 is also set to a high resistance value.
, due to the drain leakage current of I
It is designed to have a current supply capacity 4 sufficient to prevent the information charge stored in the goo 1 capacity meter (not shown) of E 'I'' Q 2 from being discharged.

According to this example, RAM is (-: M OS -
IC: Despite being manufactured by technology, 1-
As shown, the memory cell MC is n, and the memory cell is MOS.
It is composed of F E'1' and a polysilicon resistance element.

- ζpp channel M in place of the resistance Shimako
When using OSF rζ'■', please reduce the size of the memory and memory array. S'11 straw, using polysilicon resistor), - field (-1, driving M
It can be formed integrally with the gate electrode of OSFET QI or Q2, and its size can be reduced. And p channel M OS F? "As when using T-, the drive MOS F FE i' Q 1
, Q There is no need to separate iJ by a relatively large distance from 2, so no wasted blank space is created.

In the same figure, the word line W1 is selected by the selection (p5':!
, is selected by the drive circuit D1 which receives the highest voltage. The same ladder applies to the other glue - IIS W2.

The above X-address decoder X-I) is composed of similar NOR gate circuits Gl, (J2, etc.) in CI, I, and I, respectively.The inputs of these NOR gates 1, 1, 02, etc. are as follows: Receive the external address signal ΔX supplied from an appropriate circuit device (not shown) x Alsba Sofa X-A
Internal complementary address signals processed by DB are applied in a predetermined combination.

- Pair of data lines in the above memory array ■〕0゜D
O, DI, and DI are transmission game 1-M03FE'rQ9. for data selection, respectively. 1.1 (l and Q
It is connected to the common data lines CD and CD through a sub-circuit of Carano and SW7 consisting of ll and Ql2. This common-1-evening line c: r-t, (3, L, read I start circuit o OB input terminal G, and write circuit 1') I +
-('s output terminal r- is connected.": Recording/reading V output time +?
M DO day output 1 riko is data output terminal Doul
Sends a readout signal to the input circuit DIB input terminal -
B,! A write data signal supplied from data input 1t47Din is applied.

-1- Power distribution 9), configuring the switch circuit 1' 2. M
(') SF Mi TQ9. QIO and Ql i Ql2
In Case 1, y-y dresste, :I-ta YD
CR Ka;; 1sIi l! (The signal is sent to I.

This Y-A1-Stecoator Y-1) CR is composed of similar NOR-A1 circuits Cζ3, 64, etc. The inputs of these nocate circuits C: +, C;
-ΔD11 The complementary address fjB is sent within 1 degree after processing, but the predetermined combination pin C2 is applied to J9.

The control circuit CON receives control signals from the external terminals W and O8 and forms an internal control timing signal.

In this embodiment, the following circuit is provided in order to reduce current consumption in write operations.

Timing generation circuit 1'-SG is the external terminal W
``Oka, the control signal from itself and the -42 data input terminal D
This RAM-
Data (change in nυ (
It includes an edge trigger circuit that detects the transition) timing, and a mink generation circuit that receives this detection output and forms a timing signal φW with the time width necessary for the write operation. The timing signal φW formed by the circuit T-3G is applied to each NOR gate circuit (Jl, 0
Commonly supplied to second class manpower.

Next, the operation of this embodiment circuit will be explained with reference to the diagrams in FIG.

χdress signal Ai is input, and lie 1 enable signal W
When both E and chip selection signal C8 become low level, this RAM-'IC is put into the operation mode. The timing generation circuit 'l'-SG is activated by the low level of the signals WE and C3, and its output timing output φW is set to a high level. Therefore, X
The output of the address decoder X-DCR becomes low level regardless of the address signal from the address buffer X-ΔDn, and all word lines 1 and 1 are rendered unselected. Therefore, in the RAM of FIG.
~Load such as W1 M OS F' ET Q 5 ~ Q8
I
ll No direct current flows.

Next, when the write data output Din changes, the timing generation circuit]'-3G detects this amount, and the timing signal φW becomes low for the time t required for the write operation.
form. During this time, the word line according to the first address signal is selected, and the memory cells MC in one row are selected. Further, since one column of data lines has already been selected, information according to the write data signal is written into one memory cell MC. ”Second Hour VI
Since the timing signal φW becomes high level with the passage of L, the selected word line is again rendered unselected.

In the above state, when the write data signal Din changes again, one memory cell MC is selected as above,
The data signal Din is written.

Therefore, the final write data of the selected memory cell MC is determined by a subsequent write operation.

In the conventional RAM, the memory cell selection operation is performed only during the time period 1 when the signals WE and C3 in the timing diagram of FIG. 2 are at low level, whereas in the RAM of this embodiment, Since the selected state is maintained only for the time t, the current flowing from the word line load MO3FET to the memory cell can be significantly reduced. 1. That is, by limiting the selection period of the L word line,
Regarding a large number of memory cells connected to one word line, in other words, arranged in the row direction, the current flowing from the two i' line load MO3FET can be limited by 4, thereby reducing power consumption.

In the read operation, since the write-ear and -pull signals WE are at high level, the timing signal φW is set to low level without the J-record timing generation circuit T-3G operating. Therefore, regarding the read operation ζ, -C is the same as the conventional read operation, and its explanation will be omitted.

This invention is based on the above-mentioned actual 1f! ! Limited to two examples.

The memory cell is a p-channel MOS
A known static flip-flop circuit configured by a combination of an n-channel MOS FET and an n-channel MOS FET may be used.

Furthermore, the configuration of the memory array and its peripheral circuits can take various embodiments.

7. Then, when writing, set War 1 “Control cotton selection period”.
The control method for FJ is: ・Various modifications are taken such as the one that does this for the node cotton drive 1i71 f/kichi r) \l. ・Can you do 2? ,.

Further, the specific circuit configuration of the circuit that detects a change in the write data signal during a write operation and forms a timing signal with a pulse width necessary for the write operation may be any.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a timing signal X-A D'B...X address buffer, "Y"-
A DB...Y address buffer, X-DCR...X address decoder, Y-D CR...Y address decoder Z
-DA, MC...memory cell, DIB...write circuit, D
OB...readout circuit, CON...control circuit, T-3G
・・Timing generation circuit No. 1 Fig. A 91F
VDQl 1A// θ5 θ6 θ7 θC Pre-DI, '/ “0 ”1 DVe/ Rρ meeting, Ta 4M (ρ2 vv2,,;c if;;:r; QZ Dv2/〆c Hc box: ,), l )i −3 ρDrys D ” ””// 4.. □ 8 no D, Fig. 2 j

Claims (1)

[Claims] 1. An edge trigger circuit that detects the change timing of an input data signal during a write operation, and a timing ordering circuit that receives the detection output from this edge trigger circuit and forms a timing signal for the time required for the write operation. and a word line selection circuit whose word line selection period is controlled by the output timing signal of the evening timing generation circuit. 2. The above MOS Scutinok type F? A M number J, C
The MOS static type RAM according to claim 1, characterized in that it is constituted by an MO8 circuit.