JPH06196561A - Design of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To predict path delay time after layout accurately by predicting the net length from the probability of a two terminal net straddling a cut line thereby predicting the net length precisely. CONSTITUTION:When a net length is predicted under a state where logic cells are not yet placed, an imaginary cut line for predicting the net length is drawn on a net length predictive region and the net length is predicted from the probability of the net straddling the cut line. For example, a state where a net (solid line) is cut by a cut line is represented by (b) whereas a state where the net is not cut but cells (round mark) to be connected exist within a same region is represented by (a), as shown on the drawing. Probabilities of the states (b) and (a) are designated, respectively, by (p) and 2q. Probabilities of remote and close regions are designated, respectively, by alpha and (1-alpha). Expected value of the net length for state (a) is designated by La and one half of the expected value of the net length for state (b) is designated by Lb. Processing is executed according to the flow chart shown on the drawing thus predicting the net length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor integrated circuit for predicting a net length in a state where logic cells are not arranged.

[0002]

2. Description of the Related Art With the progress of miniaturization technology of LSI and the active production of various kinds, the necessity of predicting a path delay time after layout before layout is increasing. The delay time of the path consists of the delay time of the cell itself and the delay time due to the net length. Therefore, the path delay time after layout can be predicted by accurately estimating the net length before layout.

At present, as a net length prediction method, a method based on empirical data such as the number of gates, cells and fan-outs of a host and a method utilizing Lenz's law are generally used.

The Lenz's law expresses the standard of the number of terminals required for the divided logical blocks at the time of logical division. That is, the relational expression of T = AN _g ^p is established between the number N _g of gates of the divided logic block and the number T of external terminals required for this logic block. Where A is 1
The average number of pins per gate, p is the Lenz multiplier.

WEDonath ("Placement and Average Inte
rconnection Lengths of Computer Logic ", IEEE Transac
tions Circuits and Systems, vol.CAS-26, pp272-277, Ap
ril 1979.) used the above Lenz's law to predict the average net length. Specifically, when p = 0.5

[Equation 1] In other cases

[Equation 2] Is. However, this method does not accurately predict the net length because the difference due to the difference in fanout does not appear.

The above two methods have a large error with respect to the actual net length, and therefore are not suitable for the problem that requires accuracy such as calculation of the path delay time before layout. As a result, it becomes necessary to carry out processing such as circuit modification and cell replacement after rough layout, resulting in deterioration of design efficiency.

[0007]

As described above, since the conventional net length prediction method cannot accurately predict the net length after layout before layout, the path delay time after layout cannot be accurately predicted. It was as a result,
After the rough layout, it is necessary to perform processing such as circuit change and cell replacement, which deteriorates design efficiency.

The present invention solves such a problem. By accurately predicting the net length in a state where no logic cells are arranged, the path delay time after layout is accurately predicted, and efficient design is achieved. It is an object of the present invention to provide a method for designing a semiconductor integrated circuit capable of performing the above.

[0009]

According to the present invention, in designing a semiconductor integrated circuit, when predicting the net length in a state where no logic cell is arranged, the half length of the net length prediction region is defined as one side length, The number of virtual cells existing in the area is (2
* (Number of cells in the area) ^1/2 -1) For the net length prediction, the one-dimensional virtual area is replaced with the net length prediction area, and the area is equally divided into two on the virtual area. Of the virtual cut line of 1 is drawn in the same direction until the number of cells existing in the virtual region divided into two becomes one, and the 2-terminal net length is predicted from the probability that the 2-terminal net crosses the cut line, (Predicted length of 2-terminal net) * (n-1)
Is the net length of the n-terminal net.

[0010]

According to the present invention, assuming a model in which cut lines are drawn from top to bottom like a mini-cut process of placement, paying attention to the probability that the net cuts each cut line, the 2-terminal net The net length is predicted, and the net length of the n-terminal net is predicted based on the net length of the 2-terminal net.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

The proposed net length prediction method assumes a model in which cut lines in the same direction are drawn in a top-down manner in a one-dimensional virtual area, as in the case of placement mini-cut processing (FIG. 1). Paying attention to the probability of cutting each cut line, the net length of the 2-terminal net is predicted. Figure 1
The number of represents the order of each cut line.

The cut line is drawn so that the virtual area is equally divided into two parts, and the number of cells existing in the divided area becomes one.

The net length of the n-terminal net for each fan-out is (the net length of the two-terminal net) for each fan-out *
Expect as (n-1). The outline of the net length prediction method will be described below.

As shown in FIG. 2 (a), a state where the net (solid line) is divided by the cut line is b, and a net (circle mark) which is not divided by the cut line and is connected in the same region exists. The state in which it is open is a. In the state where no cut line is drawn, that is, at the chip level, only the net in the state a exists.

The probability that a net existing in the region of interest by drawing a cut line will be in state b is p and state a is
The probability of becoming is 2q. By definition, p + 2q = 1. (N-1) It is assumed that the area is equally divided into two parts by the next cut line and the next nth cut line is drawn.

The net in the state a is divided into the states a and b by the nth-order cut line. As shown in FIG. 2B, the net in the state b enters an area on the (n-1) th cutline side or crosses the nth cutline (n
-1) Either enter a region far from the next cut line or either.

The probability of entering a distant area is α, and the probability of entering a near area is (1-α). Using this model, the expected value of the net length when the nets existing in each area are in the states a and b is obtained. The expected value of the net length in the state a at the chip level becomes the predicted net length of the 2-terminal net to be obtained.
p, q, and α are parameters determined by the performance of placement.

Next, the method of predicting the net length will be described with reference to the flowchart of FIG. First, the above model is formulated. The expected value of the net length in the state of a is La,
Letting Lb be 1/2 of the expected value of the net length in the state of b, La (n-1) = La (n) * (2 * q) + (2 * Lb (n)) * p (1) The recurrence formula of Lb (n-1) = Lb (n) * (1- [alpha] _n ) + ((D / ²ⁿ ) + Lb (n)) * [alpha] _n (2) holds (step 1).

Here, p: probability of being in a state of b q: 1/2 of probability of being in a state of a on either the left or right α _n : Probability of a net already crossing the cut line further crossing the cut line n: Cut Line order D: The maximum net length of a two-terminal net, that is, assuming that the net length of a two-terminal net is a half circumference length connecting two terminals, the length when a cell is placed at a diagonal corner of a chip Let p + 2q = 1. Net length of unallocated state (L
a (0)) can be calculated from equations (1) and (2).

First, Lb (n) is calculated. Formula (2)
Than,

[Equation 3] If α _N , that is, the probability of crossing the lowest cut line is α, α _N−1 is the probability of crossing two cut lines. If the probability is α ² , the above equation becomes

[Equation 4] (Step 2).

The probability α of crossing the N-th (final-order) cut line is whether the cell is in the area on the N−1th order side or crosses the Nth order cutline and is in the area far from the N−1st order. Since it is either, it becomes 0.5.

Therefore, if α = 0.5 is used as an approximate value when calculating Lb (0), then Lb (1) −Lb (n) = D / 2 ^{N + 1} * (n−1). Net length Lb of the net in the minimum cut area
Assuming that (N) is Lb (N) = D / 2 ^{N + 1} , Lb (1) = Lb (N) + D / 2 ^{N + 1} * (N−1) Lb (n) = Lb (1) − D / 2 ^{N + 1} * (n-1) = Lb (N) + D / 2 ^{N + 1} * (N-1) -D / 2 ^{N + 1} * (n-1) = D / 2 ^{N + 1} + D / 2 ^{N + 1} * (N-n) (3) (step 3).

Next, La (0) is calculated (step 4). From equations (1) and (3), La (n-1) = 2 * q * La (n) + 2 * p * [D / ^{2N + 1} + D / ^{2N + 1} * (N-n)] = 2 * Q * La (n) -p * D / 2 ^N * n + p * D / 2 ^N (N + 1) = A * La (n) + B * n + C A = 2 * q B = -p * D / 2 ^N C = P * D / 2 ^N * (N + 1)

[Equation 5]

[Equation 6] The result of number 5 is

[Equation 7] Becomes

Here, p and q are parameters that depend on the performance of the placement. Next, the values of the two parameters are determined. As shown in FIG. 2A, there are three relationships between the cut lines and the arrangement of cells connected to the two-terminal net. Two
Assuming that the terminal nets are randomly arranged, the probability of each state is 1/3.

Therefore, assuming that p = q = 1/3, the prediction net length of the two-terminal net is: prediction net length = (D / 2 ^N ) * [N-2 * (1- (2 /
3) ^N ] ... (5) (step 5). Here, N = log ₂ (2 * (number of cells) ^1/2 −1).

The net length of the n-terminal net for each fan-out is predicted for each fan-out based on the net length of the 2-terminal net. That is, the net length for each fan-out is as follows: predicted net length = (D / 2 ^N ) * [N−2 * (1- (2 /
3) ^N )] * (n-1) ... (6) (step 6).

The result of applying the above net length prediction method is shown in FIG. The figure shows the number of cells, the number of nets, and the relative error of the applied data. As you can see from this figure,
It is now possible to accurately predict the net length.

[0029]

As described above, according to the present invention, the net length after layout can be accurately predicted before layout. Therefore, when it is difficult to meet the required specifications before layout, the circuit can be changed. It is possible to suggest the necessity of cell replacement. Therefore, it is possible to shorten the entire design period.

[Brief description of drawings]

FIG. 1 is a diagram showing cut lines and their orders.

FIG. 2 is a diagram showing an arrangement state of a two-terminal net.

FIG. 3 is a flowchart showing a processing procedure of a net length prediction method.

FIG. 4 is a chart showing relative error by comparing a predicted value and a value after actual wiring for each data.

Claims (3)

[Claims] 1. In designing a semiconductor integrated circuit, when predicting a net length in a state where no logic cell is arranged, a virtual cut line for net length prediction is drawn in the net length prediction region, A method for designing a semiconductor integrated circuit, comprising predicting a net length from a probability of crossing a cut line. 2. In designing a semiconductor integrated circuit, when predicting a net length in a state where logic cells are not arranged, a half circumference of a net length prediction region is defined as one side length, and a virtual region existing in the region is assumed. The net length prediction region is replaced with a one-dimensional virtual region having the number of cells (2 * (the number of cells in the region) ^1/2 −1), and the region is evenly divided into 2 regions on the virtual region. A virtual cut line for predicting the net length to be divided is drawn in the same direction until the number of cells existing in the virtual region divided into two becomes one, and from the probability that a two-terminal net will cross the cut line, two terminals will be drawn. A method for designing a semiconductor integrated circuit, comprising predicting a net length. 3. In designing a semiconductor integrated circuit, when predicting a net length in a state where logic cells are not arranged, a half circumference of a net length prediction area is defined as one side length, and a virtual area existing in the area is assumed. The net length prediction region is replaced with a one-dimensional virtual region having the number of cells (2 * (the number of cells in the region) ^1/2 −1), and the region is evenly divided into 2 regions on the virtual region. A virtual cut line for predicting the net length to be divided is drawn in the same direction until the number of cells existing in the virtual region divided into two becomes one, and from the probability that a two-terminal net will cross the cut line, two terminals will be drawn. A method for designing a semiconductor integrated circuit, comprising: predicting a net length, and (predicted length of a two-terminal net) * (n-1) is a net length of an n-terminal net.