JPH06195979A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the drivability to a storage element and to extend the margin to a low voltage and a temperature characteristic by installing a MOS transistor TR for voltage dropping in which the drain is connected to a power source and the source and the gate are connected to sources of PMOS TRs of first and second inverters, between the storage element and the power source. CONSTITUTION:When the state of a storage element M is defined as '1' and '0' is written, a PMOS TR 4 is turned off, and the NMOS TR of an inverter 11 is turned on, and the PMOS TR is turned off. Therefore, it is necessary to make the input value of the inverter 11 consisting of respective MOS TRs 1 and 2 smaller than a threshold value in the bus passing an NMOS TR 3, an MNOS TR 6, an NMOS TR 7, and the NMOS TR of the inverter. However, the source of a PMOS TR 3 is connected to a PMOS TR 50, and its potential is transferred by the value obtained by subtracting a threshold voltage VTHP of the PMOS TR 3 from a voltage Vcc of a power source P.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static type semiconductor memory which operates at a low voltage.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional static type semiconductor memory. In the figure, reference numerals 1 and 2 denote a PMOS (P-type metal oxide semiconductor) transistor and an NMOS (P-type metal oxide semiconductor) forming a first inverter I1. N-type metal oxide semiconductor) transistors, 3 and 4 are PMOS transistors and NMOS transistors that form the second inverter I2. One input of the first inverter I1 and the second inverter I2 is connected to the output of the other. Storage element M
Are configured.

Reference numerals 5 and 6 are transmission transistors as NMOS transistors which perform a selection operation by the Y address line 14 of the selection address signal input to the gate, and 9, 10 and 7, 8 are NMOS transistors, which are read out to the gate input. The bit signals 17 and 18 are selectively input to the sense circuit 13 and the inverter 1 by the address signals of the X address line 16 and the write X address line 15.
It is connected to the output side of 1 and the output side of the inverter 12.

Reference numeral 20 is a data input line for inputting data at the time of writing, 13 is connected to bit lines 17 and 18 selected by the NMOS transistors 9 and 10, and outputs a sense circuit output signal to the signal line 19. , And P is a power supply.

Next, the operation will be described. First, each MO
The stored values "0 ',"1'are determined by the output values of the first inverter I1 and the second inverter I2 formed of the S transistors 1, 2, 3 and 4. Now, in the state of "1 '", the output value of the inverter composed of the MOS transistors 3 and 4 is "H'", and the output value of the first inverter I1 composed of the MOS transistors 1 and 2 is "L". It is assumed that the time is '' and the state of '0' is the opposite.

When reading, the illustrated bit line 1
If 7 and 18 are selected and the stored value is ‘1’, Y
Address line 14, read X address line 16 and each M
The output voltage value of the second inverter I2 composed of the OS transistors 3 and 4 is Vcc, and each MOS transistor 1 and
The voltage value of the output of the first inverter I1 composed of 2 is 0 volt, and therefore the voltage value of the bit line 17 is V
cc-V _THN (V _THN is the threshold voltage of the NMOS transistor).

On the other hand, the voltage value of the bit line 18 is 0 volt, and each value or its transition value is input to the sense circuit 13, and "H '" is output to the signal line 19. On the other hand, when the stored value is "0 '", the signal line 19 is also "0".
It becomes L '.

On the other hand, regarding writing, if the memory element M is "1" and "0" is written, the PMOS transistor 3 is turned "on" and the NMOS transistor 4 is turned "off" as shown in FIG. , NMO of the inverter 11
S is "on" and PMOS is "off", and they are connected via the transfer transistors 6 and 7, respectively.

Further, as shown in FIG. 6, the PMOS transistor 1 is turned on, and the PMOS of the inverter 12 is turned on.
ON ', NMOS is'OFF', and each is NMOS
It is connected through the transistors 5 and 8.

Therefore, in order to set the state of the memory element M to 0 ', the PMOS transistor 3-NMOS transistor 6-NMOS transistor 7-N of the inverter 11
In the path formed by MOS, it is necessary to make the input value of the first inverter I1 composed of the MOS transistors 1 and 2 lower than the threshold value, and the NMOS transistor 2-transmission transistor 5-NMOS transistor 8-inverter 12 In the PMOS path, the input value of the second inverter I2 including the MOS transistors 3 and 4 needs to be higher than the threshold value.

Similarly, when the stored value is "0" and is set to "1", the PM of the PMOS transistor 4-NMOS transistor 6-NMOS transistor 7-inverter 11 is set.
OS transistor, PMOS transistor 1-transmission transistor 5-NMOS transistor 8-inverter 12
In the path of the NMOS transistor of, the input value of the first inverter I1 composed of the MOS transistors 1 and 2 is made higher than the threshold value, and the input value of the second inverter I2 composed of the MOS transistors 3 and 4 is It must be lower than the threshold.

[0012]

Since the conventional semiconductor memory is configured as described above, at the time of writing, in the path from the storage element M to the inverter 11 and from the storage element M to the inverter 12, the drive capability of the storage element M is higher than that of the storage element M. Is required to set the value of the memory element M to a predetermined value by the inverters 11 and 12, which are higher than
Since the MOS transistors 6 and 7 and the NMOS transistors 5 and 8 tend to effectively reduce the drive capability of the inverters 11 and 12, there is a problem that writing cannot be performed especially at a low voltage.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a semiconductor memory capable of low-voltage operation while minimizing a decrease in access time at the time of reading. To aim.

[0014]

In a semiconductor memory according to the present invention, a drain is connected to a power supply and a source and a gate are a first inverter and a second inverter between a storage element and a power supply.
In this case, a voltage lowering PMOS transistor connected to the source of the PMOS transistor of the inverter is installed.

[0015]

In the semiconductor memory according to the present invention, a diode-connected PMOS transistor is connected between the power supply and the storage element in order to effectively lower the power supply voltage supplied to the storage element, and the threshold voltage is supplied to the storage element. Reduce the power supply voltage value.

[0016]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numerals 1 and 2 denote a PMOS (P-type metal oxide semiconductor) transistor and an NMOS (N-type metal oxide semiconductor) transistor which form a first inverter I1, and 3 and 4 form a second inverter I2. PMOS
One input of the first inverter I1 and the second inverter I2 of the transistor and the NMOS transistor is connected to the output of the other, forming a memory element M.

Reference numerals 5 and 6 are transmission transistors as NMOS transistors which perform a selection operation by the Y address line 14 of the selection address signal input to the gate, and 9, 10 and 7, 8 are NMOS transistors, which are read out to be input to the gate. The bit signals 17 and 18 are selectively input to the sense circuit 13 and the inverter 1 by the address signals of the X address line 16 and the write X address line 15.
It is connected to the output side of 1 and the output side of the inverter 12.

Further, 20 is a data input line for inputting data at the time of writing, 13 is connected to bit lines 17 and 18 selected by the NMOS transistors 9 and 10, and outputs a sense circuit output signal to the signal line 19. , And P is a power supply.

Further, 50 is a PMOS transistor 1,
3 and a power source P, the PMOS transistor 50 has a drain serving as a power source and a source and a gate serving as PMOS transistors 1 and 3.
Connected to each source.

Next, the operation will be described. Now, assuming that the state of the memory element M is "1" and "0" is written,
As in the conventional example, as shown in FIG. 2, the PMOS transistor 3 is turned on ', the NMOS transistor 4 is turned off', the NMOS transistor of the inverter 11 is turned on ', and the PMOS transistor is turned on.
The transistor is off.

Therefore, the NMOS transistor 3-NM
In the path of the OS transistor 6-NMOS transistor 7-NMOS transistor of the inverter 11, each M
The input value of the first inverter I1 composed of the OS transistors 1 and 2 needs to be lower than the threshold value.
The source of the S transistor 3 is the PMOS transistor 50.
And the potential thereof is the voltage obtained by subtracting the threshold voltage V _THP of the PMOS transistor from the voltage Vcc of the power source P. Therefore, the drivability of the PMOS transistor 3 is lower than that of the conventional example, which facilitates the transition.

Further, as shown in FIG. 3, the PMOS transistor 1
Is off, NMOS transistor 2 is on, PMOS transistor of inverter 12 is on, NMO
Since the S-transistor is turned off, in the path of the NMOS transistor 2-NMOS transistor 5-NMOS transistor 8-PMOS transistor of the inverter 12, the second transistor including the MOS transistors 3 and 4 is formed.
It is necessary to make the input value of the inverter I2 of 1 above a threshold value.

However, since the gate of the NMOS transistor 2 is Vcc-V _THP , its drivability is lower than that of the conventional example, and the transition is facilitated. Also, when the state of the memory cell is "0" and "1" is written, similarly, the transition is made easier as compared with the conventional example, and the low voltage operation margin is increased.

[0024]

As described above, according to the present invention, the drain is connected to the power supply and the source and the gate are connected to the sources of the PMOS transistors of the first inverter and the second inverter between the storage element and the power supply. Since the PMOS transistor for voltage reduction is installed, the drivability to the storage element is reduced, the state transition at the time of writing can be facilitated, and the margin can be widened for low voltage and temperature characteristics. There is an effect that can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a data path to a memory cell at the time of writing according to the present invention.

FIG. 3 is a circuit diagram showing another data path to a memory cell at the time of writing according to the present invention.

FIG. 4 is a circuit diagram showing a conventional semiconductor memory.

FIG. 5 is a circuit diagram showing a data path at the time of writing in a conventional example.

FIG. 6 is a circuit diagram showing another data path at the time of writing in the conventional example.

[Explanation of symbols]

 1,3 PMOS transistor 2,4 NMOS transistor 5,6 Transfer transistor 50 Voltage lowering PMOS transistor I1 First inverter I2 Second inverter M Storage element P Power supply

Claims (1)

[Claims] 1. A first inverter and a second inverter, each of which is composed of a PMOS transistor and an NMOS transistor, which are connected in series, and a first inverter and a second inverter, and the input of the first inverter. Is connected to the output of the second inverter, and the output of the first inverter is connected to the output of the second inverter; and the input / output of the first inverter and the second inverter An NMOS whose source is connected to two connection points and whose gate input is the selected address signal
In a semiconductor memory provided with each one transfer transistor composed of a transistor, a voltage having a drain connected to a power supply and a source and a gate connected to a source of a PMOS transistor of each inverter between the storage element and the power supply. A semiconductor memory comprising a PMOS transistor for lowering.