JPH06195890A - Controller for phase synchronizing loop - Google Patents

Abstract

PURPOSE:To control a voltage controlled oscillator by means of the synthesized voltage of the phase comparison output of a phase synchronizing loop with an error detection signal. CONSTITUTION:A reproduced signal is converted to a waveform appropriate for identification by means of a equivalent reproducing circuit 1. The output signal is sent to a phase comparator 5 in a PLL circuit 4 and a comparator 2. The equivalently reproduced signal is compared in phase with a clock generated by a voltage controlled oscillator 7 in the PLL circuit 4 and the voltage controlled oscillator 7 is controlled by this compared output. Consequently, the clock as the PLL output is locked on the reproduced signal. The output of the comparator 2 and the reproduced clock of the PLL output are sent to a discriminator 3 and the reproduced digital signal identified by the relevant discriminator 3 is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop control device, and more particularly, a video device using a digital magnetic recording system requires a continuous clock to identify a reproduced signal. The present invention relates to a phase locked loop (PLL) controller for clock recovery.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a demodulation section in a conventional phase locked loop controller, and FIGS.
It is a figure which shows the signal waveform of each part in FIG. 3 in the figure
Reference numeral 1 is a reproduction equivalent circuit, 32 is a comparator, 33 is a discriminator, 34 is a PLL circuit, 35 is a phase comparator, 36 is a low pass filter (LPF), and 37 is a voltage controlled oscillator. Note that the NRZ-I system, which is a basic digital recording system, is shown as an example of the waveform of each part. The analog playback signal output from the head is
The signal is amplified by the head amplifier, is mainly compensated in the high frequency range by the reproduction equivalent circuit 31, and is input to the comparator 32 and the PLL circuit 34 that generates the reproduction clock. The output of the comparator 32 and the regenerated clock generated by the PLL circuit 34 are both sent to the discriminator 33, and the discriminator 33 identifies and outputs the digital signal.

[0003]

As described above, in the conventional PLL circuit which generates a continuous clock signal for identifying the reproduced digital signal, the voltage controlled oscillator is controlled only by the phase comparison output. Therefore, there is a problem in that the phase of the reproduced digital signal and the phase of the continuous clock for identification are deviated due to changes in the characteristics of the circuit components due to power supply fluctuations, temperature fluctuations, and changes over time.

The present invention has been made in view of such circumstances, and the phase-locked oscillator is controlled by a voltage obtained by combining the phase comparison output of the phase-locked loop and the error detection signal. It is intended to provide a loop control device.

[0005]

In order to achieve the above object, the present invention is directed to a video tape recorder using a digital magnetic recording system, in which a voltage control oscillator for generating a reproduction clock signal and a reproduction signal obtained by converting the reproduction signal are used. A phase comparator that compares the phase of an equivalent signal and the recovered clock signal from the voltage controlled oscillator, a comparison output of the phase comparator and an error detection signal are combined to generate a combined signal that controls the voltage controlled oscillator. A phase-locked loop circuit composed of an adder and an error detection output section for generating an error detection signal input to the adder are provided.

[0006]

In the PLL circuit for generating a continuous clock for identifying the reproduced digital signal, the control of the voltage controlled oscillator is controlled by adding the phase comparison output and the signal obtained by detecting the error detection signal. As a result, the phase difference between the reproduction signal and the identification clock can be suppressed.

[0007]

Embodiments will be described below with reference to the drawings. First, the basic configuration of the digital recording signal processing system will be described with reference to FIG. In the figure, 11 is an A / D converter, 12 is a correction code circuit, 13 is a modulator, 14 is a recording equivalent amplifier, 15 is a magnetic head, 16 is a magnetic tape, and 17
Is a magnetic head, 18 is a reproduction / amplification circuit, 19 is a demodulation unit, 2
0 is a reproduction equivalent circuit, 21 is an identification circuit, 22 is a PLL circuit, 23 is a demodulator, 24 is an error correction circuit, and 25 is D /
A converter.

The input video signal is converted into a digital signal by the A / D converter 11, converted into a signal having a property suitable for high-density magnetic recording by the modulator 13, and passed through the recording equivalent amplifier 14 to the magnetic tape. 16 is recorded.
The reproduced digital signal has various losses due to recording and reproduction,
And distortion is caused by intersymbol interference. Furthermore, since it becomes a waveform with a differential characteristic due to the reproduction principle,
The demodulation unit 1 has a waveform suitable for identifying "1" or "0".
It is converted by the reproduction equivalent circuit 20 of the nine. Since the equivalent waveform is a waveform which can distinguish level "1" or "0" of information at the bit position, a clock corresponding to the bit time is generated using the PLL circuit 22,
By performing the voltage comparison at this bit time, the digital signal is identified and reproduced. The reproduced digital signal thus identified passes through the demodulator 23 and the error correction circuit 24, is D / A converted, and is reproduced as a video signal.

FIG. 1 is a block diagram for explaining an embodiment of a demodulation section in a phase locked loop control device according to the present invention. FIGS. 2 (a) to 2 (f) show signal waveforms of respective sections in FIG. FIG. In the figure, 1 is a reproduction equivalent circuit, 2 is a comparator, 3 is a discriminator, 4 is a PLL circuit, 5 is a phase comparator, and 6 is a low pass filter (LPF).
r) and 7 are voltage controlled oscillators, 8 is a detector, 9 is an error detection output section, and 10 is an error correction section.

PLL for generating a reproduction clock for discrimination
The structure and operation of the circuit will be described below. The reproduced signal is reproduced into a waveform suitable for identification and reproduced by an equivalent circuit 1.
Is converted by. The output signal is sent to the phase comparator 5 of the PLL circuit 4 and the comparator 2 to determine whether it is "1" or "0". In the PLL circuit 4, the reproduced and equalized signal and the clock generated by the voltage controlled oscillator 7 are phase-compared, and the voltage controlled oscillator 7 is controlled by this comparison output. With the above operation, the clock that is the PLL output is locked to the reproduction signal. The output of the comparator 2 and the recovered clock, which is the PLL output, are sent to the discriminator 3 and the discriminator 3
A more identified reproduced digital signal is obtained.

The reproduced digital signal is processed through the demodulation period 23 and the error correction circuit 24 according to the block shown in FIG. The reproduced signal that was compared at the time of identification,
When the phase of the reproduction clock is shifted, the error detection output at point D increases. This error detection output is detected, and the detected output (point B) and the phase comparison output (point A) of the PLL circuit are added. By controlling the voltage controlled oscillator 7 with the added voltage C, the phases of the reproduced signal and the reproduced clock that have been compared are controlled so that the error detection output is reduced.

As described above, in the present invention, in order to identify the reproduced digital signal, when the PLL circuit is used to generate continuous clocks, the control of the voltage controlled oscillator of the PLL circuit is changed to the phase comparison signal. By controlling with the voltage which added the error detection signal, the phase of the continuous clock which is the PLL output is controlled so that the error detection signal is minimized.

[0013]

As is apparent from the above description, the present invention has the following effects. That is, when the phase of the reproduced digital signal and the continuous clock for identification are shifted,
An error easily occurs in the identified reproduced digital signal output, and the error signal detected based on the demodulator output increases. Therefore, by adding the signal obtained by detecting the error detection signal and the phase comparison output of the PLL circuit to control the voltage controlled oscillator of the PLL circuit, it is possible to reduce the phase shift between the reproduction signal and the reproduction clock. That is, the reproduced signal when identifying the reproduced digital signal,
The phase relationship of continuous clocks required for identifying the reproduced signal is controlled so that the error detection output is reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a demodulation unit in a phase locked loop control device according to the present invention.

FIG. 2 is a diagram showing a signal waveform of each part in FIG.

FIG. 3 is a basic configuration diagram of a digital recording signal processing system.

FIG. 4 is a block diagram of a demodulation unit in a conventional phase locked loop control device.

5 is a diagram showing a signal waveform of each part in FIG.

[Explanation of symbols]

1 ... Reproduction equivalent circuit, 2 ... Comparator, 3 ... Discriminator, 4
... PLL circuit, 5 ... Phase comparator, 6 ... Low pass filter (LPF), 7 ... Voltage controlled oscillator,
8 ... Detector, 9 ... Error detection output section, 10 ... Error correction section.

Claims (1)

[Claims] 1. A video tape recorder using a digital magnetic recording system, wherein a voltage controlled oscillator for generating a reproduction clock signal, a reproduction equivalent signal obtained by converting the reproduction signal and a reproduction clock signal from the voltage controlled oscillator are phase-compared. Input to the adder, and a phase-locked loop circuit comprising a phase comparator for generating a composite signal for synthesizing the comparison output of the phase comparator and the error detection signal and controlling the voltage controlled oscillator. And an error detection output unit for generating an error detection signal for controlling the phase locked loop.