JPH0619423A - Driving circuit of matrix display device - Google Patents

Abstract

PURPOSE:To provide the driving circuit of the matrix display device which decreases the scale of a decoder circuit while suppressing an increase in circuit cost. CONSTITUTION:The driving circuit of the matrix display device which is constituted by arranging display pixels in a matrix shape and makes a gradational display on the display pixels by applying a driving voltage corresponding to specific display data to the display pixels is equipped with an encoding circuit 1 as an encoding means which encodes the display data, a data register 2 as a data holding means which holds the data encoded by the encoding circuit 1, and a voltage applying means 3 which applies the specific driving voltage to the display pixels according to the encoded data held in the data register 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix display device drive circuit, and more particularly to a matrix for multi-gradation display suitable for use in the field of drive circuits for flat panel displays such as liquid crystal display devices. The present invention relates to a drive circuit of a display device. BACKGROUND OF THE INVENTION In recent years, with the miniaturization of information terminal devices such as computer systems, for example, many small liquid crystal display devices with small power consumption have been developed as display devices.

Above all, an active matrix type color liquid crystal display device using a TFT (Thin Film Transistor) is
Due to its excellent display quality, the conventional CRT (Cathode Ray Tu
is expected as an alternative display device. But,
The TFT active matrix type color liquid crystal display device is
Although having the above-mentioned advantages, the driving circuit for multi-gradation has a high cost, which makes the display device more expensive than a CRT.

Therefore, cost reduction of the drive circuit of the TFT active matrix type color liquid crystal display device is required.

[0004]

2. Description of the Related Art As a conventional drive circuit for a matrix display device of this type, there is, for example, one shown in FIG. FIG. 5 shows a main configuration of one output of the drive circuit for 8-gradation display. The drive circuit of this matrix display device supplies a power supply voltage for driving a data electrode via a drive line DL connected to each of a plurality of data electrodes provided in the liquid crystal display device. 10 and
Drive line D connected to the power supply voltage supply means 10 and the data electrode
The analog switch 11 for turning on / off the L and the on / off of the analog switch 11 based on predetermined display data
It is composed of a decoder circuit 12 for controlling turning off.

The power supply voltage supply means 10 corresponds to the number of gradations.
8 kinds of power supply voltage V₁~ V₈Is to supply
Power supply voltage V₁~ V₈Are in the range of 2V to 5V respectively
It is a value obtained by dividing the voltage. Analog switch 11
Are the eight types of power supplies supplied from the power supply voltage supply means 10.
Voltage V₁~ V₈8 switches S corresponding to
Consists of W0 to SW7, any of switches SW0 to SW7
By turning on only one of them, the power supply voltage V ₁~ V
₈Output any one of the power supply voltage to the drive line DL
It is a thing.

The decoder circuit 12 controls so that only one of the analog switches 11 is turned on based on display data consisting of 3-bit digital inputs D _{2 to} D ₀ input from the outside. is there. [Table 1] shows the relationship between the digital inputs D _{2 to} D ₀ and the selected voltage.

[0007]

[Table 1]

In the above configuration, for example, when "010" is input as the digital input, the decoder circuit 1
2 turns on only the switch SW2 (see FIG. 5), the power supply voltage V ₃ is applied to the data electrode via the drive line DL, and a predetermined gradation is displayed. However, such a configuration requires a power supply voltage and a switch for the required gradation, which becomes a bottleneck for performing multi-gradation display.

Therefore, the present applicant has previously filed Japanese Patent Application No. 2-25.
No. 9300 and Japanese Patent Application No. 3-116036,
A drive circuit as shown in FIG. 6 is proposed. FIG. 6 shows 16
The structure of the main part for one output of the drive circuit for gradation display is shown. Like the drive circuit shown in FIG. 5, the drive circuit of this matrix display device drives this data electrode via the drive line DL connected to each of the plurality of data electrodes provided in the liquid crystal display device. Power supply voltage supply means 10 for supplying the power supply voltage, the analog switch 11 for turning on / off the power supply voltage supply means 10 and the drive line DL connected to the data electrode, and the analog switch 11 based on predetermined display data. The decoder circuit 12 controls ON / OFF.

However, the power supply voltage supply means 10 does not supply 16 kinds of power supply voltages corresponding to the number of gradations,
9 kinds of power supply voltages V _{1 to} V ₉ are supplied, and ₉ analog switches 11 are provided corresponding to the 9 kinds of power supply voltages V _{1 to} V ₉ supplied from the power supply voltage supply means 10. Switch SW0 to SW8, switch S
Only one of W0 to SW8 or adjacent 2
By turning on two switches, the power supply voltage V _{1 to} V
Any one of the power supply voltages of ₉ or two adjacent power supply voltages is output to the drive line DL.

The decoder circuit 12 turns on any one of the analog switches 11 or two adjacent switches based on the display data consisting of 4-bit digital inputs D _{3 to} D ₀ input from the outside. To control. Shows the relationship between the voltage to be selected as the digital input D ₃ to D ₀ in Table 2.

[0012]

[Table 2]

In the above configuration, for example, when "0111" is input as a digital input, the decoder circuit 12 turns on the switches SW3 and SW4 (see FIG. 6), and the power source voltages V ₄ and V ₅ are divided. Drive line D
It is given to the data electrode via L and a predetermined gradation is displayed. [Table 3] shows the relationship between the gradation to be displayed and the switch to be turned on.

[0014]

[Table 3]

That is, in this case, when one switch is selected, a predetermined power supply voltage is output from among eight kinds of power supply voltages, so that the gradation of 8 gradations is obtained as in the conventional example shown in FIG. In addition to the gradation display, when two switches are selected, the gradation display of 8 gradations can be further performed by the voltage division by the ON resistance, and a total of 16 gradations (actually 17 gradations) can be displayed. It will be possible.

[0016]

However, in the conventional drive circuit of the matrix display device as described above,
Display data D ₃ to obtain 16 levels of power supply voltage
Since it is necessary to control the on / off of the analog switch 11 based on D ₀ , the display data D _{3 to} D ₀ are decoded to control the on / off of the switches SW0 to SW8. There were some problems to mention.

That is, for example, in the conventional example shown in FIG. 5, since the switch SW2 is turned on only when the display data is 2 (“010”), / D ₂ × D ₁ × / D ₀ (hereinafter, / Although it can be controlled by the 3-input AND gate shown in (showing the top bar), in the conventional example shown in FIG. 6, the switch SW2 has display data of 3, 4, 5 (“0011”,
"0100", "0101") because if it is necessary to turn on _{the, / D 3 × / D 2} × D 1 × D 0 + / D 3 × D 2
Decoding as shown by x / D ₁ is necessary, which means that the scale of the decoding circuit is doubled as compared with the drive circuit shown in FIG.

[Object] Therefore, an object of the present invention is to provide a drive circuit for a matrix display device which reduces the scale of a decoder circuit while suppressing an increase in circuit cost.

[0019]

In order to achieve the above object, a drive circuit of a matrix display device according to the present invention has a matrix display in which a plurality of display pixels are arranged in a matrix as shown in the principle diagram of FIG. A drive circuit of a matrix display device that applies a drive voltage corresponding to predetermined display data to each display pixel of the device to perform gradation display by each display pixel, and a code for encoding the display data. Based on the encoding circuit 1 which is the encoding means, the data register 2 which is the data retaining means which retains the encoded data encoded by the encoding circuit 1, and the encoded data which is retained in the data register 2. A voltage applying means 3 for applying a predetermined drive voltage to the display pixel is provided.

The voltage applying means 3 includes a decoder 4 for decoding the coded data held in the data holding means, and data decoded by the decoder 4 from among n-level drive voltages prepared in advance. An analog switch 5 for selecting one of the n driving voltages or two adjacent driving voltages based on the above, and is configured to apply a driving voltage of more than n voltage levels. Is preferred.

In this case, the encoding circuit 1 performs the alternating binary encoding of the display data, and the data register 2 holds the data having the number of bits larger than the number of bits of the display data. It is effective that the encoding circuit 1 redundantly encodes the display data.

[0022]

According to the present invention, the display data is encoded by the encoding means by, for example, alternating binary encoding or redundant encoding, and is decoded based on the encoded data. Decoding is simplified. That is, the increase in circuit cost is suppressed by generating a plurality of power supply voltages by the combination of analog switches, and the decoding of display data is simplified, so that the scale of the decoder circuit is reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the drive circuit of the matrix display device according to the present invention, and is a schematic block diagram showing the configuration of the main part thereof. First, the configuration will be described.

In FIG. 2, the same numbers as the numbers given to the principle diagram shown in FIG. 1 indicate the same parts. Further, the main part (not shown) of this embodiment has the same configuration as the conventional example shown in FIG. The drive circuit of the matrix display device of this embodiment is
It is roughly divided into a coding circuit 1 which is a coding means, a data register 2 which is a data holding means, and a voltage applying means 3, and the voltage applying means is composed of a decoder 4 and an analog switch 5.

Numeral 6 is a shift register and numeral 7 is a latch. The encoding circuit 1 encodes display data based on a predetermined encoding procedure. Data register 2
Is data of a plurality of pixels encoded by the encoding circuit 1, that is, 4 bits (16 gradations) × 80 pixels,
It is a register for sequentially holding.

The shift register 6 is an 80-bit register for sequentially selecting the data register 2. The latch 7 is a latch circuit for 4 bits × 80 pixels which holds the data held in the data register 2 only for the timing of one horizontal period. The decoder 4 outputs a control signal to the analog switch 5 based on the latched data.

Similar to the conventional example shown in FIG. 6, the analog switch 5 is a switch of 9 × 80 pixels for selecting a predetermined power supply voltage from nine kinds of power supply voltages. In addition,
The display data in this embodiment is 16 gradations, that is, 4
This is a bit signal, and as in [Table 2] shown in FIG. 6, “000 is displayed in correspondence with dark → bright display luminance of each pixel.
It is 0 ”→“ 1111 ”.

Next, the operation will be described. First, the encoding circuit 1
The display data to be displayed on the display device by [Table 4]
It is encoded as shown in.

[0029]

[Table 4]

Specifically, in the order of display data (luminance)
In contrast, only 1 bit of encoded data changes
Conversion by alternating binary encoding, for example, 3 → 2, 4 → 6,
5 → 14 (“0011” → “0010”, “0100”
→ "0110", "0101" → "1110")
Is converted to. As a result, the switch SW2 is controlled.
The decoder 4 for storing the data from the latch 7 is 2,
It is enough to decode the signal when it becomes 6, 14,
Is / D₃× D ₁× / D₀+ D₂× D₁× / D₀Can be expressed as
Therefore, as shown in FIG.
Because there is no 4-input AND gate,
The circuit scale can be reduced.

FIG. 3A shows a conventional decoding circuit, FIG.
FIG. 9B shows a circuit configuration example of the decoding circuit of this embodiment.
That is, the circuit scale of the decoders for controlling the other analog switches can be similarly reduced. In particular, since the same circuit has 80 circuits in this embodiment, the circuit scale can be considerably reduced as a whole.

The encoding method is not limited to that shown in [Table 4], and, for example, alternation 2 as shown in [Table 5].
It may be a binary coded code or another coded code, as long as the code of the decoder circuit can be finally reduced.

[0033]

[Table 5]

A specific example of this will be described based on [Table 6].

[0035]

[Table 6]

The encoding shown in [Table 6] is obtained by temporarily converting 4-bit display data into 5-bit data. In this case, since the converted data has a redundant portion, Is used to simplify the decoder. That is, focusing on the redundant part, for example, 3 → 1
1, 4 → 10, 5 → 2 (“0011” → “1011”,
“0100” → “1010”, “0101” → “001
0 ") is converted, and 3 is DON'TCARE in the converted data, the switch SW
The control of 2 can be performed by decoding as shown by / D ₄ × / D ₂ × D _1. Therefore, by adding the data register 2 and the latch 7 by 1 bit in FIG.
As shown in FIG. 4, a decoding circuit can be realized by a circuit that is half or less of the conventional circuit.

As described above, in the present embodiment, in order to simplify the decoder structure, the display data is once encoded and held in the data register, so that the number of pixels in one row can be obtained by adding one encoding circuit. The decoder circuit can be downsized. Therefore, the circuit scale can be reduced as a whole, and the cost of the drive circuit can be reduced.

In general, driving a matrix display device requires data driving circuits of about 640 to 1280,
Usually, it is realized by using a plurality of drive circuits in which about 80 to 240 drive circuits are integrated. In this case, an encoding circuit may be integrated and provided for each drive circuit, or display data may be converted by one encoding circuit as a whole and supplied to each drive circuit.

For the purpose of increasing the display colors and the like, a color palette IC is used for the display device, and for example, 4 bits (= 1
A circuit for converting 6-color data into 12-bit (= 4096 colors) data may be used, but the encoding process in this embodiment may be used for this palette conversion process.

[0040]

According to the present invention, the display data can be decoded by the encoding means by the alternating binary coding or the redundant coding and the decoding can be performed based on the coded data. Can be simplified. Therefore, it is possible to suppress an increase in circuit cost by generating a plurality of power supply voltages by combining the analog switches, and it is possible to reduce the scale of the decoder circuit by simplifying the decoding of the display data.

[Brief description of drawings]

FIG. 1 is a principle diagram of a drive circuit of a matrix display device of the present invention.

FIG. 2 is a schematic block diagram showing a main configuration of the present embodiment.

FIG. 3 is a circuit diagram for explaining a circuit configuration example of a decoding circuit in this embodiment.

FIG. 4 is a circuit diagram for explaining a circuit configuration example of a decoding circuit in another embodiment.

FIG. 5 is a diagram showing a configuration of a main part for one output of a drive circuit which performs 8-gradation display.

FIG. 6 is a diagram showing a configuration of a main part for one output of a drive circuit which performs 16 gradation display.

[Explanation of symbols]

 1 Encoding circuit (encoding means) 2 Data register (data holding means) 3 Voltage applying means 4 Decoder 5 Analog switch 6 Shift register 7 Latch 10 Power supply voltage supplying means 11 Analog switch 12 Decoder circuit DL drive line

Claims (4)

[Claims] 1. A gradation display is performed by applying a drive voltage corresponding to predetermined display data to each display pixel of a matrix display device having a plurality of display pixels arranged in a matrix. A driving circuit of a matrix display device for performing, comprising: an encoding means for encoding the display data, a data holding means for holding the encoded data encoded by the encoding means, and a data holding means for holding the encoded data. A drive circuit for applying a predetermined drive voltage to the display pixel based on the encoded data, and a drive circuit for a matrix display device. 2. The voltage applying means is based on a decoder which decodes the encoded data held in the data holding means, and data which is decoded by the decoder from n-level drive voltages prepared in advance. 1 of the n driving voltages
2. The drive circuit for a matrix display device according to claim 1, further comprising: an analog switch for selecting one or two adjacent drive voltages, and applying a drive voltage having a voltage level higher than n. 3. The drive circuit for a matrix display device according to claim 2, wherein the encoding means performs alternating binary encoding of the display data. 4. The data holding means is a data register for holding data having a number of bits larger than the number of bits of display data, and the encoding means redundantly encodes the display data. The drive circuit of the matrix display device according to claim 2.