JPH06188387A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the reliability of capacity for stabilizing a high voltage for word wire driver. CONSTITUTION:In a semiconductor memory device containing a step-up circuit 400 constantly generating a high voltage and a word wire drive circuit (WDi) for transmitting a high voltage from the step-up circuit to a selection word wire 3, the capacitor for stabilizing the high voltage generated by the step-up circuit is made of a series body of a capacitive element utilizing FET having a gate insulation film thickness equivalent to an insulation gate type field effect transistor (FET) within the memory device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to improvement of a circuit for transmitting a drive signal boosted to a potential level higher than an internal power supply voltage onto a selected word line. More specifically, the present invention relates to a structure for stabilizing the output voltage of a booster circuit used to generate a boosted word line drive signal.

[0002]

2. Description of the Related Art FIG. 25 is a diagram schematically showing an overall structure of a dynamic random access memory conventionally used. In FIG. 25, the dynamic random access memory responds to a memory cell array MA in which memory cells for storing information are arranged in a matrix of rows and columns, and external addresses A0-An provided from the outside. An address buffer AB for generating an internal address, an X decoder ADX for receiving an internal row address from the address buffer AB and generating a word line selection signal for selecting a corresponding row of the memory cell array MA, and an X decoder ADX. In response to the word line selection signal, the word line drive circuit W for amplifying and transmitting the word line selection signal to the selected row (word line).
D and a Y decoder ADY which receives an internal column address from address buffer AB and generates a column selection signal for selecting a corresponding column of memory cell array MA.

The address buffer AB has a row address designating a row of the memory cell array MA and a memory cell array M.
A column address designating a column of A is time-divisionally received, an internal row address and an internal column address are generated at predetermined timings, and they are given to an X decoder ADX and a Y decoder ADY, respectively.

In order to read the data of the memory cell designated by the external address A0-An (the memory cell provided corresponding to the intersection of the selected row and the selected column), the X decoder ADX is used. In response to the column selection signal from the Y decoder ADY, and a sense amplifier that detects and amplifies the data of the memory cell connected to the row to which the drive signal is transmitted by the word line drive circuit WD. In the memory cell array MA, an input / output interface (IO) for transmitting the data of the memory cell connected to the corresponding column of the memory cells of the selected row (word line) to the output buffer OB. Figure 25
, The sense amplifier and the input / output interface (I
O) and are indicated by one block SI.

The output buffer OB generates external read data from the internal data transmitted via the input / output interface (IO) and outputs it to the outside of the device.

In FIG. 25, only output buffer OB for reading data is shown. An input buffer is also provided for writing data. This input buffer may be configured to input data to the outside of the device via the same pin terminal as output buffer OB, or may be configured to input data via a different pin terminal. The input buffer generates internal write data from external write data and writes the data to the selected memory cell via the input / output interface (IO).

A control signal generating system peripheral circuit CG for generating a control signal for controlling various operation timings of the dynamic random access memory is provided. The control signal generating peripheral circuit CG has a control clock signal applied from the outside, that is, a row address strobe signal / RAS and a column address strobe signal / CAS.
In response to the write enable signal / WE, a word line drive signal φx, an equalize signal φE, which will be described later,
Precharge signal φp, sense amplifier activation signals φA and φB, etc. are generated. Control signal generation system peripheral circuit CG
Also generates a precharge potential VB for precharging the bit line and the like to a predetermined potential.

FIG. 26 is a diagram showing a schematic structure of the memory cell array shown in FIG. 25 and its related circuits. Figure 2
6, the memory cell array MA includes a plurality of memory cells 1 arranged in a matrix of rows and columns (n rows and m columns).
, Word lines WL1, WL2, ... WLn provided corresponding to the rows of the memory cell array MA, and bit lines BL0 arranged corresponding to the respective columns of the memory cell array MA.
/ BL0, BL1, / BL1, ... BLm, / BLm are included. Bit line BL (generally indicates bit lines BL0 to BLm) and bit line / BL (complementary bit lines / BL0 to / B)
(Lm is generically shown) constitutes a folded complementary bit line pair, and one pair of bit lines connects the memory cells 1 in one column of the memory cell array MA.

In FIG. 26, bit line BL0 and complementary bit line / BL0 form one bit line pair, bit line BL1 and complementary bit line / BL1 form one pair of bit lines, and so on. Thus, the bit line BLm and the complementary bit line / BLm form a bit line pair.

Memory cell 1 is provided corresponding to the intersection of one word line and a pair of bit lines. Ie 1
A memory cell 1 is provided at an intersection of a word line WL (word lines WL1 to WLn are generically shown) and one bit line of a bit line pair BL, / BL.

Bit line pair BL0, / BL0, ... BLm,
Each / BLm is provided with a precharge / equalize (P / E) circuit 150 for equalizing the potential of each bit line and precharging to a predetermined potential VB during standby of the dynamic random access memory. . Each of precharge / equalize circuits 150 becomes conductive in response to precharge instructing signal φP and equalize instructing signal φE, and each bit line BL0, /
The potentials BL0 to BLm, / BLm are precharged and equalized to a predetermined precharge potential VB.

A sense amplifier circuit 160 for detecting and amplifying the data in the selected memory cell is provided for each of the bit line pair BL and / BL. The sense amplifier circuit 160 is activated in response to the first sense amplifier drive signal φA and the second sense amplifier drive signal φB transmitted through the signal lines 162 and 164, respectively, and the potential difference between the corresponding bit line pair. Is detected and differentially amplified.

Bit line pair BL0, / BL0, ... BLm,
For each of / BLm, the column select gates T0a and T0b are turned on in response to the column select signals from the Y decoder ADY in response to Y0 to Ym and connect the corresponding bit line pairs to the internal data buses DB and / DB. , T1a, T1b, ... Tn
a and Tnb are provided. Internal data bus DB,
/ DB is connected to the output buffer OB shown in FIG.

The column selection gates T0a and T0b are provided for the bit line pair BL0 and / BL0, and the column selection gate T1 is provided.
a and T1b are provided for bit line pair BL1 and / BL1, and column select gates TMa and Tmb are provided for bit line pair BLm and / BLm.

Column selection signals Y0 to Y0 from the Y decoder ADY
Only one Ym is activated according to the column address,
The corresponding column select gate is turned on. Thereby, the corresponding bit line pair is connected to internal data buses B and / DB.

FIG. 27 is a diagram showing a structure of a portion related to one word line in the structure shown in FIG.
It is a figure which shows concretely the structure of the circuit which drives a word line.

In FIG. 27, the memory cell 1 arranged at the intersection of the word line 3 (WLi) and the bit line 2 (BLj) stores the information in the form of electric charge in the memory capacitor 6.
And the word line drive signal φxi transmitted on the word line 3.
In response to, it is turned on and includes a select transistor 5 connecting memory capacitor 6 to bit line 2. The selection transistor 5 is composed of an n-channel insulated gate field effect transistor (hereinafter, simply referred to as n-FET), its gate is connected to the word line 3, its source is connected to the bit line 2, and its drain is It is connected to the storage node 4.

One electrode of the memory capacitor 6 is connected to the drain of the selection transistor 5 via the storage node 4, and the other electrode thereof is normally 1/2 of the operating power supply potential Vcc.
Connected to receive the potential of.

A parasitic capacitance 7 is attached to the word line 3.
The parasitic capacitance 7 is the selection transistor 5 of the memory cell 1.
Including the gate capacitance of.

Corresponding to word line 3 (WLi), the internal row address from the address buffer is decoded, and a word line selection signal for word line 3 (WLi) is generated (unit) X decoder ADXi and X decoder ADXi. Of the output of the word line driver WD through the node 9 and transmits the word line drive signal φxi to the word line 3 (unit) Word line driver WD
i is provided.

When in the selected state, X decoder ADXi generates an "H" signal on node 9.

The word line driver WDi passes the signal of the X decoder ADXi provided on the node 9 through n-.
In response to the signal transmitted from the FET 14 to the node 15, the n-FET 11 transmitting the word line drive signal φx applied to the node 10 to the word line 3 via the node 13, and the node An inverter circuit 16 for inverting the output of the X decoder ADX given to
It includes an n-FET 12 that discharges the potential of word line 3 (WLi) to the ground potential level via node 13 in response to the output of inverter circuit 16.

The n-FET 14 receives the internal operating power supply voltage Vcc at its gate. Word line drive signal φx applied to node 10 is a signal boosted to a potential level higher than internal operating power supply voltage Vcc. In this case, n-F
The self-bootstrap function of ET11 raises the potential of the node 15 (due to capacitive coupling between the gate and drain of the n-FET). At this time, in order to prevent the boosted potential of node 15 from being transmitted to node 9, n−
The FET 14 is provided. That is, the n-FET 14 functions as a decoupling transistor.

Inverter circuit 16 has a CMOS structure, and its operating power supply voltage is set to internal operating power supply voltage Vcc applied to node 8 (not shown).

This word line driver WDi has a function of receiving a word line selection signal of the internal operation power supply voltage Vcc level from X decoder ADxi and giving this signal the ability to drive word line 3.

In order to generate word line drive signal φx having a boosted potential level, internal operation power supply voltage Vcc is constantly boosted in response to pulsed repetitive signal φc to generate boosted high voltage Vpp. High voltage generation circuit HVG
And the high voltage V generated by this high voltage generation circuit HVG
It includes a word line drive signal generation circuit HSG transmitting pp as a word line drive signal φx onto node 18 in response to clock signal φx0. Clock signal φx0 is generated at a timing earlier than the determination of the output potential of X decoder ADXi (generated after a lapse of a predetermined time in response to the fall of row address strobe signal / RAS).

The pulsed repetitive signal φc is generated from an on-chip ring oscillator or is externally applied.

High voltage generating circuit HVG is an n-FET provided between internal power supply voltage supply node 8 and node 32.
29, and n provided between the node 35 and the node 27.
-FET 30, a capacitor 31 provided between nodes 28 and 35, and a capacitor 33 provided between output node 27 and a second power supply voltage supply source (ground potential source).

The n-FET 29 has its gate and drain connected to each other, and has an internal operating power supply voltage Vc applied to the node 8.
Charge node 32 according to c. The n-FET 30 also has a gate and a drain connected to each other and functions as a diode. The capacitance 31 capacitively couples the node 28 and the node 35. The parasitic capacitance 34 is present at the node 35 (node 32).
Is attached. The capacitor 33 has a function of stabilizing the high voltage Vpp generated at the output node 27. The capacitor 31 has a function of boosting the potential level of the node 35 by the repeated signal φc. The high voltage generation circuit HVG generates a high voltage Vpp having a voltage level higher than the internal power supply voltage Vcc by the charge pump function of the capacitor 31.

The word line drive signal generation circuit HSG includes a p-channel insulated gate field effect transistor (hereinafter simply referred to as p-FET) provided between the node 17 and the node 25.
23), a p-FET 20 provided between the node 17 and the node 22, an n-FET 24 that discharges the node 25 to the ground potential level in response to a control signal φx0 applied to the node 19, and a control signal. An inverter circuit 26 that inverts φx0, and an n-FE that lowers the potential of the node 22 to the ground level in response to the output of the inverter circuit 26.
Including T21. The gates and drains of the p-FET 23 and the p-FET 20 are cross-coupled. High voltage Vpp from high voltage generating circuit HVG is transmitted to node 17. Output node 18 of word line drive signal generation circuit HSG
The word line drive signal φx is generated at. The word line drive signal generation circuit HSG supplies the control signal φxo of the internal operation power supply voltage Vcc level applied to the node 19 to the high voltage Vp.
It has a function of converting to a p-level word line drive signal φx. The structure of a circuit having this function is disclosed in, for example, Japanese Patent Laid-Open No.
No. 9-114337.

High voltage generation circuit HVG and word line drive signal generation circuit HSG are included in control signal generation system peripheral circuit CSG shown in FIG. In addition, the inverter circuit 26,
It has a CMOS structure and operates using the internal operating power supply voltage Vcc as the operating power supply voltage. The high voltage generation circuit HVG and the word line drive signal generation circuit HSG are provided commonly to the word line drivers provided in each of the word lines 3 (word lines WL0 to WLn). Next, the operation of each circuit portion shown in FIG. 27 will be described.

First, the operation of the high voltage generation circuit HVG will be described with reference to FIG. 28 which is an operation waveform diagram thereof. Repetitive signal φc applied to node 28 is assumed to be a pulse signal generated from an on-chip or external oscillator circuit utilizing, for example, ring oscillation and having a predetermined cycle and pulse width.

When the internal operation power supply voltage Vcc is applied to the internal operation power supply voltage supply terminal 8, the potentials of the nodes 32 and 35 are charged to the potential level of Vcc-VTN by the charging n-FET 29. Here, VTN is n-FET 29
Is the threshold voltage of. Further, the n-FET 30 for rectification
Causes the potential level of the node 27 to be Vcc-2.VTN.
Is charged to the potential level of.

When a repeated signal φc is applied to node 28, the boosting operation in high voltage generating circuit HVG is started. To simplify the description, the potential levels of the node 32 and the output node 27 are the above-mentioned potential level Vc.
After the potential levels of c-VTN and Vcc-2.VTN are stabilized, the boosting operation in this high voltage generation circuit HVG is started.

When the signal φc rises repeatedly after the potentials of the node 32 and the output node 27 have become Vcc-VTN and Vcc-2.VTN, respectively, charges are injected into the node 35 through the boosting capacitor 31, and this Node 35
The potential of rises. Due to the rise in the potential of the node 35,
Electric charges are supplied to the output node 27 through the n-FET 30, and the potential V27 of the output node 27 rises by ΔV27 = C31 · Vcc / (C31 + C33). Here, C31 indicates the capacitance value of the boosting capacitance 31, and C33 indicates the capacitance value of the stabilizing capacitance 33.

Next, when the repetitive signal φc falls, the potential of the node 32 (node 35) is lowered by the capacitive coupling by the boosting capacitance 31. However, the potential V27 is
Since the gate and the drain of the n-FET 30 are connected and functioning as a diode, the n-FET 30 becomes non-conductive, the potential of the output node 27 does not decrease, and rises when the previous repetitive signal φc rises. Hold the potential. The potentials of nodes 32 and 35 which have dropped in response to the fall of repetitive signal φc are charged by n-FET 29 and returned to the potential Vcc-VTN level.

By repeating the above operation, charges are injected into the nodes 32 and 35 through the booster capacitance 31,
Every time the potential rises, charges are injected into the output node 27 through the n-FET 30, and the potential of the output node 27 gradually rises.

The finally reached potential V32max of the node 32 (node 35) is V32max = (Vcc-VTN) + C31.Vcc / (C31 + C34). Here, C34 indicates the capacitance value of the parasitic capacitance 34. The potential V27 of the output node 27 at this time is n higher than the potential V32 (= V35) of the node 32 (node 35).
-The value becomes lower by the threshold voltage VTN of the FET 30.
That is, the final potential V27max of the output node 27
Is V27max = V32max-VTN = (Vcc-2.VTN) + C31.Vcc / (C31 + C34).

In an actual circuit, it is easy to make the capacitance value C31 of the booster capacitance 31 sufficiently larger than the capacitance value C34 of the parasitic capacitance 34. Therefore, approximately, the third term in the above two equations is the internal operating power supply voltage Vc.
is equal to c. Now, Vcc = 3.3V, VTN = 0.
Assuming 8 V, the potential V of the output node 27 is
27max is V27max = 2 (Vcc-VTN) = 5.0 (V). That is, the potential V27max of the output node 27
Has a large value of about 1.5 times the internal operating power supply voltage Vcc. This high voltage is stabilized by the stabilizing capacitor 33 having a large capacitance value.

Next, the operation of the word line drive signal generating circuit and the word line driver will be described with reference to the operation waveform diagram of FIG.

At time t0, when the control signal φx0 is at "L" level, the n-FET 24 is off, while the n-FET 21 is turned on by the inverter circuit 26. As a result, the potential of the node 22 becomes "L" of the ground potential level, and the potential of the node 25 becomes p-FET.
It attains the high voltage Vpp level applied to node 17 through 23. When the potential of the node 25 reaches the high voltage Vpp level, the p-FET 20 is completely turned off, the potential of the node 22 is surely discharged to the ground potential level through the n-FET 20, and the potential of the word line drive signal φx. The level becomes the ground potential level completely.

On the other hand, in the word line driver WDi, the output potential of the X decoder ADXi (potential of the node 9) is "L" (ground potential level), the n-FET 12 is on and the n-FET 11 is off. . As a result, the potential level of the word line drive signal φxi on the word line 3 becomes "L" which is the ground potential level.

Then, a row address strobe signal / R
When AS (see FIG. 25) falls to "L", the row selection operation starts. In response to the fall of row address strobe signal / RAS, X decoder ADX (see FIG. 25) executes a row selecting operation. Now, assume that the (unit) X decoder ADXi shown in FIG. 27 is selected.

When the potential level of node 9 rises to the internal power supply voltage Vcc level at time t1, the output of inverter circuit 16 of word line driver WDi attains the ground potential level of "L", and n-FET 12 is turned off. Then, the node 15 is charged from the node 9 through the n-FET 14 and its potential level rises. An n-FET 14 is provided between the node 9 and the node 15, and the gate of the n-FET 14 is connected to the power supply voltage supply node 8 which supplies the internal operating power supply voltage Vcc.
Therefore, the potential level of node 15 is Vcc-VTN.
Rises to the potential level of. Where VTN is n-FET
14 threshold voltage. As a result, n-FET1
1 is turned on, and word line 3 is discharged through n-FETs 11 and 21 to maintain the ground potential level.

When the potential level on node 9 stabilizes, control signal φx0 applied to node 19 rises to "H" at time t2. Control signal φx0 rises to the level of internal operation power supply voltage Vcc in response to the fall of row address strobe signal / RAS after a lapse of a predetermined time. When the control signal φx0 rises to the level of the internal operation power supply voltage Vcc, the n-FET 24 is turned on and n
-The FET 21 is turned off. This allows node 2
5 is discharged to the ground potential level by n-FET 24, and p-FET 20 is turned on in response to this, raising the potential of node 22. Finally, p-FET2
When the node 3 is turned off and the node 25 drops to the ground potential level, the potential level of the node 22 becomes p-FET2.
It goes to the high voltage Vpp level applied to node 17 via 0. As a result, the word line drive signal φx is generated.

In the word line driver WDi, when the high voltage Vpp level word line drive signal φx is applied to the node 10, the potential level of the node 15 becomes n-FET1.
Due to the self-bootstrap function of 1 (due to capacitive coupling between the gate and drain of the n-FET), the potential level of the node 15 corresponds to the voltage change of the node 10 (high voltage Vp
p) only rises. As a result, the potential level of the node 15 is Vcc-VTN + Vpp level, that is, Vpp +.
The potential level of the word line drive signal φxi transmitted to the word line 3 rises to the level of the high voltage Vpp without exceeding the VTN and without the loss of the threshold voltage in the n-FET 11.

When the word line drive signal φxi transmitted on the word line 3 rises to the high voltage Vpp level, the select transistor 5 in the memory cell 1 is turned on at a high speed, and the select transistor ( n-F
ET) memory capacity 6 without loss of threshold voltage 6
The charges stored in are transferred to the bit line 2.

After that, the sense operation of the sense amplifier and the like are performed to read or write the data of the selected memory cell.

When one memory cycle is completed, control signal φx0 falls to "L" at time t3, the output of X decoder ADXi also falls to "L", and the potentials of each signal and node at time t0. Return to the same state as.

Here, the charging operation of the word line 3, that is, the rise of the potential thereof will be described in detail as follows.

The word line 3 is charged by the high voltage generating circuit HV.
This is realized by transferring charges from the stabilizing capacitance 33 included in G to the parasitic capacitance 7 of the word line 3. Therefore, the potential level of the output node 27 of the high voltage generating circuit is such that charges are transferred to the word line 3 when the word line is selected.
Somewhat lower. However, if the capacitance value of the stabilizing capacitance 33 is set to a value that is sufficiently larger than the capacitance value of the parasitic capacitance 7 of the word line 3, the potential level of the output node 27 hardly decreases, and therefore the potential level of the selected word line is reduced. Can hold the high voltage Vpp level.

That is, the potential level V (W of the word line 3
Since L) is given by V (WL) = C33 · Vpp / (C33 + C7), if the capacitance value C7 of the parasitic capacitance 7 is a value that can be ignored compared to the capacitance value C33 of the stabilizing capacitance 33, The potential level on word line 3 can be the high voltage Vpp level.

From the viewpoint of high density and high integration, it is necessary to use, as the stabilizing capacitor 33, a space-efficient capacitor that can realize a relatively large capacitance value in a small occupied area. As such a capacitance, a MOS capacitor using an insulated gate field effect transistor is generally used.

FIG. 30A shows the cross-sectional structure of the MOS capacitor, and FIG. 30B shows its electrical connection circuit.
FIG. 30C shows an electrically equivalent circuit.

In FIG. 30A, the MOS capacitor is an N formed in a predetermined region on the P-type semiconductor substrate 101.
Type impurity regions 102a and 102b and semiconductor substrate 1
A gate insulating film (capacitor insulating film) 104 formed on the surface of the insulating film 01 and a gate electrode 103 formed on the gate insulating film 104. Impurity regions 102a and 102b provide one electrode lead-out portion of the capacitor (ground potential GND in FIG. 30A, that is, an electrode lead-out portion connected to the ground line). The gate electrode 103 constitutes the other electrode of the capacitor, and is formed of polycrystalline silicon, refractory metal silicide such as molybdenum silicide or tungsten silicide, or a multi-layer structure of polycrystalline silicon and refractory metal.

Gate electrode 103 is connected to output node 27 which receives high voltage Vpp. The power supply line and the ground line between the gate electrode 103 and the output node 27 are formed of a low resistance metal such as aluminum. Gate insulating film 104
Is formed by using an insulating film such as silicon dioxide (SiO ₂ ). The source and drain electrodes 108 are formed of a low resistance conductor such as aluminum, and are included in the impurity region 102.
Electrical contact is made with a and 102b, and ground potential GND from the ground line is applied to impurity regions 102a and 102b.

An interlayer insulating film 109 is provided to electrically insulate the electrodes 103 and 108 from each other.

When a voltage higher than the threshold voltage is applied to the gate electrode 103, the inversion layer (N-type inversion layer) 101 is formed on the surface of the semiconductor substrate 101. This inversion layer 10
1 forms one electrode of the capacitor. That is, FIG.
In the MOS capacitor shown in (A), one electrode of the capacitance is the inversion layer 101 and the other electrode is the gate electrode 103.
Is. The ground potential GND is applied to the inversion layer 101 via the impurity region 102. Ground potential GN of one electrode
D connection is realized and the other electrode (gate electrode 10
When a high voltage Vpp is applied to 3), this capacitance becomes
It functions as the stabilizing capacity shown in.

The MOS capacitor has the same structure as the MOS transistor (insulated gate type field effect transistor) used inside the memory chip, and the source electrode and the drain electrode of the MOS transistor are commonly connected to the ground potential GND. Can be regarded as a MOS transistor (see FIGS. 30B and 30C).

The capacitance of the MOS structure as shown in FIG. 30A is used because the dielectric (capacitor insulating film) can be made thin on the memory chip with the capacitance using this structure. This is because it can be formed by utilizing the vacant area of the circuit in the vicinity thereof, and a capacity with good space efficiency can be formed.

[0061]

Generally, in a dynamic random access memory, the potential level of the selected word line is set to a potential sufficient to increase the speed of reading data from the memory cell and to the memory cell. For the reason of writing the level data at high speed, a potential level about 1.5 times the internal operating power supply voltage (more strictly, the potential level corresponding to the high level side data written in the memory cell) is required. To be done.

In the FET (insulated gate type field effect transistor) used in the dynamic random access memory, the thickness of the gate insulating film is determined in consideration of performance such as operation speed and stability. . For example, if the operating power supply voltage is 3.3V, FET
The gate insulating film is set to about 100Å.

In this case, the electric field E applied to the gate insulating film is E = V / t = 3.3 · 1.5 / 100 = 5 · 10 ⁶ [V / cm], and the withstand voltage is 10 · 10 ^6. An electric field that is sufficiently lower than V / cm is applied to the gate insulating film, which ensures the reliability of the gate insulating film.

However, dynamic random
When the operating life test of the access memory was conducted, 5
It has been found that the life of a dynamic random access memory having an operating power supply voltage of 3.3 V is shorter than the life of a dynamic random access memory having an operating power supply voltage of V. Here, in the operation life test, the ambient temperature is 125 ° C. and the internal operation power supply voltage V is 3.3 V for the dynamic random access memory of 3.3 V.
Operate 1000 hours with cc set to 5V (Vpp = 5 × 1.5 = 7.5 (V)), operate at ambient temperature of 125 ° C. for dynamic random access memory with 5V as operating power supply voltage Vcc Power supply voltage Vcc is 7.5V
An operating life test was performed using (Vpp = 7.5 × 1.5 = 11.25 (V)).

When the operating condition was further severed and an accelerated operating life test was performed so that the operating life test of 1000 hours corresponded to the operating life test of 1500 hours, the operating life test of the normal standard was 3, 3 V and 5 Vcc of 0.0V
There was almost no difference in the defective rate of the DRAM of the above, but in the accelerated life operation test, the defective rate of the dynamic random access memory of 3.3V operation is higher than that of the dynamic random access memory of 5V operation. Could be higher.

In pursuit of this cause, the capacitance used for high voltage stability is subject to dielectric breakdown, and a short circuit occurs between the high voltage output node and the ground potential, making it impossible to stably generate a high voltage. Was found to be one of the main causes. One of the causes of this dielectric breakdown is that an electric field larger than the allowable value may be applied due to variations in the film thickness of the gate insulating film during manufacturing. The standard value of film thickness variation is 5Å
This is because even if the thickness is smaller, the influence becomes larger.

In the dynamic random access memory, even if the same operating power supply voltage is 3.3 V, the size of the FET is reduced and the gate is correspondingly reduced due to high density and high integration and cost reduction. The thickness of the insulating film is further reduced to 90Å and 80Å. Therefore, it is necessary to sufficiently improve the insulation characteristic of the capacitor for stabilizing the high voltage.

Further, even if instantaneous dielectric breakdown does not occur due to application of a high electric field, fatigue breakdown of the insulating film due to long-term electric field application (dielectric breakdown TDDB over time).
It is known that, because of this, even if an electric field that does not cause dielectric breakdown is applied, dielectric breakdown may occur, and the reliability of the insulation characteristics of the capacitor for high voltage stabilization is improved. It is necessary to secure it.

The problem of the insulation characteristic of the stabilizing capacitor is not limited to the semiconductor memory device, but generally occurs in an integrated circuit device that internally generates and uses a high voltage.

Therefore, an object of the present invention is to provide a semiconductor memory device having a stabilizing capacitor capable of stably generating a high voltage for driving a word line.

Another object of the present invention is to improve the reliability of the capacitance for stabilizing the high voltage for driving the word line.

Still another object of the present invention is to provide a semiconductor integrated circuit device having a high voltage generating circuit which stably generates a high voltage inside a chip.

[0073]

In summary, the semiconductor memory device according to the present invention uses a series body of a plurality of capacitive elements as a capacitor for stabilizing a high voltage for driving a word line, or The FET used in the input / output circuit directly connected to the external terminal has a sufficiently high dielectric strength voltage to prevent electrostatic breakdown.

That is, according to the first aspect of the invention, the boosting means for boosting the internal operating power supply voltage to generate a high voltage, and the word line driving for transmitting the high voltage generated by the boosting means to the selected word line. Means and a plurality of capacitive elements connected in series between the high voltage output node of the boosting means and the second power supply voltage source.

According to a second aspect of the present invention, as the capacitive element according to the first aspect, the same gate insulating film thickness as the FET included in the memory cell or the FET of the component of the circuit portion for directly transmitting a signal to the memory cell array is used. FE with
Use T.

The invention according to claim 3 includes a step-down means for stepping down an external power supply voltage to generate an internal operating power supply voltage, and each of the capacitive elements in claim 1 is applied with this stepped down internal power supply voltage. An FET having the same gate insulating film thickness as the FET that is a constituent element of the circuit is used.

According to a fourth aspect of the present invention, there is provided boosting means for boosting the internal operating power supply voltage to generate a high voltage, and word line driving means for transmitting the high voltage generated by the boosting means onto a selected word line. , An input or output circuit having an FET as a constituent element, which is directly connected to an external terminal and directly inputs or outputs a signal to the outside of the apparatus, and a gate insulating film substantially the same as the FET of the constituent element of the input or output circuit It includes a capacitive element formed by using a FET having a film thickness and connected between the high voltage output node of the boosting means and the second power supply voltage source.

According to a fifth aspect of the present invention, the high voltage generating means included in the semiconductor integrated circuit device includes a boosting capacitive element having one electrode connected to a clock signal input node to which a clock signal is input, and a power supply. A first diode element connected between a power supply potential node to which a potential is applied and the other electrode of the boosting capacitive element, and a first diode element connected between the other electrode of the boosting capacitive element and the output node. The second diode element and a plurality of stabilizing capacitive elements connected in series between the output node and the ground potential node. A potential higher than the power supply potential applied to the power supply potential node is output to the output node.

[0079]

The series body of capacitive elements in the invention according to claim 1 relaxes the electric field applied to each of the capacitive elements by the capacitance division, thereby improving the reliability of the capacitive elements when a high voltage is applied. It is possible to realize a guaranteed and highly reliable high voltage stabilizing capacitor.

According to the second aspect of the invention, the FET used for high voltage stabilization can be formed in the same manufacturing process as the memory cell transistor or the transistor of the memory cell array drive section, and an extra manufacturing process is added. In this way, a highly reliable high voltage stabilizing capacitor having a sufficiently controlled gate insulating film thickness and excellent space efficiency can be obtained.

According to the third aspect of the invention, the capacitive element for stabilizing the high voltage can be manufactured by the same manufacturing process as the FET of the circuit to which the internal step-down voltage is applied. It is possible to realize a space-efficient and highly reliable high-voltage stabilizing capacitor with well-controlled thickness without adding a complicated manufacturing process.

In the invention according to claim 4, the thickness of the gate insulating film of the FET of the circuit directly connected to the external terminal is made sufficiently thick to prevent electrostatic breakdown. Therefore, one FET is formed.
Can be used to realize a highly reliable high voltage stabilizing capacitor.

In the invention according to claim 5, since a plurality of stabilizing capacitive elements are connected in series, the electric field applied to each stabilizing capacitive element is relaxed. Therefore, the reliability of the stabilizing capacitive element is ensured even when a high voltage is generated, and the high voltage can be stably generated inside the semiconductor integrated circuit device.

[0084]

1 is a diagram showing the structure of a main portion of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, word line drive signal generation circuit HSG, (unit) X decoder AD
The Xi and word line driver WDi have the same configuration as that shown in FIG. 27 and perform the same operation, and therefore, corresponding parts are designated by the same reference numerals, and detailed description thereof will be omitted. The word line drive signal generation circuit HSG and the word line driver WDi (word line driver circuit WD) constitute the word line drive means 900 for driving the selected word line. Further, in FIG. 1, one word line 3, one bit line 2 and memory cell 1 are shown as in the configuration of FIG. The memory cell 1 includes one selection transistor 5 and
And a memory capacitor 6.

High voltage generating circuit HVG for generating a boosted word line drive signal includes a boosting unit 400 for generating high voltage Vpp from internal operating power supply voltage Vcc in response to repetitive signal φc, and this boosting unit 400. A stabilizing capacitor 330 for stabilizing the high voltage generated by 400 is included. The stabilizing capacitor 330 is connected to the output node 27 of the boosting unit 400 and the second node.
(Two in FIG. 1) capacitive elements 33a and 3 connected in series with the power supply voltage source (ground potential)
3b is included. The booster unit 400 includes a booster capacitor and two diode-connected n-FETs in the high voltage generation circuit HVG shown in FIG. That is, the booster 400
Generates a high voltage Vpp by a charge pump operation in response to repetitive signal φc.

In the stabilizing capacitance 330, the capacitive element 3 is
Voltages V33a and V3 applied to 3a and 33b
3b is V33a = C33b.Vpp / (C33a + C33), where Vpp is the high voltage generated at the node 27.
b), V33b = C33a · Vpp / (C33a + C3
3b), given in. Where C33a and C33b
Indicates the capacitance value of the capacitive elements 33a and 33b. Therefore, if the capacitance values C33a and C33b are equal,
The voltage applied to the capacitive elements 33a and 33b is 1/2 times (= Vpp / 2) as compared with the case of the stabilizing capacitance configured by one capacitance shown in FIG. 27, and the film thickness of the capacitor insulating film. Even if the thickness is thin, the voltage applied to each capacitive element is greatly reduced, so the insulation characteristics (dielectric breakdown voltage and aging dielectric breakdown characteristics) of this stabilizing capacitance 330 are greatly improved, and highly stable stabilization is achieved. Capacitance can be realized, and high voltage Vpp can be stably generated.

The capacitance value of the stabilizing capacitor 330 is the same as the word line 3
Is set to a value sufficiently larger than the capacitance value of the parasitic capacitance 7 of. However, in consideration of the area occupied by stabilizing capacitor 330 and the charging speed (that is, charging time) of output node 27 when high voltage Vpp is generated, stabilizing capacitor 330 is preferable.
The capacitance value of is set to about 30 times the parasitic capacitance 7. For example, in a 4M dynamic random access memory, the capacitance value of the parasitic capacitance 7 is usually 10p.
It is about F, and the capacitance value C330 of the stabilizing capacitor 330 is set to about 300 pF.

Since the capacitive elements 33a and 33b are connected in series, the capacitance value C3 of each of the capacitive elements 33a and 33b is larger than the capacitance value C330 of the stabilizing capacitance 330.
3a and C33b need to be large. Therefore, as the capacitive elements 33a and 33b, it is necessary to use an element structure that is as space-efficient as possible.

FIG. 2 is a diagram showing a specific structure of the stabilizing capacitor shown in FIG. The stabilizing capacity shown in FIG. 2 is n-FE.
A MOS capacitor structure configured using T is provided.
The capacitive element 33a and the capacitive element 33b are separated by an element isolation film (field oxide film) 220 formed on the surface of the p-type semiconductor substrate 200.

The capacitive element 33a is composed of the p-type semiconductor substrate 20.
N-type impurity region 202 formed in a predetermined region on the surface of 0
a and 202b and impurity regions 202a and 202
the gate insulating film 20 on the surface of the semiconductor substrate 200 between
4 and a gate electrode 203 formed via. The electrode extraction layer 208 is formed in the impurity regions 202a and 202b.
And the electrode extraction layer 231a is provided on the gate electrode 203.
Is provided.

Similar to capacitive element 33a, capacitive element 33b includes n-type impurity regions 212a and 212b, and gate electrode 213 formed on the surface of semiconductor substrate 200 via gate insulating film 214. Impurity region 212a
And 212b are provided with electrode extraction layers 218. Further, for the gate electrode 213, the electrode extraction layer 23
1b is provided.

Impurity regions 202a and 202b of capacitive element 33a have electrode extraction layer 208 and electrode extraction layer 2 respectively.
It is connected to the gate electrode 213 of the capacitive element 33b via 31b. The gate electrode 203 of the capacitive element 33a is
It is connected to receive the high voltage Vpp through the electrode extraction layer 231a. Impurity region 212a of the capacitive element 33b
And 212b are connected to the ground potential G via the electrode extraction layer 218.
Connected to receive ND.

As shown in FIG. 2, if the stabilizing capacitor is formed by using the insulated gate field effect transistor, the stabilizing capacitor is formed in the same manufacturing process as the insulated gate field effect transistor used in this semiconductor memory device. It is possible to manufacture, and it is possible to obtain a space-efficient and excellent film thickness control capacitor without adding an extra manufacturing step. In this case, even if there is a variation in the gate insulating film in the manufacturing process, each capacitive element 33 is divided by the capacitance division.
Since the voltage applied to each of a and 33b can be set to a sufficiently low voltage, it is possible to realize a stabilizing capacitance having excellent insulation characteristics.

FIG. 3 is a diagram showing a connection configuration of the stabilizing capacitors shown in FIG. 2 and an electrically equivalent circuit thereof. In FIG. 3A, the gate electrode 203 of the capacitive element 33a
Are connected to the high voltage Vpp, the impurity regions of the capacitive element 33a are coupled together and connected to the gate electrode 213 of the capacitive element 33b, and the impurity regions of the capacitive element 33b are both grounded via the electrode extraction layer 218. Connected to.
This is electrically equivalent to the structure in which the capacitance shown in FIG. 3B is connected in series between the high voltage Vpp and the ground potential.

In the structure shown in FIG. 2, an n-FET is used to realize a MOS capacitor. Alternatively, a p-FET can be used.

FIG. 4 is a diagram showing another configuration example of the stabilizing capacitor shown in FIG. In FIG. 4A, the stabilizing capacitance includes capacitive elements 33c and 33d configured by using p-FETs connected in series between the high voltage Vpp and the ground potential. The capacitive element 33 has its impurity region connected to the high voltage Vpp, and its gate electrode connected to the impurity region of the capacitive element 33d. The gate electrode of the capacitive element 33d is connected to the ground potential. Even with this configuration, the p-FET is used in the semiconductor memory device (for example, an inverter circuit having a CMOS configuration), and the capacitive element 33c can be easily manufactured in the same manufacturing process as the p-FET manufacturing process in the semiconductor memory device. And 33d can be manufactured.

In FIG. 4B, the stabilizing capacity is n
-A capacitive element 33a configured by using an FET, p-
It includes a capacitive element 33d configured using an FET. The gate electrode of capacitive element 33a is connected to high voltage Vpp, and its impurity region is connected to the impurity region of capacitive element 33d. The gate electrode of the capacitive element 3d is connected to the ground potential.

The stabilizing capacitance shown in FIG. 4C is p-FE.
A capacitive element 33c formed by using T and an n-FET
The capacitive element 33b configured by using The impurity region of the capacitive element 33c is connected to the high voltage Vpp, and its gate electrode is connected to the gate electrode of the capacitive element 33b. The impurity region of capacitive element 33b is connected to the ground potential.

The equivalent circuits of the stabilizing capacitors shown in FIGS. 4 (a), 4 (b) and 4 (c) are the same as those shown in FIG. 3 (b), and the capacitors connected in series are also used in these cases. Can be used to realize a stabilizing capacitance, the voltage applied to each of the capacitive elements 33a to 33d can be relaxed, and a stabilizing capacitance having excellent insulation characteristics can be realized. In the case of using both p-FET and n-FET, it can be manufactured in the same manufacturing process as the CMOS circuit portion of this semiconductor memory device, and a stable capacitive element can be obtained without adding an additional manufacturing process. Can be realized.

FE used for capacitive element for high voltage stabilization
As mentioned above, T is the FE used in the semiconductor memory device.
The same structure as T (the same film thickness of the gate insulating film) is used. That is, the capacitive elements 33a and 33b (33c and 33d) and the FET in the semiconductor memory device are manufactured in the same manufacturing process. The manufacturing process will be briefly described below.

Now, as shown in FIG. 5, the semiconductor chip 200
Consider a case where FETs are manufactured in the regions I and II.
Region I is a region where a capacitive element for high voltage stabilization is formed, and region II is an FET in another circuit portion.
Is a region where is formed. Now, consider the case of forming an n-FET in each of the regions I and II.

First, as shown in FIGS. 6A and 6B, a thin thermal oxide film (pad oxide film) 502 is grown on the surface of a p-type semiconductor substrate 500, and then CVD (chemical vapor deposition) is performed. Method) to form a silicon nitride film 504
A layer insulating film is formed. Here, FIG. 6A shows the FET formation process in the region I in FIG.
5B shows the FET formation process in the region II shown in FIG. In the following description, (a) in each figure
Shows a process of forming a capacitive element for stabilizing capacitance, and (b) shows a process of forming an FET in another circuit portion.

As shown in FIGS. 7A and 7B, after forming a resist film, the resist film is patterned using photolithography to form a resist pattern 506.
Then, the resist pattern 506 is used as a mask to etch away the portion of the silicon nitride film 504 to be the element isolation region.

As shown in FIG. 8, in order to set the threshold voltage of the parasitic MOSFET to a predetermined value or higher, a p-type layer made of, for example, boron is formed on the surface of the semiconductor substrate 500 in the element isolation region using this resist pattern 506 as a mask. Impurities are ion-implanted to form an ion-implanted region 508 for channel stop. Here, the parasitic MOSFET M is composed of a wiring material, a field oxide film, and a semiconductor substrate.
2 shows a parasitic FET due to the OS structure. This parasitic MOS
It is necessary to sufficiently raise the critical voltage at which the FET becomes conductive, that is, the threshold voltage, to achieve insulation between the elements. Therefore, ion implantation for channel stop is performed.

Next, as shown in FIG. 9, after removing the resist pattern 506, thermal oxidation is performed using the silicon nitride film 504 as a mask to selectively form a thick silicon dioxide film (field oxide film) in the element isolation region. Grow 510. Such a field oxidation method is used for LOCOS.
(Local oxidation of silicon) method. At this time, the field oxide film 510 also grows under the silicon nitride film 504, and part of the silicon nitride film 504 is lifted (bird's beak). During the growth of field oxide film 510, channel stop impurity implantation region 504 is diffused and activated, and channel stop region 508a is formed under field oxide film 510. Element isolation is completed by this series of steps.

In FIG. 10, the unnecessary silicon nitride film 504 and pad oxide film 502 are removed by etching to expose the surface of the semiconductor substrate 500.

In FIG. 11, the exposed portion of the substrate surface is thermally oxidized to form a thin gate oxide film 512.
Grow. Generally, this gate oxide film 512 is
Since it is a main factor that determines the threshold voltage of the OSFET, sufficient consideration is given to the control of the film thickness and the film quality.

In FIG. 12, in order to set the threshold voltage of the MOSFET to a predetermined value, for example p, which is boron, is used.
Ion implantation of type impurities is performed. The ion implantation shown in FIG. 12 is intended to control the threshold voltage of the FET, and when a transistor having a different threshold voltage is produced, the resist is used as a mask and only the necessary FET is p-type or N-type impurity ion implantation is performed.

In FIG. 13, n-type polycrystalline silicon is deposited on the entire surface by, eg, CVD method. Then, using the resist pattern 516 as a mask, this polycrystalline silicon is etched to form a gate electrode 514. Here, instead of the polycrystalline silicon layer 514 as the material of the gate electrode, a refractory silicide layer such as molybdenum silicide or tungsten silicide may be used.

In FIG. 14, a resist pattern 514 is formed.
After the removal, the gate electrode layer 514 and the field oxide film 510 are used as a mask to ion-implant a high-concentration n-type impurity (phosphorus, arsenic, or the like) in a self-aligned manner, followed by heat treatment to electrically implant the implanted ions. Activation is performed to form a source region and a drain region 516. Through this process, the basic structure of the MOSFET is formed.

Here, the polysilicon layer formed on field oxide film 510 is another wiring layer, which is a wiring layer formed in the same process as gate electrode layer 514. An example of such a wiring layer is a word line in the memory cell array portion.

In FIG. 15, a PSG film (phosphorus glass film) 518 is deposited by, eg, CVD method to form an interlayer insulating film. After the deposition by the CVD method, the PSG film 518 is reflowed to flatten the surface of the PSG film.

In FIG. 16, this interlayer insulating film (PSG
The film 518 is selectively etched using the resist pattern as a mask to expose the surfaces of the source and drain regions 516 (formation of contact holes). After that, a low resistance conductor such as aluminum is formed over the entire exposed surface of the semiconductor substrate by using, for example, PVD (Physical Vapor Deposition) or CVD, followed by etching using a resist pattern (not shown). Then, predetermined electrode wiring layers 520a and 520b are formed. Thereafter, heat treatment (sintering) is performed to form a good ohmic contact between the electrode wiring layers 520a and 520b and the source / drain region 516. In the structure shown in FIG. 16, in the capacitive element formation region shown in FIG. 16A, the electrode wiring layer 520b of the FET is patterned so as to extend also in the adjacent element.

That is, as shown in FIG. 17, in order to function as a capacitive element included in this stabilizing capacitance, the electrode wiring layer 520b serves as the gate electrode 51 of the capacitive element 33b.
4b (the contact hole for the gate electrode 514b is formed simultaneously with the formation of the contact holes for the source and drain regions in the step shown in FIG. 16). Further, the electrode wiring layer 52 of the capacitive element 33b is formed.
0c is wired so as to be connected to the ground potential in a later process. In addition, the gate electrode layer 514 of the capacitive element 33a is
a is wired so as to receive the high voltage Vpp. By this wiring step, a capacitive element having the same structure as the FET in the other circuit portion shown in FIG. 16B can be manufactured without requiring any additional manufacturing process.

In FIG. 18, the uppermost electrode wiring layer 52 is formed.
0a, 520b, and 520c are made of aluminum, for example. In order to prevent the corrosion and contamination of the electrode wiring layer, as shown in FIG. 18, a protective film 522 made of a PSG film or a silicon nitride film formed by a plasma CVD method is formed, and an external terminal and an external terminal are formed using a resist pattern (not shown) as a mask. Forming a via hole 524 for connection with a pad portion for making a connection with another wiring layer (in this case, the protective film is an interlayer insulating film) in the multilayer wiring structure, and thereafter, the resist which is no longer needed Remove the membrane.

With the above structure, the stabilizing capacitive element and the FET in the other circuit portion can be formed in the same manufacturing process, and the stabilizing capacitive element has the same structure as the FET used in the semiconductor memory device. You can

In the above embodiment, the capacitive element is formed using the n-FET in the semiconductor memory device. This n-FET is shown to use the n-FET in a general circuit in the above-mentioned configuration. As shown in FIG. 19A, this high voltage stabilizing capacitive element may have the same structure as the select transistor 5 of the memory cell 1.

In FIG. 19A, in the select transistor 5 of the memory cell 1, the impurity region 551c serving as the source region, the impurity region 551d serving as the drain region, and the impurity region 55 are formed on the surface of the semiconductor substrate 550.
Gate electrode layer 55 formed on the surface of semiconductor substrate 550 between 1c and 551d via gate insulating film 557
4c, an electrode layer 553 formed in the impurity region 551d and forming one electrode (storage node) of the memory cell capacitor, and an electrode serving as the other electrode (cell plate) of the memory cell capacitor formed on this electrode layer 553. Includes layer 555. Usually, the gate electrode layer is formed of the first polycrystalline silicon layer, the electrode layer 553 is formed of the second polycrystalline silicon layer, and the electrode layer 555 is formed of the third polycrystalline silicon layer. The electrode wiring layer 556c (bit line) formed for the impurity region 551c serving as the source region is formed using a low resistance layer such as aluminum.

Stabilizing capacitance 330 includes impurity regions 551a and 551b formed on semiconductor substrate 550, and gate electrodes 554a and 551b formed on impurity regions 551 and gate electrode 55 formed on impurity regions 551b.
4b is included. Impurity regions 551a and 551b
Is the impurity region 55 of the selection transistor 5 of the memory cell.
It is formed by the same manufacturing process as 1c and 551d.
The gate electrode layers 554a and 554b are formed in the same process as the gate electrode 554c of the selection transistor 5. In the stabilizing capacitor 330, the impurity region 551b
Are connected so as to receive the ground potential via the electrode wiring layer 556b, and the electrode wiring layer 556a is connected to the gate electrode 554b.
Connected to. Gate electrode 554a is connected to receive high voltage Vpp. In this case, the electrode wiring layer 556
b and 556a are formed in the same process as the electrode wiring layer 556c. The memory cell structure is shown in FIG.
Instead of the stacked capacitor structure shown in (A), a trench capacitor structure may be used, or another capacitor structure may be provided.

FIG. 19B shows the structure of the stabilizing capacitor formed by the CMOS process. In FIG. 19B, the stabilizing capacitor 330 includes capacitive elements 33a and 33d. The capacitive element 33 a includes a p-type well 580 formed in a predetermined region of the n-type semiconductor substrate 570, an n-type impurity region 582 formed on the surface of the p-type well 580, and a well region between the impurity regions 582. It includes a gate electrode 586 formed on the surface through a gate insulating film 584.

The capacitive element 33d is composed of the n-type semiconductor substrate 57.
And a gate insulating film 574 on the surface of the substrate between the impurity regions 572.
And a gate electrode 576 formed through. Impurity region 572 is connected to impurity region 582. Gate electrode 586 is connected to receive high voltage Vpp, and gate electrode 576 is connected to receive ground potential GND. The capacitive element 33a is formed using an n-FET, and the capacitive element 33d is formed using a p-FET. The stabilizing capacitor can be formed in the same manufacturing process as the CMOS circuit portion in the semiconductor memory device.

FIG. 20 shows a structure of a semiconductor memory device according to another embodiment of the present invention. In FIG. 20,
Repetitive signal φ from on-chip ring oscillator 630
c is generated and applied to high voltage generation circuit HVG (node 28). The high voltage generation circuit HVG includes a booster unit 400.
And a stabilizing capacitance 330. This structure is similar to that shown in FIG.

The word line driver WDi is used for each word line 3
(WLi) provided, X decoder ADX
i is also provided corresponding to the word line driver WDi.

Word line driver WDi includes n-FET 614 for passing the output of X decoder ADXi applied to node 9 and node 10 receiving high voltage Vpp.
P-FET 611 provided between the node and the node 613a
a, a p-FET 611b provided between the node 10 and the node 613b, and an n-FET 6 discharging the node 613b to the ground potential in response to the potential of the node 613a.
Including 12. The gates and drains of the p-FETs 611a and 611b are cross-coupled.

The memory cell 1 includes a selection transistor 5 and a memory capacitor 6, and responds to a signal potential on the word line 3 through the selection transistor 5 and the memory capacitor 6 is formed.
Are connected to the bit line 2 (BLi).

The structure shown in FIG. 20 does not include the circuit for generating word line drive signal φx shown in FIG. A high voltage Vpp is constantly applied to the word line driver WDi.
Is given. Therefore, the delay in the circuit generating the word line drive signal φX can be eliminated, the word line can be driven at high speed, and the memory cell access speed is improved. In the word line driver WDi, p−
Set the size (or gate width) of the FET 611b to n-FE
It must be larger than T612. This is because it is necessary to charge the word line 3 at high speed.

The n-FET 614 has its gate connected to the node 8
An internal operating power supply voltage Vcc is received via. n-FET
614 has a function of preventing the high voltage Vpp from being applied to the node 9. The operation of word line driver WDi shown in FIG. 20 will now be described with reference to the operation waveform diagram of FIG.

When the X decoder ADXi is in the selected state, its output falls from "H" to "L". Time t0
, The row select operation is not executed, and the potential of word 9 is at the "H" level of the internal operation power supply voltage Vcc level. In this state, high voltage Vpp is constantly applied to node 10. Node 613
Since a signal of “H” is given to the a through the n-FET 614, the n-FET 612 is in the ON state and the node 6
The potential of 13b is discharged to the ground potential level. In response to this, the p-FET 611a is turned on, and the node 6
The potential of 13a begins to rise, and the p-FET 611b is completely turned off. Therefore, finally the node 613
The potential of a becomes the high voltage Vpp level.

At time t1, the row selection operation is executed, and the potential of node 9 falls to "L".
The potential of 3a is discharged through n-FET 614 and node 9 (via X decoder ADXi), and drops to the ground potential level. As a result, the n-FET 612 is turned off, the p-FET 611b is turned on, and p
-The FET 611a is turned on. As a result, the node 613b rises to the high voltage Vpp level via the p-FET, and the word line drive signal φxi at the high voltage Vpp level is transmitted onto the word line 3. In the structure shown in FIG. 20, when the X decoder ADXi is selected, the potential of the word line 3 (word line drive signal φxi) rises and the selection transistor 5 of the memory cell 1 is turned on. Speed up.

When the memory cycle is completed at time t2, the potential of X decoder ADXi changes to the internal operating power supply voltage V.
The cc level rises to the "H" level. As a result, the potential level of the node 613a becomes V via the n-FET 614.
It is charged to the level of cc-VTN. Node 613
When the potential level of a reaches Vcc-VTN, n-F
The ET 612 is turned on, the node 613b is discharged to the ground potential level, the p-FET 611a is turned on, and the potential level of the node 613a rises to the high voltage Vpp. As a result, the p-FET 611b is completely turned off, and the potential level of the node 613b is n-FET 61b.
2 is completely discharged to the ground potential level.

Even in the structure of the word line drive system as shown in FIG. 20, stabilizing capacitor 330 for stabilizing high voltage Vpp includes capacitive elements 33a and 33b connected in series, The high voltage Vpp can be stably generated, and the selected word line can be charged to the high voltage level at high speed.

Next, the internal operating power supply voltage Vcc will be described. The external power supply voltage Vd may be used as it is as the internal operating power supply voltage Vcc (that is, Vd = Vc).
c). For example, in a system using a battery as a power source such as a portable personal computer, it is necessary to reduce the power consumption of this system constituent device as much as possible. This is to extend the battery life. To reduce the power consumption, the operating power supply voltage of the dynamic random access memory is lowered. Since the power consumption is proportional to the square of the voltage, the power consumption can be sufficiently reduced by the low operating power supply voltage. This lower power supply voltage can also reduce the amount of heat generated due to power consumption, and can accommodate the dynamic random access memory in an inexpensive plastic package.

When the external power supply voltage is lowered and is used as it is as the internal operating power supply voltage of the dynamic random access memory, the memory cell array section of the dynamic random access memory and the peripheral circuits are The FETs have the same film thickness (or have the same structure) at least for the gate insulating film.
Therefore, as the capacitor for stabilizing the high voltage for driving the word line in the above-described embodiment, the FET having the same structure (the same gate insulating film thickness) as the FET of the memory cell array portion or the peripheral circuit portion is used.

On the other hand, the dynamic random access circuit for generating the internal operating power supply voltage Vcc by stepping down the external power supply voltage Vd by using the on-chip internal voltage down converting circuit.
There is also a memory (Vd> Vcc). The miniaturization of logic LSIs such as the microprocessor unit that determines the system power supply voltage progresses slower than that of dynamic random access memory, and the system power supply voltage is adjusted according to the miniaturization of dynamic random access memory. This is to deal with the case where it cannot be lowered. In this case, in order to secure the reliability of the dynamic random access memory (reliability of the gate insulating film of the FET, etc.), the internal step-down circuit is used to step down the external power supply voltage to generate the internal operating power supply voltage Vcc. .

The structure of the dynamic random access memory is such that (1) the internally stepped down power supply voltage is applied to both the peripheral circuit and the memory cell array section according to the location where the internally stepped down power supply voltage is applied, and (2) The external power supply voltage is applied to the peripheral circuit section, and the internally stepped down power supply voltage is applied only to the memory cell array section.

In the first structure, the operating power supply voltage of the entire dynamic random access memory is lowered. This is a dynamic random access
This is done to bring advantages of high-speed operation in addition to the advantages of memory reliability and power consumption. The operating speed of the peripheral circuit, which is proportional to the driving capability of the FET, greatly depends on its operating power supply voltage, especially the gate voltage. On the other hand, a repeating pattern circuit in which the same pattern is repeated, such as a memory cell array and a sense amplifier, has a large load capacitance.
Therefore, the operating speed is RC given by the load capacitance and the resistance.
It is determined by the time constant, and the voltage dependence is not as great as that of the peripheral circuit. Generally, in the dynamic random access memory, a large margin is provided for the operation timing of the peripheral circuit so that the operation of the peripheral circuit and the operation of the repetitive pattern circuit do not cause a mismatch. By lowering the power supply voltage of the peripheral circuit section, the margin of this operation timing can be reduced, and as a result, the access time can be shortened.

In the first structure, the gate insulating film thicknesses of the FETs in the peripheral circuit section and the memory cell array section are the same (the sizes are different). Therefore, as the capacitor for stabilizing the high voltage for driving the word line, the FET having the same structure (same gate insulating film thickness) as the FET of the peripheral circuit and the memory cell array portion can be used again.

In the second structure, as described above, the internally stepped down power supply voltage is applied to this portion in order to ensure the reliability of the word line having the highest voltage and the circuit for directly driving this word line. Further, the power consumption is greatly suppressed because the power supply voltage of the memory cell array unit is lowered.
In this case, the FET of the peripheral circuit to which the external power supply voltage is applied
Is thicker than that of the FET in the memory cell array portion.

FIG. 22 is a diagram schematically showing an overall structure of a dynamic random access memory having an internal voltage down converting circuit. In FIG. 22, the dynamic random access memory 700 has a memory cell array 7 in which memory cells are arranged in a matrix of rows and columns.
02, a step-down circuit 704 for stepping down the external power supply voltage Vd to the internal power supply voltage Vcc of a predetermined voltage level, and a step-down circuit 7
Array drive circuit 706 for driving memory cell array 702 with internal power supply voltage Vcc from 04 as an operating power supply voltage
A peripheral circuit 708 that operates using the external operation power supply voltage Vd as the operation power supply voltage; a peripheral control circuit 710 that operates using the external power supply voltage Vd as the operation power supply voltage and controls the operation of the peripheral circuit 708; An input / output circuit 712 for inputting / outputting signals to / from the outside of the device as an operating power supply voltage
including. The input / output circuit 712 also operates under the control of the peripheral control circuit 710.

Array drive circuit 706 includes a word line drive circuit, a sense amplifier circuit, a sense amplifier drive circuit, and a precharge / equalize circuit. That is, the array drive circuit 706 is used in the memory cell array 702.
It includes a circuit portion for directly transmitting a signal to.

The peripheral circuit 708 is an address decoder (X
And Y). Peripheral control circuit 710 is for controlling peripheral circuit 708 and for controlling the operation of input / output circuit 712, and responds to externally applied control signals / RAS, / CAS and / WE to perform internal control. It is a circuit that generates a signal. This peripheral control circuit 710
May also be configured to generate signals that define the operation timing of array drive circuit 706.

Input / output circuit 712 includes not only a data input / output circuit but also an address buffer. In order to input and output signals to and from the outside of the device, the external power supply voltage Vd is used as the operating power supply voltage. This is to take an interface with the outside. That is, the input / output circuit 712 includes a buffer circuit. Peripheral circuit 708 may therefore include a write circuit that receives the output of input / output circuit (buffer circuit) 712 to generate internal write data, a preamplifier circuit that amplifies data in the memory cell array, and the like.

In the configuration shown in FIG. 22, the film thickness of the FETs constituting the array drive circuit 706 and the memory cell array 702 is reduced, and the step-down circuit 704 and the peripheral circuit 7 are formed.
08, input / output circuit 712 and peripheral control circuit 710 F
The thickness of the gate insulating film of ET is increased.

When the FET is used as the capacitor, it is necessary to use the FET having the thinnest gate insulating film in order to reduce the occupied area. Therefore, the capacitive element included in the capacitance for stabilizing the high voltage Vpp for driving the word line has the same structure (same gate insulating film thickness) as the FETs included in the memory cell array 702 and the array driving circuit 706. FET is used. Even if the thickness of the gate insulating film is reduced, the high voltage Vpp is capacitively divided and applied to each capacitive element, so that the dielectric strength characteristics are sufficiently ensured. As a result, a capacitive element having a small occupied area can be obtained.

In the dynamic random access memory using the internal voltage down converter, the above-mentioned configuration (1)
In both cases (2) and (2), the film thickness of the gate insulating film of the FETs of the internal step-down circuit and the input / output circuit is increased. This is because it operates at the external power supply voltage Vd to interface with the outside. However, even in such an internal step-down circuit and the input / output circuit, the film thickness of the gate insulating film is thinned according to the applied power supply voltage. The FET size is optimized with reference to the thickness of the gate insulating film. This is because as the film thickness of the gate insulating film becomes thinner, the gate length becomes shorter and the gate delay (signal propagation delay) becomes smaller, which leads to higher speed. This is also the case when the external power supply voltage is used as the internal power supply voltage without being stepped down without using the internal voltage down converter.

However, in the case of the input / output circuit, since it is connected to the external terminal (lead terminal), if the gate insulating film is thinned in proportion to the applied operating power supply voltage, there arises a reliability problem. The circumstances during this time will be explained.

FIG. 23 is a diagram showing an example of the configuration of an input / output circuit, and FIG. 23A shows a signal input circuit (input buffer).
23B shows the structure of the signal output circuit (output buffer). The buffer circuits in FIGS. 23A and 23B may be an address buffer, a data input buffer, and a data output buffer.

In FIG. 23A, the signal input circuit 75
0 includes two stages of cascaded inverter circuits 760 and 770. Inverter circuit 760 includes a p-FET 762 and an n-FET 764 connected complementarily between a power supply voltage (which may be an external power supply voltage or an internal power supply voltage) Vcc and a ground potential. p-
The gates of the FET 762 and the n-FET 764 are connected to the internal terminal (lead terminal) 780. Inverter circuit 770 includes a p-FET 772 and an n-FET 774 connected complementarily between the power supply voltage Vcc and the ground potential. The output of the first-stage inverter circuit 760 is applied to the gates of the p-FET 772 and the n-FET 774.
The output of the inverter circuit 770 is given to the internal circuit, and desired signal processing is executed.

F which is a component of the inverter circuit 770
The gate insulating film thickness of ET772 and 774 can be made thin according to the power supply voltage Vcc. However, the first-stage inverter circuit 7 directly connected to the external terminal
In 60, the gate insulating film thickness of the FETs 762 and 764 cannot be thinned according to the power supply voltage Vcc. Generally, the external terminal 780 and the inverter circuit 76
A charge / discharge clamp diode (protection diode) for clamping an abnormally high voltage is provided between the input unit of 0 and the input unit of 0. Such a protection diode is connected to the external terminal 780.
And the power supply voltage supply node and between the external terminal 780 and the ground potential. In such a configuration, when a charged human body or object comes into contact with the external terminal 780, discharge occurs at the external terminal 780, and a large electrostatic field is applied to the FETs 762 and 764 even if a clamp diode is provided. . To protect the FETs 762 and 764 from such an electrostatic field, F
The gate insulating film of ET762 and 764 needs to be relatively thick. Therefore, in the configuration of FIG. 23A, the gate insulating films of the FETs 762 and 764, which are the constituent elements of the inverter circuit 760, are relatively thick, and the gate insulating film of the FETs of the inverter circuit 770 has a thickness equal to the power supply voltage Vcc. Will be thinned accordingly.

This static electricity problem similarly occurs in the signal output circuit as shown in FIG. Here, in FIG. 23B, a signal output circuit (output buffer) 800 includes inverter circuits 820 and 810 connected in cascade. The inverter circuit 820 is a CMOS
And p-FET 822 and n-FET 824.
including. Inverter circuit 810 similarly comprises a CMOS configuration and includes p-FET 812 and n-FET 814. Inverter circuit 820 inverts and amplifies the signal given from the internal circuit. Inverter circuit 810 further amplifies and inverts the output from this inverter circuit 820 and outputs it to external terminal 830. When static electricity is discharged at the external terminal 830, a large electrostatic field is generated in the FE, as in the case of the inverter circuit 760 shown in FIG.
Occurs at T812 and / or 814. Therefore, the film thickness of the gate insulating film of the FETs 812 and 814 is made larger than the film thickness of the gate insulating film of the FETs 822 and 824.

In the above-described embodiment, when the series body of capacitive elements is used as the capacitance for stabilizing the high voltage for driving the word line, the FET having the gate insulating film as thin as possible is used ( To achieve a large capacitance value in a small area). Therefore, the FET of the circuit unit to which the internally stepped down power supply voltage is applied is used (in the case of partial internal step-down) or any FET inside the device is used (in the case of full internal step-down). . Specifically, an FET in a circuit portion that directly transmits a signal to the memory cell array portion or a memory cell array such as a word line drive circuit is used.

However, FIGS. 23A and 23B
When the configuration of the signal input / output circuit as shown in FIG. 4 is used, the high voltage stabilizing capacitance can be formed by using the FET of the circuit portion (first stage of input buffer or last stage of output buffer) connected to the external terminal. .

FIG. 24 is a diagram showing a structure of a main portion of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 24, high voltage generation circuit HVG, signal input circuit (input buffer) 750 and signal output circuit (output buffer) 8
00 configuration is shown. The configurations of the signal input circuit 750 and the signal output circuit 800 are similar to those shown in FIG. In the signal input circuit 750, the inverter circuit 76
The thickness of the gate insulating film of the FETs 762 and 764 of the component 0 is the FET of the inverter circuit 770.
It is thicker than that of 772 and 774.

In the signal output circuit 800, the FETs 812 and 81, which are the constituent elements of the inverter circuit 810, are also included.
The thickness of the gate insulating film of No. 4 is made thicker than the thickness of the gate insulating films of the FETs 822 and 822 which are the constituent elements of the inverter circuit 820. The gate insulating films of the FETs 772, 774, 822, and 824 are thicker than the gate insulating films of the FETs in the circuit portion to which the internally reduced voltage is applied. FETs 762, 764, 812, and 8
The electrostatic breakdown is prevented by making the gate insulating film 14 thick enough.

High voltage generating circuit HVG includes a booster 400 and a stabilizing capacitor 833. The configuration of the booster 400 is similar to that shown in FIG. The stabilizing capacitor 833 includes one capacitive element. The stabilizing capacitor 833 has the same structure (same gate insulating film thickness) as the n-FET 764 of the signal input circuit 750 and / or the n-FET 814 of the signal output circuit 800. In this case, the stabilizing capacity 833
With respect to the n-FET 764 and / or 814, the part shown in FIG. 17 is omitted in the configuration shown in the above manufacturing process, and the stabilizing capacitive element 833 is configured by using one FET. In this case, n-FETs 764 and 81
Since the withstand voltage of No. 4 is sufficiently high, the high voltage Vpp can be stably generated without dielectric breakdown even when the high voltage Vpp is constantly generated. As a manufacturing method, the n-FETs 764 and 814 and the stabilizing capacitor 833 can be manufactured in the same manufacturing process by utilizing the manufacturing processes shown in FIGS.

The stabilizing capacitance 833 is p-
It can be constructed using FETs 762 and / or 812. By constructing the stabilizing capacitor using such one FET, it is possible to realize the stabilizing capacitor with excellent space efficiency.

The signal input circuit may be either a data input circuit or an address buffer, and the signal output circuit may be a data output circuit. Further, there are two as the signal input circuit and the signal output circuit.
It does not have to be composed of cascaded inverter circuits. If the stabilizing capacitance is constructed by using the FET of the circuit portion which is connected to the external terminal and directly inputs or outputs the signal, the same effect as that of the second embodiment can be obtained.

Further, in the above-mentioned first and second embodiments, the capacitance for stabilizing the high voltage for driving the word line in the dynamic random access memory is explained. However, a static random
The same effect can be obtained even with an access memory.

Further, in the above-mentioned embodiments, the structure of the capacitor for stabilizing the high voltage for driving the word line in the semiconductor memory device is described. However,
Generally, the same effect can be obtained with a semiconductor integrated circuit device provided with a high voltage generation circuit that generates a high voltage from a power supply potential inside the device.

[0160]

As described above, according to the present invention, a circuit portion for directly transmitting / receiving a signal to / from a serial body of a capacitive element or an external terminal as a stabilizing capacitance for stabilizing a high voltage for driving a word line. Since the FET is used, it is possible to obtain a highly reliable semiconductor memory device in which the insulation characteristic of the stabilizing capacitance is significantly improved and a high voltage for driving the word line can be stably supplied. According to the invention of claim 1, since the series body of the capacitive elements is used as the stabilizing capacitance, the electric field applied to each of the capacitive elements is relaxed, and a high voltage can be stably generated. It is possible to obtain a semiconductor memory device having a high stabilizing capacity.

According to the second aspect of the present invention, as the capacitive element of the stabilizing capacitance, F having the same gate insulating film thickness as the FET of the memory cell or the memory cell array drive section is used.
Since ET is used, the thickness of the gate insulating film is sufficiently controlled without adding an extra manufacturing process, and a space-efficient and highly reliable capacitor for high-voltage stabilization is obtained, which improves reliability. It is possible to obtain a semiconductor memory device having high efficiency.

According to the third aspect of the invention, the FET having the same gate insulating film thickness as the FET of the circuit portion to which the internal step-down voltage is applied is used as the capacitive element of the stabilizing capacitance. In addition, a highly reliable high-voltage stabilizing capacitor having a well-controlled gate insulating film thickness, space efficiency, and high reliability can be realized, and a highly reliable semiconductor memory device can be obtained.

In the invention according to claim 4, since the stabilizing capacitance is formed by using the FET having the same gate insulating film thickness as the FET of the circuit portion directly connected to the external terminal, the insulating characteristic is excellent. The stabilizing capacitance can be realized by one FET, and a semiconductor memory device having a highly reliable high voltage stabilizing capacitance can be realized.

According to the fifth aspect of the present invention, a plurality of output nodes of the boosting unit for generating a high voltage are provided by utilizing the charge pump function of the boosting capacitive element and the rectifying characteristics of the first and second diode elements. Since the stabilizing capacitive elements are connected in series, the electric field applied to each stabilizing capacitive element can be relaxed, and a semiconductor integrated circuit device having high voltage generating means for stably generating a high voltage is obtained. To be

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of the stabilizing capacitor shown in FIG.

FIG. 3 is a diagram showing a connection configuration of the capacitive element shown in FIG. 2 and an electrically equivalent circuit thereof.

FIG. 4 is a diagram showing another configuration example of the stabilizing capacitor shown in FIG.

5A to 5D are views for explaining a method of manufacturing the capacitive element shown in FIG.

FIG. 6 is a diagram showing a first manufacturing process of the capacitive element shown in FIG. 1.

FIG. 7 is a diagram showing a second manufacturing process following the manufacturing process shown in FIG. 6;

8 is a diagram showing a third manufacturing process that follows the manufacturing process shown in FIG. 7. FIG.

FIG. 9 is a diagram showing a fourth manufacturing process following the manufacturing process shown in FIG. 8;

FIG. 10 is a diagram showing a fifth manufacturing process that follows the manufacturing process shown in FIG. 9.

FIG. 11 is a diagram showing a sixth manufacturing process following the manufacturing process shown in FIG. 10;

FIG. 12 is a diagram showing a seventh manufacturing process that follows the manufacturing process shown in FIG. 11.

FIG. 13 is a diagram showing an eighth manufacturing process following the manufacturing process shown in FIG. 12;

FIG. 14 is a diagram showing a ninth manufacturing process that follows the manufacturing process shown in FIG. 13.

FIG. 15 is a diagram showing a tenth manufacturing process following the manufacturing process shown in FIG. 14.

16 is a diagram showing an eleventh manufacturing process following the manufacturing process shown in FIG. 15. FIG.

FIG. 17 is a diagram showing an interconnection state of the capacitive elements in the manufacturing process shown in FIG.

FIG. 18 is a diagram showing a twelfth manufacturing process following the manufacturing process shown in FIG. 16;

19 is a diagram showing a cross-sectional structure of another configuration of the capacitive element shown in FIG.

FIG. 20 is a diagram showing a structure of a main portion of a semiconductor memory device according to another embodiment of the present invention.

21 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

FIG. 22 is a diagram schematically showing an overall configuration of a semiconductor memory device which is still another embodiment of the present invention.

FIG. 23 is a diagram showing a specific configuration example of a signal input circuit and a signal output circuit in a semiconductor memory device.

FIG. 24 is a diagram showing a structure of a main portion of a semiconductor memory device according to still another embodiment of the present invention.

FIG. 25 is a diagram schematically showing an overall configuration of a conventional semiconductor memory device.

FIG. 26 is a diagram showing a configuration of a memory cell array portion of the semiconductor memory device shown in FIG. 25 and circuits related thereto.

FIG. 27 is a diagram showing a structure of a portion related to one word line in a conventional semiconductor memory device.

28 is a signal waveform diagram representing an operation of the high voltage generation circuit shown in FIG. 27.

29 is a signal waveform diagram representing an operation of the word line drive signal generation circuit shown in FIG.

30 is a diagram showing a structure of the stabilizing capacitor shown in FIG. 27, a connection configuration, and an electrically equivalent circuit thereof.

[Explanation of symbols]

 1 memory cell 2 bit line 3 word line 5 memory cell selection transistor 27 high voltage output node 33a capacitive element 33b capacitive element 33c capacitive element 33d capacitive element 330 stabilizing capacitance 700 semiconductor memory device 702 memory cell array 704 internal step-down circuit 706 Array driving circuit 708 Peripheral circuit 710 Peripheral control circuit 712 Input / output circuit 750 Signal input circuit 760 Signal input circuit First stage inverter circuit 762 p-FET 764 n-FET 770 Inverter circuit 800 Signal output circuit 810 Last stage of signal output circuit Inverter circuit 812 p-FET 814 n-FET 830 External terminal 833 Stabilizing capacity 900 Word line drive means HVG high voltage generation circuit HSF Word line drive signal generation circuit ADXi (unit) X decoder WDi ( Unit) Word line driver ADX X decoder WD Word line drive circuit

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[Procedure amendment]

[Submission date] March 14, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 24

[Correction method] Change

[Correction content]

FIG. 24

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7210-4M H01L 27/10 325 V

Claims (5)

[Claims] 1. A memory cell array including a plurality of memory cells arranged in a matrix, a plurality of word lines each having one row of memory cells connected thereto, and a plurality of word lines responsive to an address signal. A word line selection means for generating a word line selection signal for selecting a word line from a source, a boosting means for boosting a first power supply voltage applied to a first power supply voltage node to generate a high voltage, In response to a word line selection signal from the word line selection means, word line drive means for transmitting the high voltage generated by the boosting means onto the selected word line, an output node of the boosting means, and a second A semiconductor memory device comprising: a plurality of capacitive elements connected in series with a power supply voltage node. 2. Each of the memory cells includes an insulated gate field effect transistor, and a circuit portion for directly transmitting a signal to the memory cell array portion includes an insulated gate field effect transistor as a constituent element thereof. 2. The semiconductor according to claim 1, wherein each of the capacitive elements is formed of an insulated gate field effect transistor having the same insulating film thickness as a transistor of the memory cell or a transistor of a constituent element of the circuit portion. Storage device. 3. The semiconductor memory device includes a step-down circuit that steps down a power supply voltage applied from the outside to generate an internal power supply voltage, and the internal power supply voltage is applied to each of the plurality of capacitive elements. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured by using an insulated gate field effect transistor having the same insulating film thickness as the insulated gate field effect transistor included in the circuit. 4. A memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines each having one row of memory cells connected thereto, and in response to an address signal, A word line selection means for generating a word line selection signal for selecting a word line from a plurality of word lines; a boosting means for boosting the first power supply voltage to generate a high voltage; In response to a word line selection signal, a word line driving means for transmitting the high voltage generated by the boosting means onto the selected word line, an insulated gate field effect transistor as a constituent element, and directly connected to an external terminal. A first circuit connected to the outside of the device for inputting or outputting a signal; and an insulating film which is the same as the gate insulating film of the insulated gate field effect transistor of the first circuit. A semiconductor memory device comprising: a thick insulated gate field effect transistor, and a capacitive element provided between an output node of the boosting means and a second power supply voltage source. 5. A boosting capacitive element having one electrode connected to a clock signal input node to which a clock signal is input, a power supply potential node to which a power supply potential is applied, and the other electrode of the boosting capacitive element. A first diode element connected in between, a second diode element connected between the other electrode of the boosting capacitive element and an output node, and between the output node and a ground potential node A plurality of stabilizing capacitive elements connected in series, and high voltage generating means for outputting a potential higher than a power supply potential applied to the power supply potential node to the output node, Semiconductor integrated circuit device.