JPH06188377A - Input/output protective device - Google Patents

Abstract

PURPOSE:To obtain an I/O protective device which can be manufactured by the conventional standard manufacturing process, and applied to the protective circuit of an open drain output, the input signal interface between different power supply voltages, etc. CONSTITUTION:An I/O protective circuit structure is constituted by arranging a parasitic lateral bipolar transistor or a thick film MOS transistor, between an outer I/O terminal 6 and a power supply terminal 5 of an MOS type semiconductor integrated circuit device. In the bipolar transistor, a well 3 which has not yet been connected with an external potential is applied to a base. In the MOS transistor, the well is applied to a substrate. By the above structure the sufficient surge withstand voltage can be obtained. The I/O protective device can obtain the signal interface to the outside, at a signal level exceeding the power supply potential level on the side where the protective element of this structure is added. The I/O protective device can be manufactured by the conventional standard manufacturing process, and applied to the protective circuit of an open drain output, the input signal interface between different power supply voltages, e.g. 5V-3V, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output protection circuit for a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit device is provided with a surge protection circuit as shown in FIG. 5 in its input / output buffer section in order to protect its external input / output terminals from surge damage. In order to safely release the surge charge applied to the external input / output terminal 6 to the power supply, the external input / output terminal, VSS ground power supply and VDD
An NchMOS transistor diode 18 and a PchMOS transistor diode 19 are provided between the power supplies as protection circuit elements. The NchMOS transistor diode plays a role of releasing the surge charge to the VSS power source, and the PchMOS transistor diode plays a role of releasing the surge charge to the VDD power source, which prevents the surge destruction of the input / output buffer circuit 17 and the internal circuit.

However, in this conventional surge protection circuit structure, when the signal potential of the external input / output terminal is higher than VDD, a forward current flows to VDD through the PchMOS transistor diode 19 for surge protection, so that external The signal potential of the input / output terminal 6 does not reach a level higher than VDD, and this protection circuit structure cannot cope with an interface having a signal level higher than VDD. On the other hand, when the signal potential of the external input / output terminal 6 is lower than VSS, the surge protection NchMOS transistor diode 18
Since a forward current flows through VSS through VSS, the signal potential of the external input / output terminal does not reach the level of VSS or lower, and this protection circuit structure cannot cope with the interface of the signal level of VSS or lower. That is, in the surge protection circuit structure of the external input / output terminal which has been generally used conventionally, the power supply voltage range (VSS to V
It could not cope with the signal interface with the external circuit at the signal level exceeding DD).

However, generally, the operating power supply voltage and the input / output signal level of each semiconductor integrated circuit device or electronic circuit are not constant, and the input / output signal interface between these different operating power supply voltages and signal levels is electronic. Mandatory in equipment systems. In order to provide an interface between different signal levels like this, conventionally, with respect to input / output terminals that process signals exceeding the power supply voltage, it is possible to remove the surge protection element for the power supply in the direction exceeding the power supply voltage. I've been An example thereof is shown in FIGS. 6 and 7. FIG. 6 shows a conventional Nch open drain output buffer circuit, and FIG. 7 shows an input buffer circuit. Since the semiconductor integrated circuit device interfaces with an external signal higher than the VDD power supply voltage level, the surge protection element on the VDD power supply side cannot be provided, and the NchMOS transistor diode 1 is provided only on the VSS power supply side as a surge protection element.
8 are provided.

[0005]

However, with these conventional circuit configurations, it is difficult to obtain a sufficient surge withstand voltage, and in particular with miniaturization of the manufacturing process of the MOS type semiconductor integrated circuit device, reliability is required. There is a problem that the surge withstand voltage standard cannot be satisfied. As a result, in the conventional standard manufacturing process, the input / output interface at the signal level exceeding the power supply voltage cannot be realized with the above-described conventional external input / output terminal surge protection circuit configuration. In the prior art, in order to solve this problem, a special manufacturing process is introduced to deal with the problem, but there is a big problem that the manufacturing cost increases due to an increase in the number of mask processes. On the other hand, due to inevitability due to process miniaturization and demand for low power consumption operation, recent MO
In many S-type semiconductor integrated circuit devices, the operating power supply voltage is shifting from the conventional 5V power supply voltage operation to the power supply voltage operation near 3V. On the other hand, since semiconductor integrated circuit devices operating at 5V power supply voltage and electronic circuits are also used in parallel, the interface of signals between different power supply voltages and input / output signal levels is becoming more and more essential. . It is an object of the present invention to use a conventional standard manufacturing process, to obtain an input / output interface with a signal level exceeding the power supply voltage of the semiconductor integrated circuit device, and to obtain a sufficient surge withstand voltage. It is to provide an output protection circuit.

[0006]

The input / output protection device of the present invention eliminates the current path from the external input / output terminal for the input / output signal level during normal operation to the power supply through the surge protection element, while eliminating the surge voltage. When an excessively high level potential as described above is applied to the external input / output terminal, the surge charge can be released from the external input / output terminal to the power supply.

According to a first aspect of the present invention, a semiconductor substrate of one conductivity type, a well of a conductivity type opposite to the one conductivity type formed on the surface of the semiconductor substrate, and a well surface formed so as to face each other. An input / output protection device for a semiconductor integrated circuit device comprising a plurality of same conductivity type high-concentration diffusion regions,
At least one high-concentration diffusion region of the plurality of high-concentration diffusion regions is connected to an external input / output terminal, and at least one high-concentration diffusion region that opposes the high-concentration diffusion region is connected to a power supply potential terminal, and the well is connected to the well. Is characterized in that no external potential is applied.

A second aspect of the present invention is a semiconductor substrate of one conductivity type, a well of a conductivity type opposite to the one conductivity type formed on the surface of the semiconductor substrate, and the same well formed on the surface of the well. What is claimed is: 1. An input / output protection device for a semiconductor integrated circuit device, comprising a MOS type transistor composed of a conductive high-concentration source region, a high-concentration drain region, and a thick gate insulating film, wherein the high-concentration drain region is an external input / output. The high-concentration source region is connected to a power supply potential terminal, and the well is not supplied with an external potential.

[0009]

In the input / output protection circuit according to the first aspect of the present invention, the well of the opposite conductivity type is interposed between the high-concentration diffusion regions connected to the external input / output terminal and the power supply terminal, and the lateral bipolar Since a transistor is formed, no current flows if the potential of the external input / output terminal is within the collector-emitter breakdown voltage when the base potential of this lateral bipolar transistor is open. Even if a signal from outside the level is added,
It does not affect the signal level. On the other hand, if a high potential that far exceeds the collector-emitter breakdown voltage, such as a surge pulse, is applied to the external input / output terminals, the high concentration connected to the well that is the base of the lateral bipolar transistor and the power supply terminal By causing breakdown in the reverse junction between the diffusion regions, surge charges applied to the external input / output terminals can be rapidly released to the power supply terminals. Therefore, even when a high-potential surge pulse is applied from the outside, the potential of the external input / output terminal does not rise to a potential higher than the withstand voltage between the collector and emitter of the lateral bipolar transistor, thus forming an input / output buffer circuit. MOS devices can be protected from surge breakdown.

The basic circuit operation of the input / output protection circuit according to the second aspect of the present invention is the same as that of the input / output protection circuit according to the first aspect of the present invention, except that a thick gate insulating film is used. By providing the thick film MOS transistor structure by adding the gate electrode, the PN reverse junction can be broken down at a lower external input / output terminal potential when a surge pulse is applied, and a higher surge withstand voltage can be obtained.

In normal operation, for example, even if a signal having a level higher than the VDD power supply potential is applied to the external input / output terminal,
No current flows unless the difference between the signal level and the potential level of the gate electrode of the thick film MOS transistor exceeds the threshold voltage of the thick film MOS transistor or the reverse junction breakdown voltage between the collector and emitter of the parasitic lateral transistor, The impedance between the external input / output terminal and the VDD power supply terminal is high, and even if a signal from the outside having a level higher than the VDD power supply voltage is applied to the external input / output terminal, the signal level is not affected.

On the other hand, when a very high voltage such as a surge pulse is applied to the external input / output terminal, first, the thick film MO
The S transistor is turned on, and a current starts to flow from the external input / output terminal serving as the source to the VDD power supply terminal serving as the drain. Since this thick film MOS transistor structurally includes a parasitic lateral transistor, even if a minute current flows, the collector (external input / output terminal)-
When a current starts to flow between the emitters (VDD power supply terminal), the breakdown of the junction occurs at a voltage lower than that when no current is flowing, and surge charge can be rapidly released to the VDD power supply. Therefore, the maximum value of the potential applied to the external input / output terminal can be suppressed lower than that of the structure of the input / output protection circuit according to the first aspect of the present invention, and the MOS device constituting the input / output buffer circuit is protected from surge damage. It can be prevented more safely.

[0013]

1 is a cross-sectional view of an input / output protection circuit according to the first aspect of the present invention. A pair of P ⁺ diffusion regions that oppose each other is formed in a P-type semiconductor substrate or an N-type well surrounded by a P-type well that does not apply an external potential, and one of the P ⁺ diffusion regions is used as an external input / output terminal and the other is formed. VDD of P ⁺ diffusion area
By connecting to the power supply terminal, a surge protection circuit for the VDD power supply side is configured.

In order for this protection circuit to fulfill its intended function, it is necessary to satisfy the following relationship.
{(H level of interface signal) − (VDD level)} <(Collector-emitter breakdown voltage of lateral PNP transistor) <(M configuring input / output buffer circuit
Withstand voltage of OS device).

FIG. 2 shows a structure using an N-type semiconductor substrate or an N-type well. N-type semiconductor substrate or
Forming a pair of N ⁺ diffusion region to combat P type well without applying an external potential surrounded by N-type well, the one of the N ⁺
Use the diffusion region as the external input / output terminal and the other N ⁺ diffusion region as V
By connecting to the SS power supply terminal, a surge protection circuit for the VSS power supply side is configured.

FIG. 3 is a sectional view of an input / output protection circuit according to the second aspect of the present invention. In addition to the structure of FIG. 1, a gate electrode having opposite P ⁺ diffusion region pairs Insulation of thick film layer is provided, constitutes a Pch thick-film MOS transistor to each source or drain the P ⁺ diffusion region pairs against ,
Surge protection circuit for VDD power supply side. The absolute value of the ON-OFF threshold voltage (threshold value; negative value) of the Pch thick film MOS transistor is equal to or greater than the difference between the H level potential of the desired interface signal and the gate electrode potential.
In addition, the gate insulating film thickness, the gate electrode material, and the gate electrode potential are selected and used so as to be less than the breakdown voltage of the MOS device that constitutes the input / output buffer circuit.

In order for this protection circuit to fulfill its intended function, it is necessary to satisfy the following relationship.
{(H level of interface signal)-(Thick film PchM
Gate electrode potential of OS transistor)} <{| Thick film Pc
hMOS transistor threshold voltage (negative value)
|} <(Breakdown voltage of the MOS device forming the input / output buffer circuit). In the above relational expression, the gate electrode potential of the thick film PchMOS transistor can usually be selected within the range of VSS to VDD, and the threshold voltage of the thick film PchMOS transistor can be selected by selecting the film thickness of the gate insulating film, the gate electrode material, etc. Can be adjusted. Therefore, as compared with the protection circuit structure using only a simple lateral PNP transistor as shown in FIG. 1, there is an advantage that the degree of freedom in setting the potential of the external input / output terminal for starting breakdown is high and desired characteristics can be easily obtained.

FIG. 4 shows an Nch thick film MOS transistor. In addition to the structure shown in FIG. 2, a gate electrode having a thick insulating film is provided in the opposing N ⁺ diffusion region pair portion to counter it. A pair of N ⁺ diffusion regions serving as a source or a drain of the Nch thick film MOS transistor,
Use a surge protection circuit for the VSS power supply side. The ON-OFF threshold voltage (threshold value; positive value) of this Nch thick film MOS transistor is equal to or greater than the difference between the L level potential of the desired interface signal and the gate electrode potential, and is a MOS device that constitutes the input / output buffer circuit. The gate insulating film thickness, the gate electrode material, and the gate electrode potential are selected and used so that the breakdown voltage becomes equal to or lower than the withstand voltage.

The element structure corresponding to FIGS. 1 to 4 is as follows.
Each can be expressed by using the circuit elements shown in FIGS. That is, the structure of FIG. 1 is a lateral PNP transistor 22 (FIG. 8) based on an N well not connected to an external potential, and the structure of FIG. 2 is a lateral NPN transistor 23 based on a P well not connected to an external potential.
In FIG. 9, the structure of FIG. 3 has a PchMOS transistor 24 (FIG. 10) whose substrate is an N well that is not connected to an external potential.
In the structure of FIG. 4, the circuit structure can be expressed by the NchMOS transistor 25 (FIG. 11) whose substrate is the P well which is not connected to the external potential.

Next, other embodiments corresponding to FIGS. 8, 9, 10, and 11 are shown in FIGS. 12 and 13, 14 and 15, 16 and 17, and 18 and 19, respectively. .

12 is applied to the Nch open drain output buffer circuit and FIG. 13 is applied to the input buffer circuit, and a lateral PNP transistor 22 based on an N well not connected to an external potential is added. , VDD is the example of the surge protection circuit to the power supply side.
It is possible to cope with an interface with an H level signal exceeding the D power supply potential level.

FIG. 14 is applied to the Pch open drain output buffer circuit, and FIG. 15 is applied to the input buffer circuit, and the lateral NPN transistor 23 based on the P well which is not connected to the external potential is added. This is an example of a surge protection circuit for the VSS power supply side.
It is possible to cope with an interface with an L-level signal below the power supply potential level.

FIG. 16 is applied to an Nch open drain output buffer circuit, and FIG. 17 is applied to an input buffer circuit, and a thick film PchMOS transistor 24 having an N well not connected to an external potential as a substrate is added. , VDD is an example of a surge protection circuit to the power supply side.
It is possible to cope with an interface with an H level signal exceeding the power supply potential level.

FIG. 18 is applied to a Pch open drain output buffer circuit, and FIG. 19 is applied to an input buffer circuit, and a thick film NchMOS transistor 25 having a P well substrate not connected to an external potential as a substrate is added. , VSS is an example of a surge protection circuit for the power supply side.
It is possible to cope with an interface with an L level signal that is lower than the power supply potential.

The above embodiment does not require a special manufacturing process and can be manufactured by the conventional general manufacturing process, so that the cost of the manufacturing process does not increase due to the introduction of the input / output protection circuit structure of the present invention.

FIG. 20 shows a sectional view of an example of a protection circuit according to the present invention, which is a combination of FIG. 1 and FIG. 2, and FIG. 21 shows an embodiment in which it is applied as a protection circuit for an input terminal. By adding a lateral PNP transistor 22 based on an unconnected N well and a lateral NPN transistor 24 based on an unconnected P well to the input buffer circuit, surge destruction of the input buffer circuit is prevented, and V
H level above DD power supply potential and L below VSS power supply potential
Supports interface with signals having levels. Although not shown, a similar input protection circuit corresponding to an input interface may be formed by combining FIGS. 3 and 4 of the present invention, or FIGS. 1 and 4 or FIGS. 2 and 3. it can.

[0027]

According to the structure of the present invention, an input / output buffer circuit having high reliability of surge protection and corresponding to an interface with an H level signal exceeding the VDD power supply potential or an L level signal below the VSS power supply potential. And, it is possible to provide a semiconductor integrated circuit device incorporating the same at low cost.

[Brief description of drawings]

FIG. 1 is a sectional view of an input / output protection circuit according to an embodiment of the first aspect of the present invention.

FIG. 2 is a sectional view of an input / output protection circuit according to another embodiment of the first aspect of the present invention.

FIG. 3 is a sectional view of an input / output protection circuit according to the second embodiment of the present invention.

FIG. 4 is a sectional view of an input / output protection circuit according to another embodiment of the second aspect of the present invention.

FIG. 5: Conventional input / output protection circuit diagram

FIG. 6 Conventional open drain output protection circuit diagram

FIG. 7 is a conventional input protection circuit diagram for interfacing with an H-level signal exceeding the VDD power supply voltage.

8 is an equivalent circuit diagram of the cross-sectional view of the input / output protection circuit shown in FIG. 1 of the present invention.

9 is an equivalent circuit diagram of the cross-sectional view of the input / output protection circuit shown in FIG. 2 of the present invention.

10 is an equivalent circuit diagram of the cross-sectional view of the input / output protection circuit shown in FIG. 3 of the present invention.

11 is an equivalent circuit diagram of the cross-sectional view of the input / output protection circuit shown in FIG. 4 of the present invention.

FIG. 12 is a diagram showing an embodiment in which the input / output protection circuit according to the first aspect of the present invention is applied to an Nch open drain output protection circuit.

FIG. 13 is a diagram showing an embodiment in which the input / output protection circuit according to the first aspect of the present invention is applied to an input protection circuit of a 5V / 3V interface.

FIG. 14 is a diagram showing an embodiment in which the input / output protection circuit according to the first aspect of the present invention is applied to a Pch open drain output protection circuit.

FIG. 15 is a diagram showing an embodiment in which the input / output protection circuit according to the first aspect of the present invention is applied to an input protection circuit of a -5V / -3V interface.

FIG. 16 is a diagram showing an embodiment in which the input / output protection circuit according to the second aspect of the present invention is applied to an Nch open drain output protection circuit.

FIG. 17 is a diagram showing an embodiment in which the input / output protection circuit according to the second invention of the present invention is applied to the input protection circuit of the 5V / 3V interface.

FIG. 18 is a diagram showing an embodiment in which the input / output protection circuit according to the second aspect of the present invention is applied to a Pch open drain output protection circuit.

FIG. 19 is a diagram showing an embodiment in which the input / output protection circuit according to the second aspect of the present invention is applied to the input protection circuit of the -5V / -3V interface.

FIG. 20 is a cross-sectional view of an input protection circuit to which one embodiment of the first invention of the present invention and another embodiment are applied in combination.

FIG. 21 is a diagram for explaining an embodiment in which the input protection circuit shown in FIG. 20 of the present invention is applied to an input circuit of a different power supply input interface.

[Explanation of symbols]

1 P-type semiconductor substrate 2 P-type well or P-type semiconductor substrate 3 N-type well not connected to an external potential 4 P ⁺ diffusion region 5 VDD power supply terminal 6 external input / output terminal 7 thick insulating film 8 gate electrode 9 gate electrode Terminal 10 N-type semiconductor substrate 11 N-type well or N-type semiconductor substrate 12 P-type well not connected to an external potential 13 N ⁺ diffusion region 14 VSS power supply terminal 15 Gate electrode terminal 16 Internal signal terminal 17 Input / output buffer circuit 18 NchMOS transistor Diode 19 PchMOS transistor Diode 20 NchMOS transistor 21 Input buffer 22 Lateral PNP transistor 23 Lateral NPN transistor 24 Thick film PchMOS transistor 25 Thick film NchMOS transistor

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type, and a well of a conductivity type opposite to the one conductivity type formed on the surface of the semiconductor substrate.
An input / output protection device for a semiconductor integrated circuit device, comprising: a plurality of one-conductivity-type high-concentration diffusion regions formed so as to face each other on the well surface, wherein at least one of the plurality of high-concentration diffusion regions is provided. One of the high concentration diffusion regions is connected to an external input / output terminal, at least one high concentration diffusion region that opposes the high concentration diffusion region is connected to a power supply potential terminal, and an external potential is not applied to the well. I / O protection device. 2. A semiconductor substrate of one conductivity type, and a well of a conductivity type opposite to the one conductivity type formed on the surface of the semiconductor substrate.
What is claimed is: 1. An input / output protection device for a semiconductor integrated circuit device, which comprises a MOS type transistor composed of a high-concentration source region of one conductivity type, a high-concentration drain region, and a thick gate insulating film formed on the well surface, The input / output protection device, wherein the high-concentration drain region is connected to an external input / output terminal, the high-concentration source region is connected to a power supply potential terminal, and an external potential is not applied to the well.