JPH06187433A - Graphic processor - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a pipeline to increase the graphic attribute change speed by adding a memory, where attributes of graphic data are stored, and a management table which easily manages contents of this memory. CONSTITUTION:An attribute storage memory management table 32 receives attribute information from a graphic information display list and compares it with contents of the management table to discriminate whether the attribute value is stored in attribute storage memories 36, 38, and 40 in the rear stage or not; and if it is not stored there, a mismatch signal 44 is sent to a processor 30, and attribute storage memories and the management table are updated. If the attribute value is stored there, address information is sent to a line generator or a memory device 34 in the rear stage. In this case, address information passes through a pipeline 46 connecting the line generator provided with a processor device 12 and attribute storage memories or a memory device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic processor having a pipeline structure, and more particularly to a graphic processor capable of changing graphic attributes at high speed.

[0002]

2. Description of the Related Art A graphic processing apparatus such as CAD / CAM for processing graphic data often has a pipeline structure as shown in FIG. 1 in order to speed up the processing. The pipeline structure is a method suitable for performing fixed processing repeatedly at high speed.

In FIG. 1, 10 is a graphic information display list, 12 is a processor unit, 14 is a straight line generator, and 16 is a memory unit. A command for creating a figure and coordinate data of the figure flow to the figure processing device having the pipeline structure, and finally, the figure is written as the figure information in the memory device 16 placed at the final stage.

Here, for example, when a figure as shown in FIG. 2 is written, the figures a, b, c in FIG.
1 is sent to the straight line generator 14 in FIG. 1, and the attribute values such as colors of the respective figures are sent to the memory device 16. The straight line generator 14 decomposes the received coordinate values into pixel information and sends it to the memory device 16. The memory device 16 draws the graphic information in accordance with the previously received graphic attribute information. In this way, many commands and data will flow on the pipeline.

[0005]

According to the prior art,
When the attribute changes for each figure, such as figure a → b → c as shown in FIG. 2, it is necessary to rewrite the register that holds the attribute value on the straight line generator 14 or the memory device 16 each time. To do. For example, in FIG. 2, if the color attributes of figures a and b change, and c has the same attributes as a again, b is drawn halfway though the attributes of a and c are the same. Therefore, it is necessary to rewrite the attribute register. Therefore, there is a problem that the rewriting time of the register and the passage of the attribute data on the pipeline reduce the throughput of the system.

Further, since all the attributes possessed by the respective figures do not usually change, the processor 12 in the preceding stage, which controls the straight line generator 14 and the memory device 16, searches for differences in the attributes and finds only the different attributes. A method of changing it is also conceivable, but in this case, there is a problem that the load on the processor becomes large.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a graphic processing apparatus capable of improving the efficiency of use of a pipeline and changing graphic attributes at high speed. It is what

[0008]

According to the present invention, in a graphics processing device having a pipeline structure, a plurality of memories for respectively storing attributes of graphic data, and a table for controlling and managing the graphics data attribute storage memory are provided. The object is achieved by reducing the rewriting of the attribute value of the figure and improving the efficiency of use of the pipeline.

[0009]

According to the present invention, a plurality of memories for respectively storing the attributes of graphic data are provided, and whether or not the graphic attribute information is stored in any of the plurality of graphic data attribute storage memories is stored. Determined by the control / management table. As a result, if not stored, the attribute storage memory and control / management table are updated with new attribute data, and if stored, the attribute information is specified.

Therefore, the processor for extracting the graphic information can flow the graphic information in the pipeline without checking the difference from the attribute of the immediately preceding graphic data, and the rewriting of the attribute register is reduced. And speed up processing,
The efficiency of pipeline use is improved.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an outline of one embodiment of the present invention. In FIG. 3, 12 is a processor device, which has a processor 30 and an attribute storage memory management table 32. Reference numeral 34 is a straight line generator or memory device, and memories 36, 38 for holding the attributes of figures
40 (in this embodiment, since there are only three graphic attributes, it has a configuration of 3 units), and an address register 42 for pointing the address of each attribute memory.
Since the attribute is basically changed by changing the address register 42, the attribute value can be easily changed.

The attribute storage memory management table 32 is shown in FIG.
The attribute information is received from the graphic information display list 10 of FIG.
It is judged whether or not the attribute value is stored in 6, 38 and 40, and if it is not stored, the mismatch signal 44
Is sent to the processor 30 to update the attribute storage memory and the management table.

When the attribute value is stored, the address information is sent to the straight line generator or memory device 34 in the subsequent stage. At this time, the address information is the processor device 1
2 and a pipeline 46 connecting the straight line generator or the memory device having the attribute storage memory.

FIG. 4 is a block diagram showing an outline of the attribute storage memory management table. Next, the attribute storage memory address generation procedure will be described with reference to FIG. Figure 4
In 50, 50 is an attribute storage memory management table,
The number of comparators 52 to 66 equal to the product N × M of the number N of attributes of the graphic processing device and the number M of addresses of the attribute storage memory placed in the subsequent stage are placed as shown in FIG. At the left end of the management table 50, a 1-bit P flag indicating whether the address of the attribute storage memory is valid or invalid is placed.
When valid, it becomes "0", and when invalid, it becomes "1". The initial state is all invalid. 68, 70, and 72 are attribute storage registers, which are the graphic information display list 1 of FIG.
The attribute information sent from 0 is stored, and the attribute setting end signal 74 is generated. Then, the contents of the management table 50 are compared by the comparators 52 to 66.

As a result, when they do not match or when the P flag is invalid, the mismatch signal gate 76
A mismatch signal 44 is generated. At this time, the processor 30 updates the subsequent attribute storage memories 36 to 40 and the management table 50 by the mismatch signal 44.

On the contrary, when no mismatch signal is generated, the address data 78 pointed to by the row matching the set attribute is generated and sent as the address information of the attribute storage memories 36 to 40 in the subsequent stage. In this case, FIG.
In the pipeline 46, the addresses of the attribute storage memories 36 to 40 are sent to the subsequent stage only once, and the attributes can be easily changed.

Furthermore, since the above-mentioned mismatch rarely occurs in reality, the mechanism with the addition of the attribute storage memory and the attribute storage memory management table makes it possible to improve the efficiency of the pipeline and the speed of attribute change. It is clear that

[0019]

As described above, according to the present invention, the load of the processor is increased by adding the memories for storing the attributes of the graphic data and the management table for easily managing the contents of the memories. Can be reduced.

Further, after the straight line generator, extra attribute data does not flow out, the efficiency of the pipeline is improved, and the rewriting of the attribute register is reduced, so that the overhead time of the straight line generator and the memory device is reduced. Reduction is planned.

Therefore, there is an excellent effect that the overall throughput of the graphic processing apparatus can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a pipeline structure of a conventional graphic processing apparatus.

FIG. 2 is a diagram showing a change in the attribute of a figure.

FIG. 3 is a block diagram showing an outline of an embodiment of the present invention.

FIG. 4 is a block diagram showing an outline of an attribute storage memory management table according to the present invention.

[Explanation of symbols]

 10 ... Graphic information display list 12 ... Processor device 14 ... Straight line generator 16 ... Memory device 30 ... Processor 32 ... Attribute storage memory management table 36, 38, 40 ... Attribute storage memory 42 ... Address register 44 ... Mismatch signal 46 ... Pipeline 50 ... Management table 52-66 ... Comparators 68, 70, 72 ... Attribute register 74 ... Attribute setting end signal 76 ... Mismatch signal gate 78 ... Address data

Claims (1)

[Claims] 1. A graphic processing apparatus having a pipeline structure, comprising: a plurality of memories for respectively storing attributes of graphic data; and a table for controlling and managing the graphic data attribute storage memory. Figure processing device that can change the figure attribute at high speed by reducing the number of lines and improving the efficiency of pipeline use.