JPH0618216B2 - Manufacturing method of GaAs field effect transistor - Google Patents
Manufacturing method of GaAs field effect transistorInfo
- Publication number
- JPH0618216B2 JPH0618216B2 JP57131954A JP13195482A JPH0618216B2 JP H0618216 B2 JPH0618216 B2 JP H0618216B2 JP 57131954 A JP57131954 A JP 57131954A JP 13195482 A JP13195482 A JP 13195482A JP H0618216 B2 JPH0618216 B2 JP H0618216B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- gaas
- gate electrode
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000013078 crystal Substances 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000005496 eutectics Effects 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000012808 vapor phase Substances 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 27
- 229910045601 alloy Inorganic materials 0.000 description 25
- 239000000956 alloy Substances 0.000 description 25
- 239000000758 substrate Substances 0.000 description 16
- 238000005275 alloying Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 239000011669 selenium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 2
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052711 selenium Inorganic materials 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001295 No alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005453 pelletization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Description
【発明の詳細な説明】 本発明は砒化ガリウム半導体装置に関する。The present invention relates to gallium arsenide semiconductor devices.
低雑音，高い遮断周波数，高出力等の特長を有するマイ
クロ波トランジスタとして、GaAs（砒化ガリウム）シヨ
ツトキ障壁ゲート電界効果トランジスタ（GaAs−ＳＢＧ
ＦＥＴ）が一般に知られている。As a microwave transistor having features such as low noise, high cutoff frequency, and high output, a GaAs (gallium arsenide) shutter barrier gate field effect transistor (GaAs-SBG)
FET) is generally known.
GaAs−ＳＢＧＦＥＴはｎ導電形の能動領域表面にソー
ス，ドレインとなるオーミツク接触電極を設けるととも
に、その中間にゲートとなるシヨツトキ接合電極を１つ
あるいは２つ設けて、それぞれシングルゲート構造ある
いはデユアルゲート構造を構成した構造となつている。
後者のデユアルゲート構造は第２ゲートバイアスによる
利得制御が可能となる特長が新に付加される。The GaAs-SBGFET is provided with an ohmic contact electrode serving as a source and a drain on the surface of an n-conducting type active region, and one or two Schottky junction electrodes serving as a gate in the middle of the ohmic contact electrode to have a single gate structure or a dual gate structure, respectively. The structure is composed of.
The latter dual gate structure is newly added with a feature that the gain can be controlled by the second gate bias.
第１図は従来のシングルゲート構造のＳＢＧＦＥＴ素子
の要部を示す断面図である。すなわち、Ｃｒを拡散させ
て絶縁体となつたGaAs基板１の主面にはGaAs層からなる
バツフア層２が形成され、かつこのバツフア層２上には
ｎ形エピタキシヤル層３が形成されている。このｎ形エ
ピタキシヤル層３は周辺をエツチングされて除去され、
メサ構造となつている。前記ｎ形エピタキシヤル層３上
には幅広のソース電極４およびドレイン電極５が平行に
形成されるとともに、両電極間には１本のゲート電極６
が配設されている。ゲート電極６はＴｉ，Ｗ，Ｐｔ，Ａ
ｌ，等からなりシヨツトキ障壁接合となるとともに、長
さ〔ｌ）は１μｍ程度となつている。また、ソース電極
４およびドレイン電極５は最下層にAuGe，中間層（バリ
ヤ層）にＮｉ，Ｍｏ，Ｐｔ等，最上層にＡｕ層を順次蒸
着し積層形成後３５０℃〜４００℃でアロイ処理（合金
化熱処理）を行ないオーミツク性接触を得ることにより
形成される。しかし、このアロイ処理時には、電極の積
層方向に沿つてＧａ，Ａｓ，Ｇｅ，Ａｕ等が相互拡散し
やすく、電極と基板間の合金化反応は不均一になりやす
いという欠点があることはよく知られている。FIG. 1 is a sectional view showing a main part of a conventional SBGFET device having a single gate structure. That is, a buffer layer 2 made of a GaAs layer is formed on the main surface of a GaAs substrate 1 which has been made into an insulator by diffusing Cr, and an n-type epitaxial layer 3 is formed on this buffer layer 2. . The n-type epitaxial layer 3 is etched around the periphery and removed,
It has a mesa structure. A wide source electrode 4 and a drain electrode 5 are formed in parallel on the n-type epitaxial layer 3 and a gate electrode 6 is provided between both electrodes.
Is provided. The gate electrode 6 is made of Ti, W, Pt, A
The length [l] is about 1 [mu] m as well as a junction barrier junction consisting of 1 and the like. Further, the source electrode 4 and the drain electrode 5 are formed by sequentially depositing AuGe on the lowermost layer, Ni, Mo, Pt, etc. on the intermediate layer (barrier layer), and Au layer on the uppermost layer, and forming an alloy at 350 ° C. to 400 ° C. after stacking ( Alloying heat treatment) to obtain ohmic contact. However, it is well known that during this alloying process, Ga, As, Ge, Au, etc. are easily diffused along the stacking direction of the electrodes, and the alloying reaction between the electrodes and the substrate is likely to be non-uniform. Has been.
これらの欠点に対する改善策としては、前記ソースおよ
びドレイン電極の中間層（バリヤ層）の電極材料を工夫
したり電極積層構造を変えること等が考えられる。As a remedy for these drawbacks, it is conceivable to devise the electrode material of the intermediate layer (barrier layer) of the source and drain electrodes or change the electrode laminated structure.
一方、最近、ＳＢＧＦＥＴの量産化に向けて、アロイ処
理後に素子の所望表面部分をパツシベーシヨン膜で被
い、素子特性の安定化，素子寿命の長期化を図ることが
試みられている。On the other hand, recently, for mass production of SBGFETs, it has been attempted to cover a desired surface portion of an element with a passivation film after alloying to stabilize the element characteristics and prolong the life of the element.
しかし、本願発明者の研究によればこのようなパツシベ
ーシヨンを行うと、ＦＥＴの耐圧劣化が生じ易くなるこ
とが判明した。この点について、検討した結果、パツシ
ベーシヨン時の熱処理によりオーミツク接触電極とGaAs
基板間の合金反応がさらに促進され電極成分の一部が基
板中へアロイ（合金）進行し、アロイ進行部分で動作時
に電界集中を起こし、耐圧劣化することがわかつた。However, according to the research by the inventor of the present application, it has been found that when such passivation is performed, the breakdown voltage of the FET is likely to deteriorate. As a result of studying this point, it was found that the ohmic contact electrode and GaAs were heat-treated during the passivation.
It has been found that the alloy reaction between the substrates is further promoted and a part of the electrode components progresses into the substrate as an alloy (alloy), electric field concentration occurs at the time of operation in the alloy progressing part, and the breakdown voltage is deteriorated.
オーミツク電極形成のためのアロイ処理時に電極の積層
方向（縦方向）に沿つてＡｕ，Ｇｅ，Ｇａ等が相互拡散
して不均一反応しやすいことは前述したが、電極形成後
に、パツシベーシヨンに伴い高温熱処理が行なわれるこ
のアロイ化は再び促進され基板に沿つて横方向にも進行
するものと考えられる。この横方向アロイ化は、実験の
結果、４４０℃前後になると顕微鏡でもアロイビツトと
して目視可能となることがわかつた。なお、この獲方向
アロイ進行成分は、主としてオーミツク電極中のＡｕで
あると推定される。すなわち、熱処理によりＡｕとＧｅ
が反応するとき、GaAs基板中にもＧｅがドナーとして拡
散されるが、このとき、Ａｕ原子の一部も基板中に拡散
し、アロイ進行するものと思われる。さらに、この横方
向アロイ化は結晶方向によつてその成長速さが異ること
も発見した。第３図は、横方向アロイ化の様子が結晶方
向によつて異なることを説明するための模式図である。
各電極を形成する能動層（ｎ形エピタキシヤル層３）の
表面が（１００）である場合、第３図中、オーミツク電
極７の周縁にはハツチングを施して示されるアロイ成長
部８が部分的に形成される。このアロイ成長は〔０１
０〕，〔００〕の方向，および、〔００１〕，〔００
〕の方向に成長しやすく（成長部，））また、一
点鎖線で示す〔０１〕，〔００〕方向ではわずかに
成長がみられる。（成長部）。また２点鎖線で示す
〔０１１〕，〔０〕方向には、ほとんどアロイ成長
は見られない。このように基板の結晶方向によつてアロ
イ進行の様子に差がみられる理由は、明らかではない
が、基板の結晶構造に帰因する異方性が関係しているも
のと思われる。例えばある特定の結晶において、エツチ
ング異方性が存在し、エツチビツト（ウエツトエッチン
グしたときに結晶面に形成される特定形状の凹）が形成
されることは知られているが、アロイ進行の場合もこの
場合と同じような異方性によりアロイビツトが存在しア
ロイ低調部，，が特に大きく成長するものと考えら
れる。なお、アロイ成長部との形状が差がみられる
が（成長部は先端部が半円形状を有し、成長部は小
さな成長層がいくつか集まつた形状となつている）成長
部がみられる電極の辺の長さは成長部のみられる電
極の辺の長さよりも長くなつており、このような場合
は、成長部にみられる小さな成長層がくつついて、成
長部のように一つの半円形状の成長形状になるものと
考えられる。As described above, during alloying for forming an ohmic electrode, Au, Ge, Ga, etc. are likely to interdiffuse along the electrode stacking direction (longitudinal direction) to cause a non-uniform reaction. It is considered that this alloying in which the heat treatment is performed is promoted again and progresses laterally along the substrate. As a result of experiments, it has been found that this alloying in the lateral direction becomes visible as an alloy bit even under a microscope at about 440 ° C. It should be noted that it is estimated that the advancing component of the alloy in the catching direction is mainly Au in the ohmic electrode. That is, by heat treatment, Au and Ge
Ge reacts as a donor in the GaAs substrate when reacts with, but at this time, it is considered that some of the Au atoms also diffuse into the substrate and proceed with alloying. Furthermore, it was also discovered that the growth rate of this lateral alloying differs depending on the crystal direction. FIG. 3 is a schematic view for explaining that the state of lateral alloying differs depending on the crystal direction.
When the surface of the active layer (n-type epitaxial layer 3) forming each electrode is (100), the alloy growth portion 8 shown by hatching is partially shown on the periphery of the ohmic electrode 7 in FIG. Is formed. This alloy growth is [01
0], [00] direction, and [001], [00]
It is easy to grow in the [] direction (growth part,)), and a slight growth is observed in the [01] and [00] directions indicated by the alternate long and short dash line. (Growth Department). Almost no alloy growth is observed in the [011] and [0] directions indicated by the two-dot chain line. The reason why there is a difference in the progress of alloying depending on the crystal direction of the substrate is not clear, but it is considered that the anisotropy attributed to the crystal structure of the substrate is involved. For example, it is known that there is etching anisotropy in a specific crystal and an etching bit (a concave shape having a specific shape that is formed on the crystal plane when wet etching is performed) is formed. It is considered that alloy bits exist due to the same anisotropy as in this case, and the alloy undertones, and, grow particularly large. Although there is a difference in shape from the alloy growth part (the growth part has a semicircular tip, the growth part has a shape in which several small growth layers are gathered) The length of the side of the electrode formed is longer than the side of the electrode formed in the growth part.In such a case, the small growth layer seen in the growth part is picked up and one half of the growth part is formed. It is considered that the growth shape will be circular.
また〔０１１〕および〔０〕に直交する電極辺に沿
う結晶面はエツチングすると庇状のいわゆる逆メサ形状
となる面であり、〔０１〕および〔０１〕に直交す
る電極辺に沿う結晶面は、エツチングによつて緩やかな
傾斜面を形作るいわゆる順メサ形状となる面であり、こ
のような特異なエツチングの異方性と同様にアロイ進行
異方性が存在して〔０１〕方向にはアロイ成長部が
生じるが〔０１１〕，〔０〕方向にはアロイ成長が
生じないものと推定される。ところでGaAs電界効果トラ
ンジスタでは、高周波特性向上のために各電極間の距離
は、狭くなつている。The crystal planes along the electrode sides orthogonal to [011] and [0] are so-called inverted mesa shapes when etched, and the crystal planes along the electrode sides orthogonal to [01] and [01] are , A surface having a so-called forward mesa shape that forms a gently inclined surface by etching, and alloy progress anisotropy exists in the same manner as the peculiar anisotropy of etching, and the alloy is oriented in the [01] direction. It is estimated that alloy growth does not occur in the [011] and [0] directions although the growth portion is generated. By the way, in the GaAs field effect transistor, the distance between the respective electrodes is narrowed in order to improve high frequency characteristics.
例えば第１図においてゲート電極６とソース電極４，あ
るいはドレイン電極５間は、１．５〜２μｍ程度であ
る。このように近接配置された電極間の一部に前述した
如き、アロイ進行部が生ずると、その部分でシヨート不
良，耐圧不良をひきおこすこととなる。For example, in FIG. 1, the distance between the gate electrode 6 and the source electrode 4 or the drain electrode 5 is about 1.5 to 2 μm. If the alloy advancing portion as described above occurs in a portion between the electrodes arranged in proximity to each other as described above, a short defect and a withstand voltage defect are caused in that portion.
そこで、本発明者は電流の流れる方向、すなわちチヤネ
ル方向（電極の隣接する方向）を横方向アロイの成長が
遅い方向と一致させることによつて、隣接する電極間の
シヨート不良を防止し、耐圧劣化も最小限に抑えること
ができることに気が付き、本発明を成した。Therefore, the present inventor prevents short-circuit defects between adjacent electrodes by matching the direction of current flow, that is, the channel direction (the direction in which the electrodes are adjacent) with the direction in which the growth of the lateral alloy is slow, and prevents breakdown voltage. The inventors have realized that the deterioration can be suppressed to a minimum, and have accomplished the present invention.
したがつて、本発明の目的は、GaAs基板の主面に近接し
て少なくとも２つの電極を設ける半導体装置において、
その製造時に高温熱処理が行なわれても、電極間のシヨ
ートが発生しないような電極配置パターンを有するGaAs
電界効果トランジスタを提供することにある。Therefore, an object of the present invention is to provide a semiconductor device in which at least two electrodes are provided in the vicinity of the main surface of a GaAs substrate.
GaAs having an electrode layout pattern that does not cause short-circuit between electrodes even if high-temperature heat treatment is performed during its manufacture.
It is to provide a field effect transistor.
また、本発明の他の目的は、高温で（例えば４００℃前
後の温度で）パツシベーシヨンを行なうGaAs−ＳＢＧＦ
ＥＴを高歩留で製造する方法を提供することにある。Another object of the present invention is to perform GaAs-SBGF which is passivated at a high temperature (for example, at a temperature around 400 ° C.).
It is to provide a method for producing ET with a high yield.
かかる目的を達成するための本発明は、（１００）結晶
面をもつＧａＡｓエピタキシャル層主面に互いに近接
し、所定長さ方向に沿うソース電極、ゲート電極および
ドレイン電極が配列されたメサ型のＧａＡｓ電界効果ト
ランジスタの製法であって、前記それぞれの電極の所定
長さ方向が〔０１１〕、〔０１〕、〔０〕、〔０
１〕のいずれか一つの方向に沿い、前記ゲート電極を
前記主面に対してショットキ接合を成す金属電極により
形成し、前記ソース電極およびドレイン電極をそれぞれ
前記主面に対してＡｕＧｅ層、Ｎｉ層およびＡｕ層を順
次積層して成る三層構造の金属電極によりオーミック接
触形成し、その三層構造の金属電極をアロイ処理し、し
かる後、前記ショットキ接合のゲート電極、前記三層構
造のソースおよびドレイン電極を被うように前記ＡｕＧ
ｅ層の共晶温度付近あるいはそれ以上の温度の熱処理の
ともなった気相化学成長によるパッシベーション膜を形
成することを特徴とするＧａＡｓ電界効果トランジスタ
の製法にある。The present invention for achieving the above object is a mesa-type GaAs in which a source electrode, a gate electrode and a drain electrode are arranged close to each other on a main surface of a GaAs epitaxial layer having a (100) crystal plane and along a predetermined length direction. A method of manufacturing a field effect transistor, wherein each electrode has a predetermined length direction of [011], [01], [0], [0].
1) along one direction, the gate electrode is formed of a metal electrode that forms a Schottky junction with the main surface, and the source electrode and the drain electrode are formed on the main surface with an AuGe layer and a Ni layer, respectively. And Au layers are sequentially laminated to form an ohmic contact with a metal electrode having a three-layer structure, the metal electrode having the three-layer structure is alloyed, and then the gate electrode having the Schottky junction, the source having the three-layer structure, and The AuG so as to cover the drain electrode
A method of manufacturing a GaAs field effect transistor is characterized in that a passivation film is formed by vapor phase chemical growth accompanied by heat treatment at a temperature near or above the eutectic temperature of the e layer.
以下、実施例により本発明を説明する。Hereinafter, the present invention will be described with reference to examples.
第４図は本発明の一実施例によるGaAs−ＳＢＧＦＥＴ素
子の要部を示す平面図、第５図は第４図のＶ−Ｖ線に沿
う断面図、第６図は第４図のVI−VI線に沿う断面図であ
る。第７図(a)，(b)は本発明には適用しない好ましくな
い電極パターンを示す説明図、第８図(a)，(b)は本発明
に適用する好ましい電極パターンを示す説明図である。
また、第９図は(a)〜(c)は、素子の製造方法を各工程で
の断面図である。FIG. 4 is a plan view showing an essential part of a GaAs-SBGFET device according to an embodiment of the present invention, FIG. 5 is a sectional view taken along the line VV in FIG. 4, and FIG. 6 is VI- in FIG. It is sectional drawing which follows the VI line. 7 (a) and 7 (b) are explanatory views showing undesired electrode patterns not applicable to the present invention, and FIGS. 8 (a) and 8 (b) are explanatory views showing preferred electrode patterns applied to the present invention. is there.
Further, FIGS. 9A to 9C are cross-sectional views in each step of the method for manufacturing an element.
この実施例のGaAs−ＳＢＧＦＥＴ素子は、第４図および
第５図で示すように、ソース電極（Ｓ）４とドレイン電
極（Ｄ）５との間に、第１ゲート電極９および第２ゲー
ト電極１０からなる２本のゲート電極（Ｇ）を設けた、
いわゆるデユアルゲート構造となつている。なお、第４
図ではパツシベーシヨン膜は省略してある。したがつ
て、各電極のボンデイングパツド領域１１は二点鎖線枠
で示してある。As shown in FIGS. 4 and 5, the GaAs-SBGFET device of this embodiment has a first gate electrode 9 and a second gate electrode between a source electrode (S) 4 and a drain electrode (D) 5. Two gate electrodes (G) of 10 are provided,
It has a so-called dual gate structure. The fourth
In the figure, the passivation film is omitted. Therefore, the bonding pad area 11 of each electrode is shown by a chain double-dashed line frame.
素子１２は第５図で示すように、Ｃｒをドープして半絶
縁体となつた厚さ３５０〜４００μｍのGaAs基板１上に
GaAs層からなる厚さ２．３μｍのバツフア層２を介して
形成したｎ形エピタキシヤル層３（厚さ０．３μｍ、ド
ナー濃度約１０17cm-3）上に各電極を配している。ｎ形
エピタキシヤル層３は能動層となるとともに、アイソレ
ーシヨンのために周囲は必要なパターンにエッチング除
去されてメサ構造となつている。また、このｎ形エピタ
キシヤル層３の主面、すなわちGaAs基板１の主面はあら
かじめ（１００）なる結晶面となるようにしておく。The element 12 is, as shown in FIG. 5, formed on a GaAs substrate 1 having a thickness of 350 to 400 μm which is doped with Cr to form a semi-insulator.
Each electrode is arranged on an n-type epitaxial layer 3 (thickness: 0.3 μm, donor concentration: about 10 17 cm −3 ) formed through a buffer layer 2 having a thickness of 2.3 μm and formed of a GaAs layer. The n-type epitaxial layer 3 serves as an active layer, and the periphery thereof is etched away into a required pattern for isolation to form a mesa structure. The main surface of the n-type epitaxial layer 3, that is, the main surface of the GaAs substrate 1 is made to be a (100) crystal plane in advance.
一方、ｎ形エピタキシヤル層３の主面中央には１μｍ〜
１．５μｍの長さの２本のゲート電極が平行（間隔１μ
ｍ）に配設されている。２本のゲート電極はそれぞれ第
１ゲート電極９および第２ゲート電極１０を形作つてい
る。また、２本のゲート電極を挾んで別々にソース電極
４およびドレイン電極５が配設されている。ソース電極
４と第１ゲート電極９との間隔は１．５μｍ，第２ゲー
ト電極１０とドレイン電極５との間隔は２μｍとなつて
いる。On the other hand, in the center of the main surface of the n-type epitaxial layer 3, 1 μm to
Two gate electrodes with a length of 1.5 μm are parallel (space 1 μm
m). The two gate electrodes form a first gate electrode 9 and a second gate electrode 10, respectively. In addition, the source electrode 4 and the drain electrode 5 are separately arranged across the two gate electrodes. The distance between the source electrode 4 and the first gate electrode 9 is 1.5 μm, and the distance between the second gate electrode 10 and the drain electrode 5 is 2 μm.
ゲート電極は厚さ6000Å程度のアルミニウムによつて形
成され、シヨツトキ障壁接合となつている。また、ソー
ス・ドレイン電極４，５は最下層の1300Åの厚さのAuGe
層，中層の厚さ300 ÅのＮｉ層，上層の厚さ4500ÅのＡ
ｕ層からなる三層構造となるとともに、電極形成後の４
００℃前後、５分のアロイ処理によつてオーミツク接合
化が図られている。The gate electrode is made of aluminum with a thickness of about 6000Å, forming a shutter barrier junction. The source / drain electrodes 4 and 5 are AuGe with a thickness of 1300Å in the bottom layer.
Layer, middle layer is 300 Å Ni layer, upper layer is 4500 Å A
It has a three-layer structure composed of u layers, and 4
Ohmic bonding is achieved by alloying at around 00 ° C. for 5 minutes.
一方、第１ゲート電極９および第２ゲート電極１０の一
端はｎ形エピタキシヤル層３から外れて、バツフア層２
上に延在している。この際、メサ部の段差部分上を延在
するため、アルミニウムの配線層の幅は徐々に広くなつ
てゲート長さよりも広い幅となつた状態で交差し、かつ
第６図で示すように、徐々に低くなる順メサ部分を通る
ようになつている。なお、各電極を設けたｎ形エピタキ
シヤル層３以外の表面およびバツフア層２上には絶縁膜
１３が設けられるとともに、各電極のボンデイングパツ
ド領域１１以外の素子表面はパツシベーシヨン膜１４で
被われている。On the other hand, one ends of the first gate electrode 9 and the second gate electrode 10 are separated from the n-type epitaxial layer 3, and the buffer layer 2
It extends over. At this time, since it extends over the stepped portion of the mesa portion, the width of the aluminum wiring layer gradually widens and intersects with the width wider than the gate length, and as shown in FIG. It goes through the mesa part which is gradually lowered. An insulating film 13 is provided on the surface other than the n-type epitaxial layer 3 on which each electrode is provided and on the buffer layer 2, and the device surface other than the bonding pad region 11 of each electrode is covered with a passivation film 14. ing.
ここで、各電極の隣接方向、すなわちチヤネル方向であ
りかつ各電極の近接方向である方向は、第８図(b)で示
すように、〔０１１〕方向となつている。したがつて、
第１ゲート電極９および第２ゲート電極１０の延在する
方向は、前記パツシベーシヨン膜１４（４１０℃，４０
分処理によるＣＶＤ−ＰＳＱ膜）の形成の際、電極成分
の横方向のアロイの進行がほとんどない〔０１１〕，
〔０〕方向となつている。すなわち、本発明者の発
見によつて、第３図に示すように、（１００）における
電極材料とGaAs母材間のアロイ成長は〔０１０〕および
これに等価な〔００〕方向、ならびに〔００１〕およ
びこれに等価な〔００〕方向で大きく、〔０１１〕お
よび〔０〕方向では成長はほとんど起こらず〔０
〕およびこれに等価な〔０１〕方方向ではわずかに
アロイ進行部が現われることが確認されている。そこ
で、この実施例では、第８図(a)で示すように、隣接す
る電極方向はアロイ成長がわずかしか生じない結晶方
向、あるいは第８図(b)で示すように、アロイ成長がほ
とんど生じない結晶方向とすることによつて、電極形成
後にＡｕとＧｅの共晶温度３５６℃よりも高い温度でパ
ツシベーシヨンを行なつても隣接する電極のシヨートあ
るいは耐圧劣化が生じないようにしている。なお、第７
図(a)，(b)はアロイ進行によつて隣接する電極の耐圧劣
化やシヨートが生じ易い好ましくない電極パターン例を
示すものである。第７図(a)，(b)および第８図(a)，(b)
はシングルゲート構造を例にして説明しているが、ゲー
ト電極が２本となるデユアルゲート構造でも同様であ
る。Here, the adjoining direction of each electrode, that is, the channel direction and the approaching direction of each electrode is the [011] direction as shown in FIG. 8B. Therefore,
The extending direction of the first gate electrode 9 and the second gate electrode 10 is defined by the passivation film 14 (410 ° C., 40 ° C.).
When a CVD-PSQ film is formed by a splitting process, there is almost no lateral alloying of electrode components [011],
The direction is [0]. That is, according to the findings of the present inventor, as shown in FIG. 3, the alloy growth between the electrode material and the GaAs base material in (100) is [010] and the equivalent [00] direction, and [001]. ] And its equivalent in the [00] direction, and almost no growth occurs in the [011] and [0] directions.
] And the equivalent [01] direction, it is confirmed that an alloy progress portion appears slightly. Therefore, in this embodiment, as shown in FIG. 8 (a), the adjacent electrode direction has a crystallographic direction in which alloy growth hardly occurs, or as shown in FIG. 8 (b), almost alloy growth does not occur. By adopting the non-crystallizing direction, even if the passivation is performed at a temperature higher than the eutectic temperature of Au and Ge of 356 ° C. after the electrodes are formed, short-circuiting of the adjacent electrodes or deterioration of withstand voltage does not occur. The seventh
Figures (a) and (b) show examples of unfavorable electrode patterns in which deterioration of breakdown voltage of adjacent electrodes and shorts are likely to occur due to progress of alloying. 7 (a), (b) and 8 (a), (b)
In the above description, a single gate structure is taken as an example, but the same applies to a dual gate structure having two gate electrodes.
また、ここで第９図(a)〜(c)を参照しながら前記素子１
２の製断方法について簡単に説明する。まず、GaAs基板
１を用意して順次GaAsからなるバツフア層２およびｎ形
エピタキシヤル層３を形成する。GaAs基板１はＣｒがド
ープされて絶縁体となつていて、たとえば350〜400μｍ
の厚さとなつている。バツフア層２は２．３μｍとな
り、Ｃｒのｎ形エピタキシヤル層３への侵入を防止する
役割を果す。ｎ形エピタキシヤル層３はイオウ（Ｓ）あ
るいはセレン（Ｓｅ）を約１０17cm-3の濃度にドープし
てｎ形のGaAs層とし、厚さは０．３μｍと極めて薄い。Also, referring to FIGS. 9 (a) to 9 (c), the element 1
The cutting method 2 will be briefly described. First, a GaAs substrate 1 is prepared, and a buffer layer 2 and an n-type epitaxial layer 3 made of GaAs are sequentially formed. The GaAs substrate 1 is doped with Cr to serve as an insulator, for example, 350 to 400 μm.
The thickness of The buffer layer 2 has a thickness of 2.3 μm and plays a role of preventing Cr from entering the n-type epitaxial layer 3. The n-type epitaxial layer 3 is doped with sulfur (S) or selenium (Se) to a concentration of about 10 17 cm -3 to form an n-type GaAs layer, and the thickness is 0.3 μm, which is extremely thin.
つぎに、同図(b)に示すように、能動層となるｎ形エピ
タキシヤル層３のアイソレーシヨンのために、ｎ形エピ
タキシヤル層３の周囲を所望のパターンにエツチング除
去してメサ構造とする。その後、常用の蒸着技術によつ
てAuGe／Ｎｉ／Ａｕからなるソース電極４およびドレイ
ン電極５を前述のパターン通りに形成し、オーミツクを
得るためにアロイ処理（４００℃，５分処理）を行な
う。Next, as shown in FIG. 3B, for isolation of the n-type epitaxial layer 3 serving as an active layer, the periphery of the n-type epitaxial layer 3 is etched and removed into a desired pattern to form a mesa structure. And After that, the source electrode 4 and the drain electrode 5 made of AuGe / Ni / Au are formed according to the above-mentioned pattern by a conventional vapor deposition technique, and an alloy treatment (400 ° C., 5 minutes treatment) is performed to obtain an ohmic property.
つぎに、常用の部分蒸着技術によつて前述のパターン通
りにアルミニウムを取り付けてシヨツトキ障壁接合のゲ
ート電極６を形成する。さらに、素子の表面をＣＶＤ−
ＰＳＧ膜（気相化学成長によるリンシリケートガラス
膜）を所望厚さに形成する。この際、所望部分はＣＶＤ
−ＰＳＧ膜（パツシベーシヨン膜）で被われないことに
よつてワイヤ接続用のボンデイングパツド領域１１を形
成して、素子１２を得る。Next, aluminum is attached according to the above-described pattern by a conventional partial vapor deposition technique to form a gate electrode 6 having a shutter barrier junction. Furthermore, the surface of the device is CVD-
A PSG film (phosphorus silicate glass film by vapor phase chemical growth) is formed to a desired thickness. At this time, the desired portion is CVD
A bonding pad region 11 for wire connection is formed by being not covered with a -PSG film (passivation film) to obtain a device 12.
このような実施例によれば、GaAs−ＳＢＧＦＥＴのパツ
シベーシヨン時の熱による特性劣化は大幅に緩和するこ
とができる。また、量産化に伴いペレツト付け，モール
ド，その他の工程に伴う熱処理温度および回数が増加す
るが、これらの熱による特性劣化も同様に緩和すること
ができる。したがつて、信頼性の向上および歩留の向上
を図ることができることから量産化も可能となる。According to such an embodiment, the characteristic deterioration due to heat during the passivation of the GaAs-SBGFET can be remarkably alleviated. In addition, although the heat treatment temperature and the number of times associated with pelletization, molding, and other steps increase with mass production, the characteristic deterioration due to these heats can be similarly mitigated. Therefore, since the reliability and the yield can be improved, the mass production is possible.
また、本発明はｐ形GaAs能動層の場合にも同様に適用で
きる。Further, the present invention can be similarly applied to the case of the p-type GaAs active layer.
また、本発明は第１０図に示すように、アイソプレーナ
構造のＩＣにも適用できる。すなわち、ｎ形エピタキシ
ヤル層３を絶縁膜１５で区割して独立した能動領域１６
を形成し、それぞれの能動領域１６に所望の素子を形成
し、かつ平坦な上面上を利用して各素子を配線層１７で
結線して所望のＩＣを形成する。この実施例ではGaAs−
ＳＢＧＦＥＴ１８とシヨツトキ障壁ダイオード１９を結
線した例を示す。Further, the present invention can be applied to an IC having an isoplanar structure as shown in FIG. That is, the n-type epitaxial layer 3 is divided by the insulating film 15 and the independent active region 16 is formed.
Then, a desired element is formed in each active region 16, and each element is connected by the wiring layer 17 using the flat upper surface to form a desired IC. In this embodiment, GaAs-
An example in which the SBGFET 18 and the shutter barrier diode 19 are connected is shown.
このような実施例では、ゲートの引出部分をメサ構造の
ように段差による断線を防止する目的で太くする必要も
なく、ゲート電極と同一の長さで引き出すことができる
ため、寄生容量の軽減化が図れる利点がある。In such an embodiment, unlike the mesa structure, it is not necessary to thicken the lead-out portion of the gate in order to prevent disconnection due to a step, and the lead-out portion can be drawn out with the same length as the gate electrode, so that the parasitic capacitance can be reduced. There is an advantage that can be achieved.
前記絶縁膜１５はＡｌ2Ｏ3，ＳｉＯ2，Ｓｉ3Ｎ4等の選
択酸化による方法で形成してもよい。The insulating film 15 may be formed by a method of selective oxidation of Al 2 O 3 , SiO 2 , Si 3 N 4 or the like.
また、第１１図に示すように、Ｈ＋，Ｎａ等をイオンイ
ンプランテーシヨン法で打ち込んで高抵抗層，絶縁物層
等のアイソレーシヨン領域２０を形成してもよい。ま
た、このアイソレーシヨン領域２０は１０７Ωcmと高抵
抗のGaAsを部分的に成長（たとえば部分エピタキシヤル
法）させるようにして形成してもよい。Further, as shown in FIG. 11, H + , Na or the like may be implanted by an ion implantation method to form an isolation region 20 such as a high resistance layer or an insulating layer. The isolation region 20 may be formed by partially growing GaAs having a high resistance of 10 7 Ωcm (for example, partial epitaxial method).
また、第１２図で示すように、Ｃｒをドープした半絶縁
性GaAs基板１に部分的に不純物をドープして独立した能
動領域２１を形成してもよい。この場合、イオウ
（Ｓ），セレン（Ｓｅ）をドープすればｎ形となり、亜
鉛（Ｚｕ）をドープすればｐ形となる。上述した如きメ
サエツチングによるアイソレーションを用いない、アイ
ソプレーナー構造GaAsＩＣにおいては、エツチ段差部に
おける電極の段切れ等の心配がなくなり、電極レイアウ
トはまつたく自由に行なうことができるが、これらに本
発明を適用することにより耐圧不良等を防止しえるレイ
アウトパターンを有したすぐれたＩＣを提供することが
可能となる。Further, as shown in FIG. 12, the semi-insulating GaAs substrate 1 doped with Cr may be partially doped with impurities to form an independent active region 21. In this case, doping with sulfur (S) or selenium (Se) results in n-type, and doping with zinc (Zu) results in p-type. In an isoplanar structure GaAs IC that does not use isolation by mesa etching as described above, there is no concern about electrode breakage at the etching step and the electrode layout can be performed freely. By applying it, it becomes possible to provide an excellent IC having a layout pattern capable of preventing a breakdown voltage defect or the like.
以上のように、本発明によれば、熱処理によるアロイ進
行に起因する特性劣化を防止することができるので、高
信頼度，高歩留のGaAs半導体装置を製造することができ
るため、コストの低減が図れ、量産化が可能となる。As described above, according to the present invention, it is possible to prevent the characteristic deterioration due to the progress of alloying due to the heat treatment, so that it is possible to manufacture a GaAs semiconductor device with high reliability and high yield, and thus to reduce the cost. And can be mass-produced.
第１図は従来のGaAs−ＳＢＧＦＥＴ素子の断面を示す断
面図、 第２図は同じく素子表面の結晶方向を示す説明図、 第３図は同じくアロイ成長状態を示す説明図、 第４図は本発明の一実施例によるGaAs−ＳＢＧＦＥＴ素
子を示す平面図、 第５図は第４図のＶ−Ｖ線に沿う一部の拡大断面図、 第６図は第４図のVI−VI線に沿う一部の拡大断面図、 第７図(a)，(b)は好ましくない電極パターンを示す説明
図、 第８図(a)，(b)は好ましい電極パターンをを示す説明
図、 第９図(a)〜(c)は本発明によるGaAs−ＳＢＧＦＥＴ素子
の製造方法を示す各工程における断面図、 第１０図は他の実施例によるGaAs−ＳＢＧＦＥＴを組み
込んだ素子の断面図、 第１１図はアイソレーシヨン方法を示す断面図、 第１２図は他のアイソレーシヨン方法を示す断面図であ
る。 １……GaAs基板、２……バツフア層、３……ｎ形エピタ
キシヤル層、４……ソース電極、５……ドレイン電極、
６……ゲート電極、７……電極、８……アロイ成長部、
９……第１ゲート電極、１０……第２ゲート電極、１２
……素子、１４……パツシベーシヨン膜、１５……絶縁
膜、１６，２１……能動領域、１７……配線層、１８…
…GaAs−ＳＢＧＦＥＴ、１９……ダイオード、２０……
アイソレーシヨン領域、，，……アロイ成長部。FIG. 1 is a sectional view showing a section of a conventional GaAs-SBGFET device, FIG. 2 is an explanatory view showing the crystal direction of the device surface, FIG. 3 is an explanatory view showing an alloy growth state, and FIG. FIG. 5 is a plan view showing a GaAs-SBGFET device according to an embodiment of the invention, FIG. 5 is a partially enlarged sectional view taken along line VV of FIG. 4, and FIG. 6 is taken along line VI-VI of FIG. Partial enlarged sectional views, FIGS. 7 (a) and (b) are explanatory views showing an unfavorable electrode pattern, FIGS. 8 (a) and (b) are explanatory views showing a preferable electrode pattern, and FIG. (a) to (c) are cross-sectional views in each step showing the method of manufacturing a GaAs-SBGFET device according to the present invention, FIG. 10 is a cross-sectional view of a device incorporating a GaAs-SBGFET according to another embodiment, and FIG. FIG. 12 is a cross-sectional view showing an isolation method, and FIG. 12 is a cross-sectional view showing another isolation method. 1 ... GaAs substrate, 2 ... buffer layer, 3 ... n-type epitaxial layer, 4 ... source electrode, 5 ... drain electrode,
6 ... Gate electrode, 7 ... Electrode, 8 ... Alloy growth part,
9 ... First gate electrode, 10 ... Second gate electrode, 12
...... Element, 14 ...... passivation film, 15 ...... insulating film, 16, 21 ...... active region, 17 ...... wiring layer, 18 ...
... GaAs-SBGFET, 19 ... Diode, 20 ...
Isolation area, ... Alloy growth section.
Claims (1)
シャル層主面に互いに近接し、所定長さ方向に沿うソー
ス電極、ゲート電極およびドレイン電極が配列されたメ
サ型のＧａＡｓ電界効果トランジスタの製法であって、
前記それぞれの電極の所定長さ方向が〔０１１〕、〔０
１〕、〔０〕、〔０１〕のいずれか一つの方向
に沿い、前記ゲート電極を前記主面に対してショットキ
接合を成す金属電極により形成し、前記ソース電極およ
びドレイン電極をそれぞれ前記主面に対してＡｕＧｅ
層、Ｎｉ層およびＡｕ層を順次積層して成る三層構造の
金属電極によりオーミック接触形成し、その三層構造の
金属電極をアロイ処理し、しかる後、前記ショットキ接
合のゲート電極、前記三層構造のソースおよびドレイン
電極を被うように前記ＡｕＧｅ層の共晶温度付近あるい
はそれ以上の温度の熱処理のともなった気相化学成長に
よるパッシベーション膜を形成することを特徴とするＧ
ａＡｓ電界効果トランジスタの製法。1. A method of manufacturing a mesa-type GaAs field effect transistor in which a source electrode, a gate electrode and a drain electrode are arranged close to each other on a main surface of a GaAs epitaxial layer having a (100) crystal plane and along a predetermined length direction. There
The predetermined length direction of each of the electrodes is [011], [0
1], [0], or [01] along one direction, the gate electrode is formed of a metal electrode forming a Schottky junction with the main surface, and the source electrode and the drain electrode are respectively formed on the main surface. Against AuGe
Layer, Ni layer and Au layer are sequentially laminated to form ohmic contact with a metal electrode having a three-layer structure, the metal electrode having the three-layer structure is alloyed, and then the gate electrode of the Schottky junction and the three layers are formed. A passivation film is formed by vapor phase chemical growth accompanied by heat treatment at a temperature near or above the eutectic temperature of the AuGe layer so as to cover the source and drain electrodes of the structure G
aAs Field effect transistor manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57131954A JPH0618216B2 (en) | 1982-07-30 | 1982-07-30 | Manufacturing method of GaAs field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57131954A JPH0618216B2 (en) | 1982-07-30 | 1982-07-30 | Manufacturing method of GaAs field effect transistor |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7186832A Division JP2555871B2 (en) | 1995-07-24 | 1995-07-24 | Gallium arsenide semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5923566A JPS5923566A (en) | 1984-02-07 |
| JPH0618216B2 true JPH0618216B2 (en) | 1994-03-09 |
Family
ID=15070089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57131954A Expired - Lifetime JPH0618216B2 (en) | 1982-07-30 | 1982-07-30 | Manufacturing method of GaAs field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618216B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008177511A (en) * | 2007-01-22 | 2008-07-31 | Mitsubishi Electric Corp | Field effect transistor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0341462Y2 (en) * | 1985-03-28 | 1991-08-30 |
-
1982
- 1982-07-30 JP JP57131954A patent/JPH0618216B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．３７［３（１９８０−８−１）ＰＰ．３１１〜３１３ |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008177511A (en) * | 2007-01-22 | 2008-07-31 | Mitsubishi Electric Corp | Field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5923566A (en) | 1984-02-07 |
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