JPH06181475A - Orthogonal demodulation circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration of an anti-aliasing filter and to prevent deterioration in a code error ratio when a frequency difference is large by setting a sampling frequency of a digital signal to be high. CONSTITUTION:Analog low pass filters 15,16 and digital low pass filters 19,20 are used to eliminate a high frequency component being a half of a frequency fs or over equal to that of a conventional circuit and the frequency characteristic of the analog low pass filters 15,16 is enough to have a gentle slope in comparison with that of conventional filters. Thus, the circuit of the analog low pass filters 15,16 is simplified because of less number of filter stages. Speed conversion circuits 21,22 are made up of, e.g., two D flip-flop circuits, interleave a digital signal whose sampling frequency is 2fs to a data input terminal and the clock frequency is subject to speed conversion to the frequency fs and it is extracted. Then a phase rotation circuit 25 cancels the phase rotation of the input digital signals and a code error ratio is not deteriorated even when a frequency difference between the input digital modulation signal and a demodulation use carrier is high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature demodulation circuit, and more particularly to a quadrature demodulation circuit for obtaining two demodulation baseband signals of a quadrature signal (Q signal) and an in-phase signal (I signal) by a quasi-coherent detection method.

A frequency shift keying (FSK) system, a phase shift keying (PSK) system, a quadrature amplitude modulation (QAM) system and the like are used as a modulation system of a digital signal. This is because the code error rate and the transmission capacity are more advantageous than other modulation methods. In a quadrature demodulation circuit that demodulates a digitally modulated wave modulated by such a modulation method by a quasi-coherent detection method, simplification of the filter configuration and the like is desired.

[0003]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional quadrature demodulation circuit. In the figure, the digital modulated wave signals input to the input terminal 10 and modulated by, for example, the QAM method are supplied to multipliers 11 and 12, respectively, where they are obtained by an oscillator 13 and a π / 2 phase shifter 14. It is multiplied by two demodulation carriers having mutually orthogonal phases.

The carrier wave for demodulation, which is the oscillation frequency of the oscillator 13, is a fixed frequency close to the carrier wave of the input digital modulated wave signal, and the two analog baseband signals having the difference frequency between them are outputted from the multipliers 11 and 12. It is taken out as a demodulated signal. The analog baseband signal obtained by demodulation is supplied to the A / D converters 43 and 44 through the low-pass filters 41 and 42 of the analog circuit and is analog-digital converted.

The low-pass filters 41 and 42 are used for the subsequent A / D.
An analog filter circuit that removes a frequency that is 1/2 times the clock frequency (sampling frequency) f _S of the converters 43 and 44, and aliasing noise is generated in the output digital signals of the A / D converters 43 and 44. The filter circuit is a so-called anti-aliasing filter provided so as not to be included.

The digital signals of the sampling frequency f _{S which} are separately taken out from the A / D converters 43 and 44 are supplied to the phase rotation circuit 25 after the unnecessary high frequency components are removed by the digital low pass filters 23 and 24. The digital low-pass filters 23 and 24 are roll-off filters that give a roll-off characteristic to an input digital signal, and output an I signal and a Q signal, respectively.

In the phase rotation circuit 25, the phase error signal obtained by comparing the output signal with the comparator 26 is used as the loop filter 2
Controlled oscillator (V
Based on the oscillation frequency from the (CO) 28, the input I and Q signals are phase-rotated in a direction to eliminate the rotation of the signal points in the signal space, and output to the output terminals 29 and 30 demodulated signals of the I and Q signals. Is output.

In this way, the quadrature demodulation circuit of the quasi-coherent detection system which demodulates the digital modulated wave signal without reproducing the carrier wave is suitable for large-scale semiconductor integrated circuit (LSI).

[0009]

However, in the above-described conventional quadrature demodulation circuit, when performing quasi-synchronous detection, a multiplier is used according to the frequency difference between the carrier wave of the input digital modulated wave and the output oscillation frequency of the oscillator 13. Since the output baseband signals of 11 and 12 cause phase rotation, if the frequency difference is large, a digital low-pass filter (roll-off filter)
With 45 and 46, the required attenuation rate cannot be obtained and the code error rate of the demodulated data is deteriorated.

Further, the anti-aliasing filter 41
And 42, the cut-off frequency f _S / 2 is close to the upper limit frequency of the baseband signal, so that a low-pass filter characteristic having a steep slope is required, which complicates the circuit configuration of the anti-aliasing filters 41 and 42. There is also a problem.

The present invention has been made in view of the above points,
An object of the present invention is to provide a quadrature demodulation circuit that solves the above problems by setting the sampling frequency of a digital signal high.

[0012]

A quadrature demodulation circuit of the present invention is for removing aliasing noise for removing high frequency components from first and second analog signals obtained by quasi-coherent detection of an input digital modulated wave signal. A / through the analog filter of
Analog / digital conversion is performed by the D converter. The sampling frequency of this analog-to-digital converter is a second sampling frequency higher than the existing first sampling frequency.

The output digital signal of the A / D converter is subjected to removal of high frequency components by the first and second digital filters, then converted to the first sampling frequency by the speed conversion circuit, and further phase rotated by the output circuit. The signal is either canceled and output as demodulated data, or the phase rotation is canceled and the high frequency component is removed by the digital filter, and then the output circuit performs speed conversion and waveform shaping to output demodulated data. It

[0014]

In the present invention, since the sampling frequency of the A / D converter is higher than the existing first sampling frequency, A
As the above-mentioned analog filter provided in the input stage of the / D converter, one having a low-pass filter characteristic having a gentler slope than the conventional analog filter can be used.

The digital filter provided at the output stage of the A / D converter causes the output digital signal of the A / D converter to be at least 1 / the first sampling frequency.
After the high frequency component more than double the frequency is removed, the speed conversion circuit or the output circuit performs the speed conversion and the sampling frequency is converted to the first sampling frequency. Therefore, the aliasing noise caused by the speed conversion is generated. And the waveform can be shaped at the same sampling frequency as the conventional one.

According to the second aspect of the invention, the digital signal can be input to the waveform shaping filter after removing the phase rotation.

[0017]

1 shows a block diagram of a first embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. In FIG. 1, multipliers 11 and 12
The quasi-coherently detected first and second analog baseband signals extracted by the analog low-pass filters 15 and 16 have their high-frequency components removed, and then the A / D converter 17
And 18 respectively.

The above analog low pass filters 15 and 16
Is the sampling frequency of the A / D converters 17 and 18
Existing sampling frequency f_SHigher frequencies, eg
2f _SIs set to A / D converters 17 and 1
No aliasing noise is included in the output digital signal of 8
Set anti-aliasing
It's a filter.

The digital signals with sampling frequencies of 2f _S extracted by the A / D converters 17 and 18, respectively, have their high frequency components above the folding frequency removed by the digital low-pass filters 19 and 20, and then the speed conversion circuit 2
1, 22 are supplied.

[0020] For digital low pass filter 19 and 20 to the sampling frequency by a subsequent speed converting circuit 21 and 22 are converted to the same f _S a conventional, speed conversion circuit 2
This is an anti-aliasing filter that is set so that aliasing noise is not desired in the output digital signals of 1 and 22.

That is, according to this embodiment, the analog low-pass filters 15 and 16 and the digital low-pass filter 19 are used.
And 20 remove high-frequency components of the same frequency f _S / 2 or more as in the conventional case, and the analog low-pass filter 15
The frequency characteristics of 16 and 16 are as shown by the solid line I in FIG. 2, and the characteristics may have a gentler slope than the frequency characteristics of the conventional analog low-pass filters 41 and 42 (shown by the broken line II in FIG. 2).

Therefore, the circuits of the analog low-pass filters 15 and 16 are the same as the conventional analog low-pass filters 41 and 42.
The number of filter stages is smaller than that of the above, and the configuration can be simplified. The digital low-pass filters 19 and 20 have the same frequency characteristics as shown by the broken line II in FIG.

The speed conversion circuits 21 and 22 are provided in order to obtain a digital signal of the same sampling frequency f _S as in the conventional case, so as not to increase the processing speed of the digital low-pass filters 23 and 24 in the next stage as compared with the conventional case. For example, in FIG.
As shown in FIG. 2, two D-type flip-flops 51 and 52 are provided.
It is composed by.

In FIG. 3, a D-type flip-flop 51 is provided.
The output digital signals of the digital low-pass filters 19 and 20 are input to the data input terminal of and the first clock pulse of the frequency 2f _S is applied to the clock terminal, so that the Q output of the D-type flip-flop 51 is output. The input digital signal latched by the first clock pulse is taken out from the terminal and applied to the data input terminal of the D-type flip-flop 52.

The D-type flip-flop 52 latches this input digital signal by the second clock pulse of the frequency f _S and outputs it. That is, from the Q output terminal of the D-type flip-flop 52, the digital signal of the sampling frequency 2f _S to the data input terminal of the D-type flip-flop 51 is thinned out and the digital signal converted to the sampling frequency f _S is taken out.

The digital low-pass filters 23 and 24 shown in FIG. 1 to which the speed-converted digital signal is input are roll-off filters that perform waveform shaping, and remove unnecessary high-frequency components. The phase rotation circuit 25 includes the comparator 26, the low pass filter 27, and the VCO as described with reference to FIG.
Together with 28 cancels out the phase rotation of the input digital signal.

FIG. 4 shows a block diagram of the second embodiment of the present invention. In the figure, the same components as those in FIGS. 1 and 5 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 4, A / D
The output digital signals of the converters 17 and 18 are supplied to the phase rotation circuit 31.

The phase rotation circuit 31 compares the phase difference between the output demodulated data of the two channels, and the output error signal of the comparator 38 is fed through the loop filter 39 as a control code from the VCO 40. The frequency is fed back in accordance with the frequency error. The phase rotation of the input digital signal is canceled out based on the controlled oscillation frequency. The phase rotating circuit 31 has the same configuration as the phase rotating circuit 25, but differs from the phase rotating circuit 25 in that it operates at twice the speed.

The output digital signal of the phase rotation circuit 31 has its high frequency components above the folding frequency f _S / 2 removed by the digital low-pass filters 32 and 33, respectively, and then the sampling frequency is changed from 2 f _S by the speed conversion circuits 34 and 35. is converted into f _S is taken out. Speed conversion circuit 33, 3
The output digital signal 5 is waveform-shaped by digital low-pass filters 36 and 37 called roll-off filters, and then output to output terminals 29 and 30 as demodulated data of I and Q signals, while comparator 38 Is input to.

According to this embodiment, the roll-off filter 3
Since the phase rotation circuit 31 cancels and removes the phase rotation from the digital signal before being input to 6, 37, even if the frequency difference between the input digital modulated wave signal and the output oscillation frequency of the oscillator 13 is large. After removing the influence of the frequency difference, the digital signal can be input to the roll-off filters 36 and 37. Therefore, according to the present embodiment, it is possible to prevent deterioration of the code error rate even if the frequency difference is large.

In the present invention, demodulated data can be obtained by the same method for a digital signal modulated by the FSK system or the PSK system. A demodulated signal is extracted from the input side of the VCOs 28 and 40 for the FSK modulated digital signal.

[0032]

As described above, according to the first aspect of the invention, since the slope of the frequency characteristic of the analog filter on the input side of the A / D converter can be made gentler than before, the processing of the roll-off filter is performed. The analog filter, which is an anti-aliasing filter, can have a simple circuit configuration without increasing the speed, and according to the second aspect of the invention, phase rotation is performed on the input digital signal of the roll-off filter. Since it is removed, even if the frequency difference between the input digital modulated wave signal and the demodulation carrier from the quasi-synchronous detection oscillator is large, it is possible to demodulate without degrading the code error rate. Is.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating characteristics of a filter.

FIG. 3 is a circuit diagram of an example of a speed conversion circuit.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of a conventional example.

[Explanation of symbols]

11, 12 Multiplier 13 Oscillator 15, 16 Analog low-pass filter (anti-aliasing filter) 17, 18 A / D converter 19, 20, 32, 33 Digital low-pass filter (anti-aliasing filter) 21, 22, 34, 35 Speed conversion circuit 23, 24, 36, 37 Digital low-pass filter (roll-off filter) 25, 31 Phase rotation circuit 28, 40 Voltage controlled oscillator (VCO)

Claims (2)

[Claims] 1. The input digital modulated wave signals are mutually separated by 9
The detection means (11-14) for quasi-coherent detection using two demodulation carrier waves having fixed frequencies having different 0 ° phases to obtain the first and second analog signals, and the detection means (11-14) The first and second analog filters (15, 16) for removing aliasing noise for removing high frequency components of the first and second analog signals, and the first and second analog filters (15, 16) First and second A / D for performing analog-digital conversion on each output analog signal at a second sampling frequency higher than the existing first sampling frequency
A converter (17, 18) and at least a frequency that is at least 1/2 times the first sampling frequency in the output digital signals of the first and second A / D converters (17, 18) The first and second digital filters (19, 20) for removing high frequency components, and the sampling frequency of each output digital signal of the first and second digital filters (19, 20) are set to the first
Speed conversion circuit (21,
22) and an output circuit (23 to 28) for obtaining demodulated data by canceling phase rotation after waveform shaping of the output digital signals of the speed converting circuits (21, 22). . 2. The input digital modulated wave signals are separated from each other by 9
The detection means (11-14) for quasi-coherent detection using two demodulation carrier waves having fixed frequencies having different 0 ° phases to obtain the first and second analog signals, and the detection means (11-14) The first and second analog filters (15, 16) for removing aliasing noise for removing high frequency components of the first and second analog signals, and the first and second analog filters (15, 16) First and second A / D for performing analog-digital conversion on each output analog signal at a second sampling frequency higher than the existing first sampling frequency
A converter (17, 18), a phase rotation means (31, 38-40) for canceling and eliminating the phase rotation of each output digital signal of the first and second A / D converters (17, 18), At least the first sampling frequency in the output digital signal of the phase rotation means (31, 38-40)
First and second digital filters (32, 33) for removing high frequency components equal to or more than 1/2 times the frequency, and sampling of each output digital signal of the first and second digital filters (32, 33) Frequency is the first
An output circuit (34 to 37) for converting the sampling frequency to the waveform and shaping and outputting the demodulated data.