JP2000068839A - Sigma delta type a/d converter, demodulator, receiver and disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax digital conversion accuracy being a requirement. SOLUTION: An output of a delay element 34 is fed to a complementary digital filter 44 via a digital integration device 42 to a loop consisting of an analog adder 30, a comparator 32, a delay element 34, a 1-bit D/A converter 361 and an analog integration device 38. The complementary digital filter 44 has a complementary characteristic (1-TR (f)) to a filter characteristic TR (f) to suppress an undesired frequency component included in a digital output SO. An output of the complementary digital filter 44 is fed to the analog adder 30 via a D/A converter 362 as a correction signal of an input signal SI. A QPSK signal quadrature demodulation section of a CDMA receiver multiplies an RF inverse spread signal and an RF modulation signal and filters harmonics to conduct filtering and inverse spread by a detection partial response filter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a sigma-delta type A.
The present invention relates to a / D converter, a demodulator, a receiver and a disk device using the A / D converter or the demodulator.

[0002]

2. Description of the Related Art FIG. 1 shows a receiving section and a demodulating section of a conventional quadrature demodulation type receiver. The signal received by the antenna 10 is supplied to the mixer 13 via the low-noise amplifier 11 and the band-pass filter 12, is multiplied with the local oscillation signal LO1, and the frequency is shifted to the intermediate frequency (IF). The signal passes through the band-pass filter 15 and the mixer 1
It is supplied to one input of each of 6A and 16B. The other input terminal of each of the mixers 16B and 16A is supplied with a local oscillation signal LO2 and a signal obtained by shifting the phase thereof by the π / 2 phase shifter 17. Thereby, the output of the band-pass filter 15 is synchronously detected, and the in-phase component and the quadrature component of the baseband signal are supplied to the A / D converters 18A and 18B, respectively, and are digitized.

In digital communication, a half-Nyquist filter, which is a kind of low-pass filter, is generally used as a transmission filter. In this case, the use of a half-Nyquist filter as a reception filter suppresses intersymbol interference and adjacent channel interference. . When the bandwidth of the baseband signal is wide as in CDMA, the half-Nyquist filter cannot be constituted by an analog filter, and a digital filter constituted by a DSP is used. In the case of a transmission filter, the output of this DSP is D
The signal may be converted into an analog signal by an / A converter.

However, in the case of a receiving filter, as shown in FIG. 22, the digital signal must be digitized by A / D converters 18A and 18B and then filtered by a DSP 19 using a half-Nyquist filter. The input signals of the A / D converters 18A and 18B have a low SN ratio due to intersymbol interference, no intersymbol separation, and an adjacent channel interference signal.

Therefore, it is necessary to increase the accuracy of the A / D converters 18A and 18B, which increases the cost. When a conventional sigma-delta A / D converter having a relatively simple configuration is used as the A / D converters 18A and 18B, the bit error rate increases due to the above-described causes and low conversion accuracy. The band-pass filter 15 is a SAW filter that delays a signal with a surface acoustic wave.
Different components are required for the first and second stages of the filter. For this reason, achieving high reliability by miniaturization, high integration, and reduction in the number of components is prevented.

FIG. 23 shows a conventional disk drive reading unit. A signal recorded on an optical disk or a magnetic disk is detected by a head 20, passed through a low-noise amplifier 22 and a band-pass filter 25, digitized by an A / D converter 28, and supplied to a DSP 29. In order to achieve high recording density and high-speed reading, high-speed and high-precision signal processing is required. The A / D converter 28 has 14 to 16 bits.
Performance of several hundred MSps is becoming necessary. As with the half-Nyquist filter, if a PRML filter, which is a kind of a partial response filter, can be provided in a stage preceding the A / D converter 28, the A / D converter 2
8 is greatly relaxed.

However, conventionally, this is not possible, and DSP2
At 9 the filter had to be filtered with a PRML filter. Such a problem also occurs in other devices that need to suppress unnecessary frequency components with a digital filter after digitizing an analog signal.

[0008]

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a digital conversion required by performing a correction control by feeding back a signal from a digital circuit to an analog circuit while digitizing an analog signal. An object of the present invention is to provide a sigma-delta A / D converter capable of relaxing accuracy, and a receiver and a disk device using the same.

Another object of the present invention is to provide a demodulator capable of relaxing digital conversion accuracy required by supplying information of a digital filter to an analog circuit, and a receiver and a disk device using the same. Is to do.

[0010]

According to the present invention, in a sigma-delta A / D converter for converting an analog input signal into a digital output, the digital output is supplied and included in the digital output. A complementary digital filter having characteristics complementary to a filter characteristic for suppressing unnecessary frequency components; and a D / A converter, and substantially converting the output of the complementary digital filter to the D / A conversion The analog input signal is corrected by an inverted signal of the signal converted to analog by the device.

When the output of the D / A converter is not used,
Feedback control is performed so that the analog feedback signal value corresponding to the digital output approaches the analog input signal value. However, since the analog input signal contains unnecessary frequency components, higher precision is required for the sigma-delta A / D converter. To meet this requirement, the sample clock frequency becomes too high and impractical.

When the output of the D / A converter is not fed back, the output of the complementary digital filter is a signal component to be removed from the digital output by the complementary digital filter and a desired digital filter complementary to the digital filter. When the output of the digital filter is fed back, that is, when the analog input signal is corrected with an inverted signal of the signal obtained by converting the output of the complementary digital filter into an analog signal by the D / A converter, the corrected signal is converted into an analog feedback signal corresponding to the digital output. Feedback control is performed so that the signal approaches.

As a result, the S / N ratio of the corrected signal is improved, so that the conversion accuracy required for the sigma-delta A / D converter is relaxed, and the conventional A, which has conventionally required high accuracy, is required.
There is an effect that the sigma-delta A / D converter can be used instead of the / D converter. 3. The sigma-delta A / D converter according to claim 2, wherein the D / A converter quantizes an error signal between the corrected analog input signal and an analog feedback signal corresponding to the digital output. Having.

According to a third aspect of the present invention, in the sigma-delta A / D converter according to the first or second aspect, the complementary digital filter has a characteristic complementary to a partial response filter characteristic. In the sigma-delta A / D converter according to claim 4, in claim 3, the complementary digital filter is
It has characteristics complementary to the half Nyquist filter characteristics.

In the sigma-delta A / D converter according to a fifth aspect, in the third aspect, the complementary digital filter includes:
It has characteristics complementary to the PRML filter characteristics. According to the sigma-delta type A / D converter of claim 6, claim 1 or 2
In the above, the complementary digital filter has characteristics complementary to the equalizing filter characteristics. In the sigma-delta A / D converter according to claim 7, in claim 1 or 2,
The complementary digital filter has characteristics complementary to the adaptive equalizing filter characteristics.

According to an eighth aspect of the present invention, in the sigma-delta A / D converter according to the first or second aspect, the complementary digital filter has a characteristic complementary to a multipath interference removal filter characteristic. In a sigma-delta A / D converter according to a ninth aspect, in the first or second aspect, the complementary digital filter has a rake combining function.

According to a tenth aspect of the present invention, in the sigma-delta type A / D converter according to the first or second aspect, the output of the complementary digital filter is supplied to the D / A converter via a digital differentiator. The output of the A converter is used as the analog feedback signal via an analog integrator. In the sigma-delta A / D converter according to claim 11, the sigma-delta A / D converter according to claim 2, wherein a value obtained by adding a value obtained by integrating an output of the comparator and an output value of the complementary digital filter to the D / A converter is used. Supplied.

According to a twelfth aspect of the present invention, in the sigma-delta A / D converter according to the second aspect, the analog input signal is supplied to an input terminal of the comparator via an integration capacitor, and the D / A converter is inverted. An output is provided to the input of the comparator. In the sigma-delta A / D converter according to claim 13,
3. The comparator according to claim 2, wherein an integration capacitor is connected between a conductor of a reference potential and an input terminal of the comparator, and an inverted output of the D / A converter is supplied to an input terminal of the comparator.

In the sigma-delta A / D converter according to the present invention, an integrating capacitor is connected between the inverting output terminal of the D / A converter and the input terminal of the comparator. . In the sigma-delta A / D converter of claim 15, in claim 2, digital integration of the output of the comparator is performed by a counter, a moving average filter, or a low-pass filter.

In a sigma-delta A / D converter according to a sixteenth aspect, in the second aspect, the complementary digital filter performs a product-sum operation on a low-order term and a product-sum operation on the remaining terms. The second filter is executed by a DSP operating at a clock lower than the operation clock of the first filter. In the sigma-delta A / D converter according to claim 17, in claim 16, the D / A converter is a first D / A converter connected to an output side of the first filter, and the second filter. And a second D / A converter connected to the output side of.

According to an eighteenth aspect, in the sixteenth aspect, the DSP performs a differentiation process at a stage before or after the process of the second filter. The sigma-delta A according to any one of claims 2 to 18, wherein the baseband signal is input as the analog input signal in a receiver that digitizes a baseband signal and filters the baseband signal with a reception filter. / D converter.

According to this receiver, the sample clock frequency can be made lower than in the case of the following claim 20. In a twentieth aspect, in a receiver for detecting a modulated wave to obtain a baseband signal, digitizing the baseband signal, and filtering the digital signal with a reception filter, the modulated wave is input as the analog input signal, and the modulated wave is A sigma-delta A / D converter according to any one of claims 2 to 18, wherein a sample clock to the clock input terminal of the comparator is selected to be detected.

According to this receiver, detection can be performed in addition to digitization and filtering of unnecessary signals. Claim 2
In a disk device, a modulation signal recorded on a disk is read by a head, a baseband signal is obtained by detecting the modulation wave, and the baseband signal is digitized and filtered by a partial response filter. A wave is input as the analog input signal,
19. A sigma-delta A / D converter according to claim 2, wherein a sample clock to a clock input terminal of the comparator is selected so that the modulated wave is detected.

According to a twenty-second aspect, in a demodulator for filtering a signal obtained by multiplying a digital data by a spreading code with a first partial response filter and extracting the digital data from an RF modulation signal modulated by the filtered signal, An RF despread signal generation circuit for generating an RF despread signal in which a despread code is synthesized by a signal filtered by the second partial response filter and a local transmission signal; the RF despread signal; the RF modulated signal; A multiplying / filtering circuit for performing detection, filtering by the second partial response filter and despreading by multiplying the input signal, which is a signal obtained by shifting the frequency of the RF modulation signal to the intermediate frequency, and filtering the harmonics; Have.

According to this demodulator, detection and filtering by the second partial response filter and despreading are performed by the product and harmonic filtering, so that the configuration and processing are simplified. According to a twenty-third aspect of the present invention, in the twenty-second aspect, the output of the multiplying / filtering circuit is digitized by a comparator, and the output of the comparator is delayed and converted to an analog signal. And an integration loop circuit for adding to the output of.

According to a twenty-fourth aspect of the present invention, in the demodulator according to the twenty-third aspect, a multiplying circuit for multiplying the RF despread signal and the analog signal, and an analog adder for adding an output of the multiplying circuit to the input signal And According to a twenty-fifth aspect of the present invention, the demodulator according to the twenty-fourth aspect further includes a digital low-pass filter inserted into the integration loop of the integration loop circuit.

According to a twenty-sixth aspect, in the twenty-third aspect, the demodulator further comprises a digital differentiator to which the output of the integration loop circuit is supplied, and a decimator for decimating the output of the differentiator circuit. The receiver according to claim 27 includes the demodulator according to any one of claims 22 to 26.

[0028] In the disk device of claim 28, claim 2
The demodulator according to any one of 2 to 26 is provided.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a basic configuration of a sigma-delta A / D converter according to a first embodiment of the present invention. In FIG. 1, symbols + and-indicate a non-inverting input terminal and an inverting input terminal, respectively. The left and right sides of the dashed line are an analog circuit and a digital circuit, respectively.
2 shows a D converter and a D / A converter.

The loop of the analog adder 30, the comparator 32, the delay element 34, the D / A converter 361, and the analog integrator 38 is a known sigma-delta converter, and the non-inverting input terminal of the analog adder 30 , An input signal SI is supplied from an input terminal 40. The comparator 32 binarizes or ternarizes the analog input signal X and outputs a digital signal Y in synchronization with the sample clock SC. For example, in the case of ternarization, if X <−
If ε, −ε ≦ X ≦ ε or X> ε, then '-
1 ',' 0 'or' 1 'is output. Digital signal Y
Is supplied to the D / A converter 361 after being delayed by one sampling period by the delay element 34.

In the following, the binary bit '-1' can be processed as '0'. D / A converter 36
1 outputs an analog value (the amount of voltage, current or charge) Δ when the input is “1” and outputs an analog value 0 when the input is “0” when the comparator 32 is ternarized, Input is'-
When the value is 1 ', an analog value -Δ is output. D / A converter 3
61 is a current switch, for example.

The analog integrator 38 is, for example, an integrating capacitor or a circuit in which a capacitor is connected between input and output terminals of an operational amplifier. In the digital circuit, the output of the comparator 32 is supplied to the complementary digital filter 44 via the delay element 34 and the digital integrator 42. Digital integrator 42
Corresponds to the digital value of the output of the analog integrator 38 and is taken out from the output terminal 46.

The signal Y is delayed by one sampling period by the delay element 34, and the delayed signal is
The digital integrator 42 integrates in synchronization with C. The digital integrator 42 is, for example, a counter that counts up and down when the input is 1 or “−1”, a moving average filter, or a low-pass filter.

The complementary digital filter 44 includes an integrator 44
A filter (complementary digital filter) having a characteristic (1-TR (f)) complementary to the filter characteristic TR (f) for suppressing unnecessary frequency components included in the baseband signal output from the digital filter. It has characteristics as shown in FIG. The complementary digital filter 44 has, for example, a complementary half-Nyquist filter or a complementary PRML filter that is a complementary partial response filter, or a characteristic complementary to an equalizer characteristic, an adaptive equalizer characteristic, a multipath interference removal characteristic, or an adaptive multipath interference removal characteristic. It is a complementary digital filter. The complementary digital filter may have a rake combining function. The complementary digital filter 44 is basically represented by a product-sum operation, and its coefficient can be easily determined by an impulse response.

The complementary digital filter 44 has a complementary PRML
In the case of a filter, the sigma-delta A / D converter of FIG.
ML filter). The output of the complementary digital filter 44 is supplied to an inverting input terminal of the analog adder 30 via a 1-bit or multi-bit output D / A converter 362.

Next, the operation of the sigma-delta A / D converter configured as described above will be described. The input signal SI is, for example, an RF modulation signal or a baseband signal obtained by detecting the RF modulation signal. When the input signal SI is an RF modulation signal before detection, a signal having a frequency that can be synchronously detected is used as the sample clock SC. The sample clock SC and the quantization step Δ are determined according to the required digital conversion accuracy.

If the input signal SI is an RF modulation signal, there is a disadvantage that the frequency of the sample clock SC becomes high, but there is an advantage that detection is performed simultaneously by sampling. When the output of the D / A converter 362 is not supplied to the analog adder 30, feedback control is performed so that the output of the analog integrator 38 approaches the input signal SI, and the output signal SO becomes a digital value corresponding to the input signal SI. Becomes However, since the input signal SI includes the unnecessary frequency components, higher accuracy is required for the sigma-delta A / D converter. In order to meet this demand, the frequency of the sample clock SC becomes too high, which is not practical.

When the output of the D / A converter 362 is not supplied to the analog adder 30, the complementary digital filter 4
The output of 4 is a signal component to be removed from the output signal SO of the digital integrator 42 by the digital filter having the characteristic TR. When the output of the complementary digital filter 44 is supplied to the analog adder 30 via the D / A converter 362, the unnecessary component is removed from the difference between the input signal SI and the output of the D / A converter 362, that is, the input signal SI. Signal (SI is RF
In the case of a modulated signal, feedback control is performed so that the output of the analog integrator 38 approaches a signal (a signal obtained by removing unnecessary components included in the baseband signal synchronously detected by the sample clock SC).

As a result, the conversion accuracy required for the sigma-delta A / D converter is relaxed, and the sigma-delta A / D converter is replaced with a conventional A / D converter requiring high accuracy. Can be used. Output signal SO
Is a digital value corresponding to the output of the analog integrator 38, and as a result, the output signal SO tends to be a signal filtered by the analog filter having the characteristic TR.

FIG. 1 shows an example of a logical configuration, and the present invention includes various modifications having substantially the same function as this configuration. For example, the polarity of the output of the D / A converter 362 may be reversed and supplied to the non-inverting input terminal of the analog adder 30. The same applies to the D / A converter 361. The polarity of the output with respect to the input of the comparator 32 may be reversed, and the polarity of the input or output of the analog adder 30 may be reversed. Further, the same or almost the same function may be achieved for each of the digital circuit and the analog circuit by changing the order of the linear elements connected in series. For example, in FIG. 1, the output of the delay element 34 is supplied to the digital integrator 42 in order to eliminate the time lag between the output of the digital integrator 42 and the output of the analog integrator 38. A configuration for supplying the integrator 42 may be used.

FIGS. 3 to 7 show the first to fifth examples each having substantially the same structure as the structure of FIG. 1, that is, having the same function as the structure of FIG. 1 and having a different expression form. 3, a digital differentiator (differentiator) 48 is connected between the output terminal of the complementary digital filter 44 and the input terminal of the D / A converter 362, and the output terminal of the D / A converter 362 and the analog adder 30 are connected. The analog integrator 38A is connected between the input terminal of the analog integrator 38A.

In FIG. 4, the D / A converter 36 shown in FIG.
In order to connect the input terminal of the digital integrator 42 to the output terminal of the digital integrator 42, the output terminal of the digital integrator 42 and the D / A converter 36
A digital differentiator 481 is connected between the input terminal and the first input terminal. In FIG. 5, the output of the digital integrator 42 and the output of the complementary digital filter 44 are added by the digital adder 49, so that the digital differentiator 481 of FIG.
A cascade connection of the converter 361 and the analog integrator 38A;
The cascade connection of the digital differentiator 482, the D / A converter 362A, and the analog integrator 38 is combined to form a cascade connection of the digital differentiator 48, the D / A converter 36, and the analog integrator 38. The D / A converter 36 is a multi-bit input.

According to this configuration, the analog circuit is simplified. The delay element 34, the digital integrator 42, the complementary digital filter 44, the digital adder 49, and the differentiator 48 can be regarded as one digital filter as a whole, and can be digitally processed by one DSP by a program. Differentiator 48 that performs operations opposite to each other
And the integrator 38 may be omitted.

In FIG. 6, the analog integrator 38 and the digital differentiator 482 of FIG. 4 perform operations opposite to each other on the same line, and the analog integrator 38A and the digital differentiator 481 perform operations opposite to each other on the same line. Therefore, the configuration is omitted. In FIG. 7, since the analog integrator 38 and the differentiator 48 of FIG. 5 perform operations opposite to each other on the same line, the configuration is omitted.

FIG. 8 shows an embodiment of the configuration of FIG. In this configuration, the analog integrator 38 and the analog adder 30 of FIG. 5 are configured by one integration capacitor 38B.
The digital filter 44A has the function of the complementary digital filter 44 and the digital adder 49 shown in FIG. In addition, as is well-known, '1', '0' or '-
The quantization step Δ is increased or decreased according to the number of consecutive 1's,
Needless to say, a configuration in which the complementary digital filter of the present invention is applied to an adaptive sigma-delta A / D converter that increases or decreases the input value of the integrator 42 according to this may be used. Further, a configuration in which the complementary digital filter of the present invention is applied to a second-order or higher sigma-delta A / D converter may be employed.

FIG. 9 shows that the configuration of FIG.
2 shows a sigma-delta A / D converter applied to a QPSK demodulation circuit of an A receiver. This circuit is an improvement of part 1 (including the receiving filter in the DSP) of the conventional circuit of FIG. Hereinafter, the I channel will be mainly described. The reception filter is a half Nyquist filter, for example, a root raised cosine roll-off filter, and a complementary half Nyquist filter having a characteristic complementary to this filter characteristic is used as the complementary digital filter 44 in FIG.

In this circuit, the digital integrator 42 shown in FIG.
And the D / A converter 361 are constituted by the counter 42A and the inverted output type current switch circuit 361A, respectively.
For example, the counter 42A increments the count value by 1 when the output of the delay element 34 is “1”, and decrements the count value by 1 when the output of the delay element 34 is “−1”. The input of the current switch circuit 361A is “1”.
, A constant negative current −Δ is output, and when the input is “−1”, a constant positive current Δ is output. These '1' and '-1' may be an up signal and a down signal, respectively. 31 is a coupling capacity. The comparator 32 has a high impedance input, and the input node of the comparator 32 is a charge integration node.

The complementary digital filter 44 shown in FIG.
With the FIR filter 441, the register 442, and the DSP4
43. The FIR filter 441 shares the low-stage terms of the product-sum operation of the complementary digital filter 44, and performs high-speed processing in synchronization with the sample clock Ci. In the register 442, the count of the counter 42A is latched (decimated) by a clock having a frequency that satisfies the sampling theorem, which is lower than the frequency of the sample clock Ci. The DSP 443 is a complementary digital filter 4
4, the remaining stages of the product-sum operation are shared, and the content of the register 442 is processed at a low speed in this cycle.

The output of the FIR filter 441 is
The signal is digitized by the inverted current output type D / A converter 362A via 8A, and the electric charge is supplied to the input node (charge integration node) of the comparator 32 via the integration capacitor 38B1. The DSP 443 also performs a differentiator process before or after filtering. The output of the DSP 443 is digitized by the inverted current output type D / A converter 362B,
Further, charge is supplied to the input node of the comparator 32 via the integration capacitor 38B2.

The sample clock generation circuit 50 generates an in-phase component sample clock Ci and a quadrature component sample clock Co for synchronous detection based on the clock CLK, and supplies the clock Ci to the clock input terminal of the comparator 32. For example, the intermediate frequency COS (2π · fi · t) and −
SIN (2π · fi · t) is supplied to each of the other comparators to generate square-wave clocks Ci and Co, and at the rising edge, the inputs of the I-channel comparator 32 and the corresponding comparator of the Q channel are digital. Be transformed into Comparator 3
2 outputs a pulse or holds the output until the next sample clock.

The same applies to the Q channel as to the I channel. In-phase component SOI and quadrature component S of output signal
The OQ is feedback-controlled as described above so as to be filtered by a half-Nyquist filter which is a reception filter. For example, the input signal SI is obtained by converting a received signal having a carrier frequency fc = 1.4 GHz into an intermediate frequency fi = 3.
It is converted into a signal of 50 MHz, and the sampling frequency is also 350 MHz. The input of the register 442 is latched by a clock whose sampling frequency has been reduced to 43.75 MHz. For example, the digital circuit on the left side of the alternate long and short dash line in FIG. 9 is a compound semiconductor HEM such as InGaP.
The D / A converter is composed of a silicon bipolar transistor LSI, and the right side of the dashed line is composed of a low-speed and low-power-consumption CMOS circuit. Such a configuration is used as a base station receiver.

For example, the FIR filter 441 performs the 171-stage operation in the product-sum operation at 350 Sps. As described above, the input signal SI may be a baseband signal obtained by detecting an RF modulation wave. In this case, the sampling period can be reduced to, for example, 43.75 MHz, and the entire circuit of FIG. It can be configured as a circuit and used for a mobile station receiver.

[Second Embodiment] FIG. 10 shows a second embodiment of the present invention.
Sigma delta type A to which the configuration of FIG.
1 shows a basic configuration of a / D converter. The integration capacitor 3 of FIG.
8B, the analog integrator 38 and the analog adder 30
It comprises an integrating capacitor 38C and a V / I converter 31A. A reference potential, for example, a ground potential is applied to one end of the integration capacitor 38C. V / I converter 31A is, for example, a transconductance amplifier. The input signal SI is supplied to an input node (charge integration node) of the comparator 32 via the V / I converter 31A.
The output of comparator 32 is provided to decimator 42C to speed up the feedback to the analog circuit. The decimator 42C includes the above-described counter, moving average filter, or low-pass filter. DSP44C
Performs the processing of the complementary digital filter 44 and the differentiator 48 of FIG.

Current switch 361 and D / A converter 36
2 is an inverted current output type. FIG. 11 shows a modification of the configuration of FIG. In this circuit, an integration capacitor 38C is connected between the inverted voltage output terminal of the D / A converter 362 and the input terminal of the comparator 32. When the D / A converter 362 is a current output type, differentiation in the DSP 44C becomes unnecessary. Other points are the same as those in FIG.

[Third Embodiment] FIG. 12 shows a third embodiment of the present invention.
3 shows a sigma-delta A / D converter for demodulating a wideband CDMA receiver to which a configuration similar to that of FIG. 3 is applied, according to an embodiment. This circuit is, for example, part 1 of the conventional circuit of FIG.
(Including the receiving filter in the DSP). The sigma-delta A / D converter is obtained by adding a loop of a complementary digital filter to a known second-order sigma-delta A / D converter.

V / I converter 31A and integrating capacitor 3
8C is the same as FIG. Current switch 3
The inversion current output terminals of 61A and 361B are connected to one ends of integration capacitors 38C and 38D, respectively, and the inversion current output terminal of D / A converter 362 is connected to the one end of integration capacitor 38C. The voltage of the integration capacitor 38C is converted into a current by the V / I converter 31B, and this current and the inverted current output of the current switch 361B are stored in the capacitor 38D, and the voltage due to the charge is supplied to the comparator 32 as an error signal. You. Q channel is also I
Same as channel.

13 to 19 show simulation conditions or results of the circuit of FIG. FIG. 13 shows the reception QP
IQ of orthogonal baseband signal included in SK signal
This shows a locus on rectangular coordinates. Four phase points (1,1),
The reason why (-1, 1), (1, -1) and (-1, -1) are not converged, that is, the reason for occurrence of intersymbol interference is root raised cosine which is a kind of partial response filter. This is due to being filtered by the roll-off transmit filter but filtered by the root raised cosine roll-off receive filter.

FIG. 14 shows the waveform of the received signal SI. The vertical axis is standardized so that the average amplitude value is 1. Since the signal is a high-frequency signal, it is painted black, and only the envelope is indistinguishable. FIG.
The frequency characteristic of the complementary root raised cosine roll-off filter as the two complementary digital filters 44 is shown. The horizontal axis is the baseband signal bandwidth 4.096M.
Hz is set to 32. 1024 x 4.096 / 32M
The high-frequency side is cut off and approximated so as to be symmetrical at Hz. The central V-shaped portion is formed for stabilizing the operation.

FIG. 16 shows the complementary digital filter 44.
5 shows an impulse response waveform of FIG. The characteristics of the complementary digital filter 44 are determined by this waveform. FIG.
I component SO of the quadrature baseband signal demodulated by the circuit
3 shows waveforms of I and Q component SOQs. FIG. 18 shows the locus of the signal of FIG. 17 on the IQ orthogonal coordinates. The values on the vertical and horizontal axes are digital values.

FIG. 19 shows an ideal locus corresponding to FIG. 18, that is, a locus on the IQ orthogonal coordinates of a signal obtained by filtering the signal of FIG. 13 with a root raised cosine roll-off filter. Comparing FIG. 18 with FIG. 19, it can be seen that good results are obtained with this embodiment.

[Fourth Embodiment] FIG. 20 is a block diagram showing a receiver quadrature demodulator according to a fourth embodiment of the present invention to which a sigma-delta A / D converter is applied. Hereinafter, the I channel will be mainly described. This receiver uses QPS
It is assumed that the CDMA receiver receives the K signal, but may be another similar device.

The input signal SI is a signal obtained by multiplying data D (t) by a complex spreading code C (t) through a half-Nyquist filter and modulating a carrier having an angular frequency ω. A code obtained by passing the complex spreading code C (t) through a half-Nyquist filter is represented by c (t). In an ideal case, the input signal SI is expressed as: SI = D (t) | c (t) | COS (ωt + φ (t)), where D (t): binary value of -1, -1 Data sequence c (t) = | c (t) | EXP (jφ (t)), where j is an imaginary unit.

The input signal SI is supplied to one input terminal of the analog adder 54. The output of the analog adder 54 is supplied to one input terminal of the product circuit 56A. The RF despread signal Ri (t) is supplied from the RF despread signal generation circuit 58 to the other input terminal of the multiplication circuit 56A. R
In the F despread signal generation circuit 58, the DSP 581
A complex despreading code C (t) equal to the complex spreading code is generated, and then a multi-valued digital signal c (t) that is passed through a half-Nyquist filter is generated.
(T) | COS (φ (t)) and orthogonal component | c (t) |
SIN (φ (t)) is supplied to D / A converters 582A and 582B, respectively. D / A converters 582A and 582
The output of 2B is supplied to the synthesis circuit 583, and from this, the carrier wave CI = COS (ωt) and CQ = −SIN (ωt) generated by the local oscillation circuit, the RF despread signal Ri (t) = | c (T) | COS (ωt + φ (t) + φ
0) Rq (t) = | c (t) | SIN (ωt + φ (t) + φ
0) is generated. Here, φ0 is a phase offset. The suffixes i and q indicate the in-phase component and the quadrature component, respectively, and so on.

Analog adder 54, analog multiplying circuit 5
6A, analog low-pass filter 59, analog adder 60, comparator 32, digital delay element 34, 1-bit D
A loop of the / A converter and the analog multiplication circuit 56A is formed. 0.5 times the output F of the current switch 36 is subtracted by the adder 60, and the output of the product circuit 56B is
4 is subtracted.

The output of the adder 54 is (SI−F · Ri), and the output of the multiplication circuit 56A is Ri · (SI−F · Ri) = (D + F) · | c (t) | ² COS (ωt + φ) (T) + φ0) · COS (ωt + φ (t)) = (D + F) · | c (t) | ² {COS (2ωt + 2φ (t) + φ0) + COS (φ0)} / 2 This harmonic component is filtered by the low-pass filter 59, and (D + F) · | c (t) | ² · COS (φ0)
/ 2 is obtained. Therefore, the output SI of the adder 60
Is: SI = (D + F) · | c (t) | ² · COS (φ0) /
2-F / 2 For simplicity, if φ0 = 0, then SI = (D + F) · | c (t) | ² / 2−F / 2.

When F = 1 and D = 1, SI = │c (t) │ ² −0.5. | C (t) | is the distance from the origin in FIG. 19 to a point on the trajectory.
> 0, and the output of the comparator 32 becomes '1'. This corresponds to the detection of D (t) = '1'.

When F = −1 and D = −1, SI = − | c (t) | ² +0.5. SI <0 near the above four phase points,
The output of the comparator 32 is "-1". This is D (t)
== “− 1” is detected. The data D (t) can be demodulated by sampling the in-phase component SI at the bit period of the data D (t).

In FIG. 20, after the output of the delay element 34 is supplied to a digital differentiator (differentiator) 64 and a counter 442 as a digital integrator, the output is latched by a register 442 at a frequency lower than the sampling clock, and the product circuit At 66B, it is multiplied with COS (φ0). The same applies to the Q channel as to the I channel. The RF despread signal Rq (t) is supplied from the RF despread signal generation circuit 58 to one input terminal of each of the multiplication circuits 56C and 56D. The register output is SIN (φ
0). The output of the product circuit 66A and 66B are added by the adder 68, disappears phase offset term, the output SO = D (t) | c (t) | 2/2 is obtained.

FIG. 21 shows a modification of the configuration of FIG.
In this circuit, an analog low-pass filter 59A is inserted between the analog adder 60 and the comparator 32. The frequency characteristic of the low-pass filter 59A is, for example,
This is the same as that of the low-pass filter 59. Delay element 3
The output of 4 is supplied to the shift register 42D (or serial / parallel converter), and is held in the register 442 at a reduced sampling rate. The same applies to the Q channel as to the I channel. Outputs SOI 'and SOI from register 442 and the corresponding register of the Q channel, respectively.
Q ′ is obtained.

The other points are the same as those in FIG.

[Brief description of the drawings]

FIG. 1 shows a sigma-delta A / D according to a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a basic configuration of a converter.

FIG. 2 is a diagram illustrating an example of a frequency characteristic of the digital filter of FIG. 1;

FIG. 3 is a diagram showing a first example having the same function as the configuration of FIG. 1 and having a different expression format.

FIG. 4 is a diagram showing a second example having the same function as the configuration of FIG. 1 and having a different expression format.

FIG. 5 is a diagram showing a third example having the same function as the configuration of FIG. 1 and having a different expression format.

FIG. 6 is a diagram showing a fourth example having the same function as the configuration of FIG. 1 and having a different expression format.

FIG. 7 is a diagram showing a fifth example having the same function as the configuration of FIG. 1 and having a different expression format.

FIG. 8 is a block diagram showing one embodiment of the configuration of FIG. 5;

FIG. 9 is a block diagram showing a sigma-delta A / D converter in which the configuration of FIG. 3 is applied to a quadrature demodulation circuit of a CDMA receiver.

FIG. 10 is a block diagram showing a basic configuration of a sigma-delta A / D converter to which the configuration of FIG. 3 is applied according to a second embodiment of the present invention.

FIG. 11 is a block diagram showing a modification of the configuration of FIG. 10;

FIG. 12 is a block diagram illustrating a basic configuration of a sigma-delta A / D converter to which the configuration of FIG. 3 is applied according to a third embodiment of the present invention.

13 is a graph showing I- of an orthogonal baseband signal included in an input RF signal used in the simulation of the circuit of FIG. 12;
FIG. 3 is a diagram showing a trajectory on Q orthogonal coordinates.

14 is a waveform chart showing an input RF signal used in the simulation of the circuit of FIG.

FIG. 15 shows an F used in the simulation of the circuit of FIG.
It is a frequency characteristic figure of an IR complementary digital filter.

FIG. 16 shows F used in the simulation of the circuit of FIG.
It is a figure showing an impulse response waveform of an IR complementary digital filter.

17 is a diagram showing a demodulated quadrature verse band signal waveform obtained by a simulation of the circuit of FIG. 12;

18 is a diagram showing a locus of the signal of FIG. 17 on IQ orthogonal coordinates.

FIG. 19 is a diagram showing an ideal trajectory corresponding to FIG. 18;

FIG. 20 is a block diagram illustrating a quadrature demodulation unit of a CDMA receiver according to a fourth embodiment of the present invention.

FIG. 21 is a block diagram showing a modification of the configuration of FIG. 20;

FIG. 22 is a block diagram showing a conventional quadrature demodulation type receiver.

FIG. 23 is a block diagram showing a conventional disk device reading unit.

[Explanation of symbols]

Reference Signs List 10 antenna 11, 22 low noise amplifier 12, 15, 25 bandpass filter 13, 16A, 16B mixer 17 π / 2 phase shifter 18A, 18B, 28 A / D converter 19, 29, 44C, 443 DSP 20 head 30, 54, 60 Analog adder 31 Coupling capacitance 31A, 31B V / I converter 32 Comparator 34 Delay element 361 1-bit D / A converter 361A Current switch circuit 362, 362A D / A converter 38, 38A Analog integrator 38A , 38A1, 38A2, 38C, 38D Integrating capacitor 381 Adder 382 Delayer 40 Input terminal 42 Digital integrator 42A Counter 42C Decimator 42D Serial / parallel converter 44, 44A Digital filter 441 FIR filter 442 Register 46 Output terminal 48, 48A Differentiator 49, 54, 60, 68 Digital adder 50 Sample clock generation circuit 56A, 56B, 66A, 66B Product circuit 59, 59A Low-pass filter 64 Differentiator 641 Subtractor SI Input signal SO Output signal SOI Output signal In-phase component SOQ Output signal quadrature component SC sample clock Ci in-phase component sample clock Ci quadrature component sample clock CLK clock

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 27/22 H04L 27/22 Z F-term (Reference) 5D044 CC04 FG01 GK17 GL02 GL31 5J064 AA01 BA03 BC06 BC07 BC08 BC10 BC12 BC29 BD01 5K004 AA05 FA05 FG02 FH01 5K022 AA04 AA23 CC10

Claims (28)

[Claims] 1. A sigma-delta A / D converter for converting an analog input signal to a digital output, wherein the digital output is supplied and complementary to a filter characteristic for suppressing unnecessary frequency components included in the digital output. And a D / A converter having substantially characteristic characteristics, and the analog input is substantially an inverted signal of a signal obtained by converting the output of the complementary digital filter into an analog signal by the D / A converter. A sigma-delta A / D converter for correcting a signal. 2. The D / A converter according to claim 1, further comprising a comparator for quantizing an error signal between the corrected analog input signal and an analog feedback signal corresponding to the digital output. 2. The sigma-delta A / D converter according to 1. 3. The sigma-delta A / D converter according to claim 1, wherein said complementary digital filter has a characteristic complementary to a partial response filter characteristic.
D converter. 4. The sigma-delta A / D converter according to claim 3, wherein said complementary digital filter has characteristics complementary to half-Nyquist filter characteristics. 5. The method according to claim 1, wherein the complementary digital filter is a PRML.
4. The sigma-delta A / D converter according to claim 3, having a characteristic complementary to a filter characteristic. 6. The sigma-delta A / D converter according to claim 1, wherein said complementary digital filter has a characteristic complementary to an equalizing filter characteristic. 7. The sigma-delta A / D converter according to claim 1, wherein the complementary digital filter has a characteristic complementary to an adaptive equalizing filter characteristic. 8. The sigma-delta A / D according to claim 1, wherein said complementary digital filter has a characteristic complementary to a characteristic of a multipath interference removal filter.
converter. 9. The sigma-delta A / D converter according to claim 1, wherein said complementary digital filter has a rake combining function. 10. The output of the complementary digital filter is supplied to the D / A converter via a digital differentiator, and the output of the D / A converter is used as the analog feedback signal via an analog integrator. The sigma-delta A / D converter according to claim 1 or 2, wherein: 11. The D / A converter is supplied with a value obtained by adding a value obtained by integrating an output of the comparator and an output value of the complementary digital filter.
A sigma-delta A / D converter as described in the above. 12. The analog input signal is supplied to an input terminal of the comparator via an integration capacitor, and the D / A
3. The sigma-delta A / D converter according to claim 2, wherein an inverted output of the converter is supplied to an input terminal of the comparator. 13. The comparator according to claim 1, wherein an integration capacitor is connected between a conductor of a reference potential and an input terminal of said comparator, and an inverted output of said D / A converter is supplied to an input terminal of said comparator. The sigma-delta A / D converter according to claim 2. 14. The sigma-delta A / A converter according to claim 2, wherein an integration capacitor is connected between an inverting output terminal of said D / A converter and an input terminal of said comparator.
D converter. 15. The digital integration of the output of the comparator is
3. The sigma-delta A / D converter according to claim 2, wherein the conversion is performed by a counter, a moving average filter, or a low-pass filter. 16. The complementary digital filter is divided into a first filter that performs a product-sum operation on low-order terms and a second filter that performs a product-sum operation on the remaining terms.
3. The method according to claim 2, wherein the first filter is executed by a DSP operating at a clock lower than the operation clock of the first filter.
A sigma-delta A / D converter as described in the above. 17. The D / A converter, comprising: a first D / A converter connected to an output side of the first filter; and a second D / A converter connected to an output side of the second filter. 17. The sigma-delta A / D converter according to claim 16, comprising: 18. The sigma-delta A / D converter according to claim 16, wherein the DSP performs a differentiation process at a stage before or after the process of the second filter. 19. A sigma-delta A according to claim 2, wherein the baseband signal is digitized and filtered by a reception filter, wherein the baseband signal is input as the analog input signal. A receiver having a / D converter. 20. A receiver for detecting a modulated wave to obtain a baseband signal, digitizing the baseband signal, and filtering the digital signal with a reception filter, wherein the modulated wave is input as the analog input signal, and the modulated wave is 19. A sample clock to a clock input terminal of the comparator is selected so as to be detected.
A receiver comprising the sigma-delta A / D converter according to any one of the above. 21. A disk device for reading a modulated signal recorded on a disk with a head, detecting the read modulated wave to obtain a baseband signal, digitizing the baseband signal, and filtering the baseband signal with a partial response filter, 19. The sampled clock to the clock input terminal of the comparator is selected so that the modulated wave is input as the analog input signal and the modulated wave is detected.
A disk device comprising the sigma-delta A / D converter according to any one of the above. 22. A signal obtained by multiplying digital data by a spreading code is filtered by a first partial response filter,
A demodulator for extracting the digital data from the RF modulated signal modulated by the filtered signal, wherein the despreading code generates an RF despread signal in which the signal filtered by the second partial response filter and the local transmission signal are combined. An RF despread signal generation circuit, and multiplying the RF despread signal, the RF modulated signal or an input signal which is a signal obtained by shifting the frequency of the RF modulated signal to an intermediate frequency, and filtering a harmonic. Detection, the second
A multiplying / filtering circuit for performing filtering and despreading by a partial response filter. 23. An integrating loop circuit which digitizes the output of the multiplying / filtering circuit by a comparator, delays the output of the comparator and converts the output into an analog signal, and adds the signal to the output of the multiplying / filtering circuit. 3. The method according to claim 2, further comprising:
2. The demodulator according to 2. 24. A multiplication circuit for multiplying the RF despread signal and the analog signal, and an analog adder for adding an output of the multiplication circuit to the input signal. Item 24. The demodulator according to item 23. 25. The demodulator according to claim 24, further comprising a digital low-pass filter inserted in an integration loop of said integration loop circuit. 26. The demodulator according to claim 23, further comprising: a digital differentiator supplied with an output of the integration loop circuit; and a decimator for decimating an output of the differentiation circuit. 27. A receiver comprising the demodulator according to claim 22. 28. A disk device comprising the demodulator according to claim 22.