JPH06181348A - Magnetoelectric conversion element - Google Patents

Magnetoelectric conversion element

Info

Publication number
JPH06181348A
JPH06181348A JP4333159A JP33315992A JPH06181348A JP H06181348 A JPH06181348 A JP H06181348A JP 4333159 A JP4333159 A JP 4333159A JP 33315992 A JP33315992 A JP 33315992A JP H06181348 A JPH06181348 A JP H06181348A
Authority
JP
Japan
Prior art keywords
type
input
type gaas
hall element
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4333159A
Other languages
Japanese (ja)
Other versions
JP3221114B2 (en
Inventor
Ryoichi Takeuchi
良一 竹内
Masahiko Usuda
雅彦 臼田
Takashi Udagawa
隆 宇田川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP33315992A priority Critical patent/JP3221114B2/en
Publication of JPH06181348A publication Critical patent/JPH06181348A/en
Application granted granted Critical
Publication of JP3221114B2 publication Critical patent/JP3221114B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To enable a magnetic conversion element to be protected against damage and continuously kept stable in characteristics when an operating electric power is abruptly applied by a method wherein a P/N junction is provided to one of a pair of N-type ohmic electrodes. CONSTITUTION:Zn ions are implanted into a P-type GaAs layer forming region 205, which is thermally treated (for instance, in an atmosphere contains arsine gas of prescribed partial pressure) to provide a P/N function to the input electrode 201-a out of a pair of N-type GaAs input electrodes 201-a and 201-b. Furthermore, in an N-type GaAs layer region which is formed into the input power sections 201-a and 201-b and an output power section 202, the N-type GaAs layer is exposed. For instance, Au-Ge alloy is vacuum-evaporated to come into ohmic contact with N-type GaAs for the formation of two pairs of four input electrodes 206-a, 206-b, and 207s. By this setup, a magnetoelectric conversion element of this design can be protected against damage and continuously kept high in characteristics when an operating power is abruptly applied.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は III−V族化合物半導体
材料を用いた磁電変換素子、特に高いサージ耐性を有す
る高信頼性の III−V族化合物磁電変換素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoelectric conversion element using a III-V group compound semiconductor material, and particularly to a highly reliable III-V group compound magnetoelectric conversion element having high surge resistance.

【0002】[0002]

【従来の技術】磁界を検知し、その強度をもって電気信
号に変換する、いわゆる磁電変換素子の一つとしてホー
ル(Hall)素子が知られている。ホール素子は従来
からシリコン(Si)、ゲルマニウム(Ge)等の単一
元素からなる単体半導体や、ヒ化ガリウム(GaAs)
やリン化インンジウム(InP)などの元素周期律表の
第 III族並びに第V族に属する元素からなる、いわゆる
III−V族化合物半導体を利用して得られており、これ
らの半導体材料に磁場を印加した際に起こる電子の運動
によって発生するホール(Hall)電圧を被検知量と
した一種のセンサーであり、従来から磁界強度の測定に
は勿論のこと回転体の回転数の測定など、多岐に亘る産
業分野に多用されている。
2. Description of the Related Art A Hall element is known as one of so-called magnetoelectric conversion elements that detect a magnetic field and convert it into an electric signal with its strength. Hall elements have conventionally been single semiconductors made of a single element such as silicon (Si) and germanium (Ge), and gallium arsenide (GaAs).
And indium phosphide (InP), which are elements of Group III and Group V of the periodic table,
It is a kind of sensor that is obtained by using a III-V group compound semiconductor and has a detected amount of a Hall voltage generated by the movement of electrons when a magnetic field is applied to these semiconductor materials. It has been widely used in various industrial fields such as the measurement of the rotational speed of a rotating body as well as the measurement of the magnetic field strength.

【0003】ホール素子には上記の如くSi単体半導体
の他、InSb、InAsやGaAs等の III−V族化
合物半導体が使用されている。実際のホール素子の製造
にあたっては、例えばInSbから成るバルク結晶その
ものをホール素子の感磁部として利用する場合も有る
が、多くは高抵抗のGaAs単結晶基板にイオン注入法
により或はGaAs単結晶基板上にVPE、MOCV
D、MBE法等の気相成長法や液相成長法により形成さ
れたGaAs層が感磁部として利用されている。従来か
らの一般的なホール素子の製造方法は、この様にして形
成された感磁部となる層上に電気信号の入・出力電極と
なるオーミック(Ohmic)特性を有する電極を形成
し、ホール素子を構成する。
In addition to the Si simple substance semiconductor as described above, III-V group compound semiconductors such as InSb, InAs and GaAs are used for the Hall element. In the actual manufacture of the Hall element, for example, a bulk crystal made of InSb itself may be used as a magnetic sensing portion of the Hall element, but in many cases, it is formed by ion implantation on a high-resistance GaAs single crystal substrate or by GaAs single crystal. VPE, MOCV on the substrate
A GaAs layer formed by a vapor phase growth method such as D or MBE method or a liquid phase growth method is used as a magnetic sensing part. A conventional general method for manufacturing a hall element is to form an electrode having ohmic characteristics, which is an input / output electrode of an electric signal, on the layer which becomes the magnetically sensitive portion thus formed, Configure the element.

【0004】ホール素子の構成上、上記のオーミック電
極は必須な構成要素である。通常ホール素子は図1に示
す様に、感磁部 103 となるGaAsエピタキシャ
ル成長層の表面上に設けた一対の入力電極 101 と
一対の出力電極 102 とから形成される。一般的に
感磁部層 103 となる半導体層の電子移動度の高さ
がホール素子の感度特性を決めるため、感磁部として同
じ半導体材料に於いてもp形ではなくn形の伝導形を示
すn形半導体層が用いられてる。このためこの様なn形
伝導体について電極材料としてオーミック電極となり易
い、例えば金ーゲルマニウム合金などがもっぱら利用さ
れている。
The ohmic electrode is an essential constituent element in the structure of the Hall element. As shown in FIG. 1, the normal Hall element is formed of a pair of input electrodes 101 and a pair of output electrodes 102 provided on the surface of the GaAs epitaxial growth layer which becomes the magnetic sensitive section 103. Generally, the high electron mobility of the semiconductor layer that becomes the magnetic sensing layer 103 determines the sensitivity characteristic of the Hall element, so that even if the same semiconductor material is used as the magnetic sensing section, an n-type conductivity type instead of a p-type conductivity type is used. The n-type semiconductor layer shown is used. For this reason, for such n-type conductors, gold-germanium alloys, which are likely to be ohmic electrodes, are mainly used as electrode materials.

【0005】実際にホール素子を動作させるにあって
は、例えば上記の金ーゲルマニウム合金によって構成さ
れる一対のオーミック性入力電極に電圧を適宣印加す
る。しかし、単にn形の伝導を示す半導体感磁部層上に
形成されたオーミック電極では、動作電圧を印加するに
際し許容値を越えるサージ的な電圧により、或はまた素
子の動作中に起こる突発的な過剰な動作電圧の印加によ
ってもホール素子の機能が破壊される難点があった。こ
のためこの様なサージ的に入力する電圧によるホール素
子の破壊を防御するために、ホール素子の駆動用電気回
路にサージ的な入力を吸収するダイオード等の電気部品
を具備してなる、いわばプロテクト回路を組み込むのが
従来から行われている一般的な方法であった(たとえ
ば、「最新カ−エレクトロニクスと車載電子機器の信頼
性対策」 P.255〜227、1989年 技術情報
協会刊 参照)。
In actually operating the Hall element, a voltage is appropriately applied to, for example, a pair of ohmic input electrodes made of the above-described gold-germanium alloy. However, in the ohmic electrode formed on the semiconductor magnetic sensitive layer which simply exhibits n-type conduction, a surge voltage exceeding an allowable value when an operating voltage is applied, or a sudden phenomenon that occurs during the operation of the device. However, even if an excessive operating voltage is applied, the function of the Hall element is destroyed. For this reason, in order to prevent the destruction of the Hall element due to such a surge-like input voltage, the electric circuit for driving the Hall element is equipped with an electric component such as a diode that absorbs the surge-like input. Incorporation of a circuit has been a general method that has been conventionally performed (see, for example, "Reliability countermeasures for latest car electronics and on-vehicle electronic devices" P.255-227, published by Technical Information Society of 1989).

【0006】[0006]

【発明が解決しようとする課題】しかしながら上記の様
な従来からの方法は、電気部品の構成数を単に増加させ
ると共に電気回路上の構成を複雑化し、結果的にはホー
ル素子の小型化に支障を来す等の欠点があり、微小領域
での磁界測定、2次元的な磁界強度の分布測定には差し
支えを生じていた。
However, the conventional method as described above simply increases the number of components of the electric component and complicates the constitution on the electric circuit, and as a result, obstructs the miniaturization of the Hall element. Therefore, there is a problem in that the magnetic field measurement in a minute area and the two-dimensional magnetic field strength distribution measurement are hindered.

【0007】本発明者は上記の欠点に鑑み、突発的な動
作用電源の入力から素子を保護するための特別な外部回
路を必要とせず、安定的な動作をもたらす高信頼性のし
かも小型化が容易な磁電変換素子を提供することを目的
としてなされたものある。
In view of the above-mentioned drawbacks, the present inventor does not need a special external circuit for protecting the element from the sudden input of the power source for operation, and is highly reliable and miniaturized for stable operation. In order to provide an easy magnetoelectric conversion element,

【0008】[0008]

【課題を解決するための手段】本発明者は従来のホール
素子に見られる感磁部を構成するn形半導体層にオーミ
ック接触を構成する一対の入力電極の構成手段に検討を
加えた。その結果化合物半導体からなるホール素子に於
いて一対を成すオーミック性入力電極の一つにp/n接
合を設けることにより、突発的な動作電源の入力から素
子を保護し、継続して安定な特性を発揮し得る高い信頼
性を有する化合物半導体ホール素子を提供するものであ
る。
Means for Solving the Problems The present inventor has studied a means for forming a pair of input electrodes that form ohmic contact with an n-type semiconductor layer that forms a magnetically sensitive portion, which is found in conventional Hall elements. As a result, in a Hall element made of a compound semiconductor, a p / n junction is provided on one of a pair of ohmic input electrodes to protect the element from the sudden input of operating power supply and to maintain stable characteristics. It is intended to provide a compound semiconductor Hall element having high reliability capable of exhibiting the above.

【0009】上記p/n接合は、例えば入力電極が形成
されるn形半導体層に接合させるてp形半導体を介在さ
せれば容易に形成され得る。例えば、GaAs、In
P、ヒ化インジウム(InAs)やアンチモン化インジ
ウム(InSb)等の III−V族2元化合物、またはそ
れらの混晶半導体を利用したホール素子にあっては、元
素の周期律表に掲げられる第II族元素である亜鉛(Z
n)やマグネシウム(Mg)のイオンを適量注入するい
わゆるイオン注入を施し、然る後適宣熱処理を施すこと
によりn形半導体領域内にp形の伝導形を有する化合物
半導体層を形成することが出来る。一方、n形の伝導形
を呈する III−V族2元化合物またはそれらの混晶半導
体は、p形半導体層領域内に元素周期律表の第IV族に属
するシリコン(Si)、ゲルマニウム(Ge)、もしく
は第VI族の硫黄(S)やセレン(Se)等の元素をイオ
ン注入すれば容易に得ることが出来る。また、上述のp
形、またはn形化合物半導体層は、イオン注入法に限ら
ず有機金属熱分解気相成長法(MOCVD)法、分子線
エピタィシャル(MBE)法等の気相成長、或はまた液
相エピタキシャル法などの成長法によっても形成でき
る。
The p / n junction can be easily formed by, for example, joining the n-type semiconductor layer on which the input electrode is formed and interposing the p-type semiconductor. For example, GaAs, In
Hall elements using P, indium arsenide (InAs), indium antimonide (InSb), or other III-V group binary compounds or mixed crystal semiconductors thereof are listed in the periodic table of elements. Zinc (Z
It is possible to form a compound semiconductor layer having a p-type conductivity type in an n-type semiconductor region by performing so-called ion implantation in which an appropriate amount of n) or magnesium (Mg) ions are implanted, and then performing appropriate heat treatment. I can. On the other hand, a III-V group binary compound having an n-type conductivity or a mixed crystal semiconductor thereof is a silicon (Si) or germanium (Ge) belonging to Group IV of the periodic table of elements in the p-type semiconductor layer region. Alternatively, it can be easily obtained by ion-implanting an element such as sulfur (S) or selenium (Se) of Group VI. Also, the above p
The n-type or n-type compound semiconductor layer is not limited to the ion implantation method, but is also a vapor phase growth method such as metalorganic pyrolysis vapor phase epitaxy (MOCVD) method, molecular beam epitaxy (MBE) method, or liquid phase epitaxial method. Can also be formed by the growth method.

【0010】Si、Ge等の単体半導体から成るホール
素子に於いても、上記の様な方法でp/n接合を形成す
ることが出来る。但し、これら第VI族の半導体にあって
は上記の III−V族化合物半導体とは異なり、p形層の
形成には第 III族に属する元素を、n形層の形成にはリ
ン(P)、ヒ素(As)等の第V族の元素をイオン注入
するか、或はドーピング(添加)するエピタキシャル成
長法により得られる。
Even in the Hall element made of a single semiconductor such as Si or Ge, the p / n junction can be formed by the above method. However, in these Group VI semiconductors, unlike the above-mentioned III-V group compound semiconductors, elements belonging to Group III are used for forming the p-type layer, and phosphorus (P) is used for forming the n-type layer. , An arsenic (As) or other group V element is ion-implanted or doped (added) to obtain an epitaxial growth method.

【0011】更に、GaAsから成るホール素子をイオ
ン注入法を利用して得る場合を例に挙げ、本発明に説明
を加える。従来と同様GaAsから成るホール素子を得
るには半絶縁性のいわゆる高抵抗のGaAs単結晶を基
板として用いる。先ずこの高抵抗GaAs基板表面の素
子を形成する領域以外、即ち入・出力電極部、感磁部と
なる領域以外の領域を、公知のフォトリソグラフィー
法、エッチング法等に従って一般的なレジスト剤、酸化
ケイ素(SiO2 )、窒化ケイ素(SiN)などの膜で
被覆する。然る後、GaAsに対しn形不純物となるS
iイオンを適量注入する。次に、上述の素子の機能部と
なる領域以外を被覆していた膜材をエッチングにより除
去する。その後、Siイオンが注入されたGaAs結晶
基板に適宣熱処理を施し、注入されたSiイオンを電気
的に活性化させてn形GaAsから成る感磁部、及び各
々一対をなす入力並びに出力電極部を形成する。次にS
iをイオン注入した一対をなす入力電極部の片方に、p
/n接合を成す様に例えばZnイオンなどのp型不純物
を注入する。然る後に再び適宣熱処理を施し、注入され
たZnイオンを電気的に活性化してp/n接合を形成す
る。最終的には各々一対をなす入・出力電極部に金ーゲ
ルマニウム合金等の、n形GaAsに対し、オーミック
接触をもたらす電極材を真空蒸着法などにより被着して
電極を形成すれば、本発明に係わるホール素子が得られ
る。
Further, the present invention will be described by taking as an example the case where a Hall element made of GaAs is obtained by utilizing the ion implantation method. To obtain a Hall element made of GaAs as in the conventional case, a semi-insulating so-called high-resistance GaAs single crystal is used as a substrate. First, a region other than a region where elements are formed on the surface of the high-resistance GaAs substrate, that is, a region other than a region that serves as an input / output electrode portion and a magnetic sensitive portion is subjected to a general resist agent and oxidation according to a known photolithography method, etching method, or the like. Cover with a film of silicon (SiO 2 ), silicon nitride (SiN), or the like. After that, S that becomes an n-type impurity for GaAs
Implant an appropriate amount of i ions. Next, the film material that covers the area other than the functional portion of the element is removed by etching. Thereafter, the GaAs crystal substrate into which Si ions are implanted is subjected to appropriate heat treatment to electrically activate the implanted Si ions to form a magnetic sensitive portion made of n-type GaAs, and a pair of input and output electrode portions. To form. Then S
i is ion-implanted into one of the pair of input electrode portions,
A p-type impurity such as Zn ions is implanted so as to form a / n junction. After that, appropriate heat treatment is performed again to electrically activate the implanted Zn ions to form a p / n junction. Finally, if electrodes are formed by depositing an electrode material, such as gold-germanium alloy, which causes ohmic contact with n-type GaAs on each pair of input / output electrode portions by vacuum deposition or the like, the The Hall element according to the invention can be obtained.

【0012】上記の例ではn形不純物のSiを先ず注入
し、活性化のための熱処理を施し、然る後、p形不純物
のZnイオンを注入し、熱処理する工程手順であった
が、本発明に係わるホール素子にあっては別段この手順
に限定されることはなく、上記の例とは逆にp形不純物
を注入し熱処理を施した後、n形不純物を注入し熱処理
を実施しても良い。また、各イオンの注入の度に熱処理
を施すのではなく、p形、n形不純物を先ずイオン注入
し、然る後同時に熱処理を行う簡略化された工程でも本
発明に係わるホール素子が得られる。
In the above example, the n-type impurity Si is first implanted, and the heat treatment for activation is performed, and then the Zn ions of the p-type impurity are implanted and the heat treatment is performed. The Hall element according to the present invention is not particularly limited to this procedure. Contrary to the above example, p-type impurities are implanted and heat-treated, and then n-type impurities are implanted and heat-treated. Is also good. Further, the Hall element according to the present invention can be obtained by a simplified process in which p-type and n-type impurities are first ion-implanted and then heat-treated at the same time, instead of performing heat-treatment each time each ion is implanted. .

【0013】以上、化合物半導体の例としてGaAs
を、並びに単体半導体の例としてSiを例に挙げて本発
明に係わる新たなホール素子につき概略を記したが、I
nP、InAs、InSb或はそれらの混晶を材料とし
ても、またGeの様なSi以外の単体半導体に於いても
上述の方法により本発明に記載のp/n接合をもってな
る新たなホール素子を得ることは可能である。
As described above, GaAs is used as an example of the compound semiconductor.
, And Si as an example of a single semiconductor, the outline of the new Hall element according to the present invention is described.
Even if nP, InAs, InSb, or a mixed crystal thereof is used as a material, or a single semiconductor other than Si such as Ge, a new Hall element having the p / n junction according to the present invention is formed by the above-described method. It is possible to get.

【0014】[0014]

【作用】本発明に記載のp/n接合を一対の入力電極の
内、一方の入力電極にp/n接合を設けることにより、
ホール素子を動作させるための動作・制御電圧等の入力
には何等支障を与えず、許容を越える動作電圧の入力に
対しては機能破壊から素子を防護する作用が得られる。
By providing the p / n junction described in the present invention to one of the pair of input electrodes, the p / n junction is provided.
The input of the operation / control voltage for operating the Hall element is not hindered, and the input of an operating voltage exceeding the permissible level can protect the element from functional breakdown.

【0015】[0015]

【実施例】以下、本発明に係わるホール素子について、
実施例を基に詳細に説明する。 (実施例1)ここでは、 III−V族2元化合物であるG
aAsを母体材料とするホール素子を例に挙げ説明を加
える。先ず、本発明に係わるホール素子の平面の概略図
を図2に示し、断面図を図3に示す。先に記載した如
く、GaAsから成るホール素子にあってはクロム(C
r)などの遷移金属または酸素(O2 )などを添加して
なる、或は無添加(アンドープ)の半絶縁性を有する高
抵抗のGaAs結晶を基板として使用する。本実施例で
は比抵抗が約107 Ω・cmの無添加の半絶縁性GaA
s単結晶を基板204 として使用した。また、基板
204 の面方位は(100)±0.5度の範囲内にあ
った。但し、使用する基板の比抵抗値並びに面方位共に
上述の値に限定されることはなく、例えば比抵抗が10
6 Ω・cm程度であっても良く、面方位も(100)面
から2度程度傾斜させた方位であっても差し支えはな
い。
EXAMPLES Hereinafter, Hall elements according to the present invention will be described.
A detailed description will be given based on examples. (Example 1) Here, G, which is a III-V group binary compound, is used.
A hall element using aAs as a base material will be described as an example. First, a schematic plan view of a Hall element according to the present invention is shown in FIG. 2, and a sectional view thereof is shown in FIG. As described above, in the Hall element made of GaAs, chromium (C
A high resistance GaAs crystal having a semi-insulating property, which is formed by adding a transition metal such as r) or oxygen (O 2 ) or is not added (undoped), is used as a substrate. In the present embodiment, a non-doped semi-insulating GaA having a specific resistance of about 10 7 Ω · cm is added.
s single crystal was used as the substrate 204. Also the substrate
The plane orientation of 204 was within the range of (100) ± 0.5 degrees. However, the specific resistance value and the plane orientation of the substrate to be used are not limited to the above values, and for example, the specific resistance is 10
It may be about 6 Ω · cm, and the orientation of the plane may be an orientation inclined by about 2 degrees from the (100) plane.

【0016】次に、上述のGaAs単結晶基板 204
表面に感磁部 203、入力電極部 201 及び出
力電極部 202 となるn形の伝導形を呈するGaA
s層を形成すべく、該GaAs結晶 204 表面を一
般的なフォトレジスト材で全面に亘り被覆し、その後公
知のフォトリソグラフィー法及びエッチング法を駆使し
て素子形成領域部に相当する部分(201〜203)の
フォトレジストを選択的に剥離し、同領域に於てGaA
s結晶 204 の表面を露出させた。
Next, the above-mentioned GaAs single crystal substrate 204
GaA that exhibits an n-type conductivity type on the surface to be the magnetic sensing portion 203, the input electrode portion 201, and the output electrode portion 202
In order to form the s layer, the surface of the GaAs crystal 204 is entirely covered with a general photoresist material, and thereafter, a portion (201 to 201) corresponding to an element formation region portion is formed by making full use of a known photolithography method and etching method. The photoresist of 203) is selectively removed, and GaA is removed in the same area.
The surface of the s crystal 204 was exposed.

【0017】然る後、上記の如く加工されたGaAs結
晶 204 を一般のイオン注入装置内に載置し、質量
数28、もしくは29のSiイオンを加速電圧200K
V、ドーズ量2×1012cm-2の条件で上記素子形成領
域(202〜204)に選択的に注入しn形GaAs注
入層を形成した。次いで、マスキング材として利用した
フォトレジスト材を剥離した後、このイオン注入を施し
たGaAs結晶 204 を、所定の分圧のアルシン
(AsH3 )ガスを含む雰囲気内に於て温度850℃で
15分間熱処理した。
After that, the GaAs crystal 204 processed as described above is placed in a general ion implantation apparatus, and Si ions having a mass number of 28 or 29 are accelerated at an acceleration voltage of 200K.
An n-type GaAs injection layer was formed by selectively implanting into the device forming regions (202 to 204) under the conditions of V and a dose amount of 2 × 10 12 cm -2 . Next, after peeling off the photoresist material used as the masking material, the ion-implanted GaAs crystal 204 is heated at a temperature of 850 ° C. for 15 minutes in an atmosphere containing arsine (AsH 3 ) gas at a predetermined partial pressure. Heat treated.

【0018】次に再び該GaAs結晶 204 の表面
全体にフォトレジスト材を塗布し、一対のn形GaAs
から成る入力電極 201 の一方 201−a との
p/n接合を形成するため、p形GaAs層を形成すべ
き該当領域 205 を公知のフォトリソグラフィー法
とエッチング法により加工し、当該p形GaAs形成領
域(205)に在るフォトレジスト材を選択的に除去し
た。然る後、Znイオンを加速電圧100KVで、ドー
ズ量8.0×1013cm-2で注入した。先述の如くフォ
トレジスト材を剥離した後、所定の分圧のアルシンガス
を含む雰囲気中に於て温度650℃で20分間の第2回
目の熱処理をGaAs結晶に施した。
Next, a photoresist material is applied to the entire surface of the GaAs crystal 204 again to form a pair of n-type GaAs.
In order to form a p / n junction with the one 201-a of the input electrodes 201 made of p-type GaAs, a corresponding region 205 in which a p-type GaAs layer is to be formed is processed by a known photolithography method and etching method to form the p-type GaAs. The photoresist material in the area (205) was selectively removed. After that, Zn ions were implanted with an acceleration voltage of 100 KV and a dose of 8.0 × 10 13 cm -2 . After stripping the photoresist material as described above, the GaAs crystal was subjected to the second heat treatment at a temperature of 650 ° C. for 20 minutes in an atmosphere containing a predetermined partial pressure of arsine gas.

【0019】更に、上記Si並びにZnイオンを注入し
たGaAs結晶 204 の表面を、一般的なフォトレ
ジスト材で全面に亘り被覆し、入力電極部 201 と
出力電極部 202 となるn形GaAs層の領域を被
覆しているフォトレジスト材のみを剥離し、同領域(2
01及び202)に於て該n形GaAs層が露出する様
に加工を施した。然る後、n形GaAsとオーミック接
触をもたらす金ーゲルマニウム(Au−Ge)合金を真
空蒸着し、各々一対をなす計4個の入力用電極206
及び出力用電極 207 を構成した。ここではn形の
オーミック電極材料としてGeの含有量が12重量%の
Au−Ge合金を使用したが、Au−Ge合金に於ける
Geの含有量はこれに固定されることはなく、またAu
−Ge合金以外の物質を用いても構わない。
Further, the surface of the GaAs crystal 204 implanted with Si and Zn ions is entirely covered with a general photoresist material to form an n-type GaAs layer region which becomes the input electrode portion 201 and the output electrode portion 202. Only the photoresist material covering the
01 and 202) were processed so that the n-type GaAs layer was exposed. After that, a gold-germanium (Au-Ge) alloy that causes ohmic contact with n-type GaAs is vacuum-deposited, and a total of four input electrodes 206 each forming a pair.
And an output electrode 207. Here, an Au-Ge alloy having a Ge content of 12% by weight was used as the n-type ohmic electrode material, but the Ge content in the Au-Ge alloy is not fixed to this, and Au is not fixed.
A material other than the Ge alloy may be used.

【0020】p形GaAs注入領域 205 には、熱
処理された金ー亜鉛(Au−Zn)合金からなp形Ga
As用のオーミック入力電極 209 を設けた。次
に、図2に示す如くAuからなる配線 208 を、Z
nイオン注入によるp形オーミック電極 209 と入
力用電極 206 のうちp形注入層 205 を設け
てない側の入力電極 206−b に連結させて構成し
た。
In the p-type GaAs implantation region 205, a p-type Ga made of heat-treated gold-zinc (Au-Zn) alloy is formed.
An ohmic input electrode 209 for As was provided. Next, as shown in FIG. 2, the wiring 208 made of Au is connected to Z
The p-type ohmic electrode 209 formed by n-ion implantation and the input electrode 206 were connected to the input electrode 206-b on the side where the p-type implantation layer 205 was not provided.

【0021】(比較例)また、本発明による効果をより
よく対比させるため、本発明に依るp/n接合を含まな
い従来のホール素子を作成した。その手順はp形GaA
s注入層の注入は実施せず、その他はすべて同一とし
た。
Comparative Example Further, in order to compare the effects of the present invention better, a conventional Hall element not including the p / n junction according to the present invention was prepared. The procedure is p-type GaA
The implantation of the s-implanted layer was not performed, and the other conditions were the same.

【0022】表1に本発明に係わるホール素子の特性、
特に耐サージ特性につき従来のホール素子のそれと比較
して纏める。
Table 1 shows the characteristics of the Hall element according to the present invention,
In particular, the anti-surge characteristics will be summarized in comparison with those of the conventional Hall element.

【0023】[0023]

【表1】 [Table 1]

【0024】本発明によるp/n接合の有無に係わら
ず、入力並びに出力抵抗値、積感度、ホール電圧の温度
依存性、ホール電圧の不平衡率の諸特性に顕著な差は認
められなかった。一方、入力電極に瞬時に所定の電圧を
印加する手法で入力電圧に対するサージ耐性を調査した
結果、本発明に係わるp/n接合を設けて成るホール素
子については、同接合を有しない従来のホール素子に比
較し格段に優れたサージ耐性を示した。一例として、p
/n接合を含まない従来のホール素子では、25Vのパ
ルス電圧の印加に対し、被検体の総数8200個の52
%に相当する数の検体が、電極部の破壊に基づくと思わ
れるホール出力電圧の不安定性、入力抵抗値の均一性の
悪化等の以上をもたらした。また、35Vのパルス電圧
の入力では実に83%の数に及ぶ被検体が何等かの電気
的特性に異常を来した。これとは全く逆に本発明に基づ
くp/n接合を入力電極側に有するホール素子にあって
は、35Vのパルス電圧の瞬時入力に対しても被検体総
数7500の内、素子特性上何等かの異常を来したもの
は皆無であった。
Regardless of the presence / absence of the p / n junction according to the present invention, no significant difference was observed in the characteristics of the input and output resistance values, the product sensitivity, the temperature dependence of the Hall voltage, and the unbalance rate of the Hall voltage. . On the other hand, as a result of investigating the surge resistance to the input voltage by the method of instantly applying a predetermined voltage to the input electrode, it was found that the Hall element having the p / n junction according to the present invention has a conventional Hall element without the same junction. Compared to the device, it showed significantly better surge resistance. As an example, p
In the conventional Hall element that does not include the / n junction, when the pulse voltage of 25 V is applied, 52
%, The number of samples caused the instability of the Hall output voltage, the deterioration of the uniformity of the input resistance value, etc., which are considered to be due to the destruction of the electrode part. In addition, when a pulse voltage of 35 V was input, 83% of the subjects had abnormal electrical characteristics. On the contrary, in the Hall element having the p / n junction according to the present invention on the input electrode side, even if the instantaneous input of the pulse voltage of 35 V is applied, there is some difference in the element characteristics among the total number of specimens 7500. None of them had any abnormalities.

【0025】尚、本発明に係わる実施例では、GaAs
半導体を材料とするホール素子を例に挙げたが、本発明
による効果は、InP、InAs、InSbなどの2元
系化合物半導体、並びにSi、Ge等の単体半導体を使
用した場合でも発揮され得るのは明かである。
In the embodiment according to the present invention, GaAs is used.
Although the hall element made of a semiconductor is taken as an example, the effect of the present invention can be exhibited even when a binary compound semiconductor such as InP, InAs, InSb, or a single semiconductor such as Si or Ge is used. Is clear.

【0026】[0026]

【発明の効果】本発明に基づくp/n接合を内蔵したホ
ール素子に於いては、上述の如く耐サージ特性が向上す
るのは明白であり、従来に無い高い信頼性を発揮するホ
ール素子を与える効果をもたらすものである。加えて、
サージ耐性を有する機能を素子に内蔵させることによっ
て、従来の如くサージ吸収機能をもった外部電気回路を
具備させる必要もないため、素子自体を小型化すること
も可能であり、よって、微小領域に於ける磁界センサ
ー、回転センサー等として産業界への応用が図られ、高
信頼性、高精度が要求される制御工学分野等の発展に寄
与するところ大である。
In the Hall element incorporating the p / n junction according to the present invention, it is obvious that the surge resistance is improved as described above, and a Hall element exhibiting a high reliability which has never been obtained is obtained. It has an effect to give. in addition,
By incorporating a function with surge resistance in the element, it is not necessary to provide an external electric circuit having a surge absorbing function as in the conventional case, and therefore the element itself can be downsized, and therefore, in a minute area. It is applied to the industrial field as a magnetic field sensor, rotation sensor, etc., and contributes to the development of the field of control engineering that requires high reliability and high accuracy.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来のホール素子の回路構成例を示す図であ
る。
FIG. 1 is a diagram showing a circuit configuration example of a conventional Hall element.

【図2】本発明に係わるp/n接合を内蔵してなるホー
ル素子の概略を示す平面図である。
FIG. 2 is a plan view showing an outline of a Hall element including a p / n junction according to the present invention.

【図3】図2の平面図をA−A’ラインで切断した断面
構造図である。
FIG. 3 is a sectional structural view of the plan view of FIG. 2 taken along the line AA ′.

【符号の説明】 101・・・・入力電極 102・・・・出力電極 103・・・・感磁部 104・・・・結晶基板 201・・・・入力電極の形成領域 202・・・・出力電極の形成領域 203・・・・感磁部 204・・・・結晶基板 205・・・・p形層の形成領域 206・・・・n形入力電極 207・・・・n形出力電極 208・・・・Au配線 209・・・・p形入力電極[Explanation of reference numerals] 101 ... Input electrode 102 ... Output electrode 103 ... Magnetism sensitive portion 104 ... Crystal substrate 201 ... Input electrode formation region 202 ... Output Electrode forming region 203 ... Magnetosensitive portion 204 ... Crystal substrate 205 ... P-type layer forming region 206 ... N-type input electrode 207 ... N-type output electrode 208. ... Au wiring 209 ... P-type input electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力電極にp/n接合を含んでなること
を特徴とする III−V族化合物半導体磁電変換素子。
1. A III-V compound semiconductor magnetoelectric conversion element, wherein the input electrode includes a p / n junction.
JP33315992A 1992-12-14 1992-12-14 Magnetoelectric conversion element Expired - Fee Related JP3221114B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33315992A JP3221114B2 (en) 1992-12-14 1992-12-14 Magnetoelectric conversion element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33315992A JP3221114B2 (en) 1992-12-14 1992-12-14 Magnetoelectric conversion element

Publications (2)

Publication Number Publication Date
JPH06181348A true JPH06181348A (en) 1994-06-28
JP3221114B2 JP3221114B2 (en) 2001-10-22

Family

ID=18262951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33315992A Expired - Fee Related JP3221114B2 (en) 1992-12-14 1992-12-14 Magnetoelectric conversion element

Country Status (1)

Country Link
JP (1) JP3221114B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557149A (en) * 1994-05-11 1996-09-17 Chipscale, Inc. Semiconductor fabrication with contact processing for wrap-around flange interface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557149A (en) * 1994-05-11 1996-09-17 Chipscale, Inc. Semiconductor fabrication with contact processing for wrap-around flange interface

Also Published As

Publication number Publication date
JP3221114B2 (en) 2001-10-22

Similar Documents

Publication Publication Date Title
US4978938A (en) Magnetoresistor
US5453727A (en) Semiconductor sensors and method for fabricating the same
US6590389B1 (en) Magnetic sensor, magnetic sensor apparatus, semiconductor magnetic resistance apparatus, and production method thereof
US4662060A (en) Method of fabricating semiconductor device having low resistance non-alloyed contact layer
US4926154A (en) Indium arsenide magnetoresistor
Sadwick et al. Schottky barrier heights of n-type and p-type al/sub 0.48/In/sub 0.52/As
EP0194197B1 (en) Heterojunction bipolar transistor and process for fabricating same
JP2793440B2 (en) Magnetic sensor and method of manufacturing the same
KR890009007A (en) Manufacturing method of integrated infrared detector
JP3221114B2 (en) Magnetoelectric conversion element
JP3069545B2 (en) Laminate including compound semiconductor and method of manufacturing the same
JP2003060255A (en) Hall generator and hall ic
EP0375107B1 (en) Improved magnetoresistors
US5117543A (en) Method of making indium arsenide magnetoresistor
JPH0342707B2 (en)
EP0124277B1 (en) Field effect transistor for integrated circuits
Ryu et al. Preparation of Ge-GaAs heterojunctions by vacuum evaporation
JP2597774Y2 (en) Hall element
JP3399053B2 (en) Heterojunction Hall element
JP3287048B2 (en) Heterojunction magnetoelectric transducer
JP3287054B2 (en) Magnetoelectric conversion element
JP2768184B2 (en) Manufacturing method of magnetoelectric conversion element
JP2600682Y2 (en) Heterojunction Hall element
JPH03240281A (en) Gaas hall element
JP3223613B2 (en) Magnetoelectric conversion element and method of manufacturing the same

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100817

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees