JPH06180595A - Sound and image processor - Google Patents

Abstract

PURPOSE:To sensuously grasp sound volume control by applying register values according to attenuation widths of a variable resistor circuit incorporated in the sound and image processor and setting them so that the attenuation widths and register values correspond fixedly to each other. CONSTITUTION:The attenuation characteristics of the variable resistor circuit have the attenuation width sectioned by 1dB for four steps from the maximum sound volume and then by 2dB for following four steps and the maximum attenuation quantity is 12dB. In this case, more register values are provided and a register value 1 is applied to attenuation width of 1dB. In the four steps of the low order, the attenuation width is 2dB, so the two register values are made to correspond to the attenuation widths. Consequently, attenuation quantities can easily be known from the set values of registers. Further, the circuit constitution is sometimes varied in attenuation quantity from -10dB and -12dB to -10dB and -11dB. In this case, register values 3 and 2 are made to correspond to -10dB and a register value 1 is made to correspond to -11dB, thereby facilitating adjustments.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voice image processing apparatus having a voice data output function.

[0002]

2. Description of the Related Art Currently, a digital system is predominant as a sound source. In the digital method, all audio signals are obtained as numerical values, and waveforms can be easily prepared by adding, subtracting, multiplying, and dividing. Computers are used because high-speed data processing capability is required to perform waveform synthesis by calculation. To obtain a sound source, there is also a method of generating a sound by creating a waveform by programming, but in order to obtain a sound source with high sound quality, an intended analog sound is often converted into a digital signal.

To digitize a voice signal, a pulse code modulation method (PC
M) is used. PCM is a method for obtaining digital data by sampling an analog signal at regular time intervals, quantizing a measured value, and converting the obtained numerical value into a binary number.

Differential PCM (DPCM) improved from PCM
Is a method in which the amount of data is reduced by taking the difference between the values of adjacent samples and performing quantization. Adaptive difference PCM (ADP
CM) further compresses the data by reducing the sampling pitch when the difference is large and increasing the pitch when the difference is small, thereby minimizing sound quality damage and using a smaller amount of data. It reproduces the sound.
The PCM data has a small data amount due to compression / expansion performed by conversion of scale level vs. scale value and conversion of ADPCM data vs change amount vs level increase / decrease value.
Interconverted with PCM data.

When a game machine is cited as an audio image processing apparatus for outputting a sound, a small-sized programmable sound generator (PSG) having a small amount of data is first used. The PSG generates a voice waveform created by performing amplitude change and frequency modulation by calculation from waveform data of a certain period given by control of a central processing unit (CPU). In some cases, noise is created by directly generating a simple waveform. PSG audio output is easy to control, but it is difficult to obtain a free sound.

As a sound source for obtaining a free sound, the ADPCM system which can obtain a high quality sound is adopted.
The CPU reads the audio data that is written in advance in the form of ADPCM data in the attached storage device, and AD
The PCM decoder refers to the scale value from the scale level, expands the data, and reproduces the sound. The ADPCM decoder in the voice generation mechanism has a built-in synchronization signal generation circuit and produces a transfer rate equal to the sampling rate at the time of sound source production. The PCM data is reproduced according to the transfer rate set by the synchronization signal and output as voice.

In the voice image processing apparatus, PSG, ADPCM
In addition to a sound source whose output is controlled by a CPU or the like, an external sound device is connected to obtain a high-quality sound output. For example,
Compact disc (CD) as a storage medium for game software
In the game device that introduced the
High quality sound is obtained with M sound source.

The volume function of the sound source can be roughly divided into an analog signal volume and a digital signal volume. The volume of the analog signal is generally of the voltage control type. The volume of the digital signal is
In many cases, it also serves as a D / A converter that changes the conversion ratio in bit data units during analog conversion.

The volume of each audio data is adjusted through a volume circuit and is output as an analog signal through a mixing circuit. The output attenuation is generally N (dB)
= 20 log (I ₁ / I ₀ ). Here, I ₁ is the magnitude of the output signal, and I ₀ is the magnitude of the input signal.

A volume value is set by dividing an interval from the maximum volume to the minimum volume of zero attenuation into an appropriate attenuation width, and the set volume value corresponds to the register value in a one-to-one correspondence. FIG. 10 is an explanatory diagram showing an example of a conventional volume register. In this example, the attenuation width is divided from the maximum volume by 1 dB in 4 steps and by 2 dB in the following 4 steps, and the maximum attenuation amount is 12 dB. As shown in the figure, register values 0 to 7 are associated with eight volume values.

[0011]

As described above, in the audio data output unit of the audio image processing apparatus, the volume circuit is provided with a register, and the volume is controlled by the value set in the register. As can be seen from the expression for calculating the amount of attenuation, the volume changes logarithmically with the strength of the sound signal.

The volume circuit, which makes it easy for the user to control the volume, has a constant dB by the logarithmic curve.
It is possible to obtain an amplification or attenuation width that is equally divided in units. By setting the register value for each volume value, the register value corresponds to the equally divided attenuation width.
The volume circuit, in which the register value is relative to the attenuation width, makes it easy to grasp the volume and control the volume easily.

However, depending on the characteristics of the volume circuit, it does not have an attenuation width that is equally divided by a logarithmic curve.
It is difficult to provide a constant attenuation width near the maximum and minimum volumes. As shown in FIG. 10, even when the attenuation width is not constant, the register value is determined on a one-to-one basis according to each volume value, and the relationship between the register setting value and the attenuation amount is not linear. Therefore, it is difficult for the user to intuitively know the attenuation amount from the set value of the register.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a volume control register in a sound and image processing apparatus in which the relationship between the register value and the attenuation amount is linear, and to provide a volume circuit in which the volume control can be grasped intuitively. And

[0015]

In order to solve the above problems, according to the present invention, a register value is applied according to the attenuation width of a volume circuit incorporated in an audio image processing apparatus so that the attenuation width and the register value are constant. Set to correspond. Since the change of the attenuation width and the register value becomes constant, the set value of the register and the attenuation amount have a linear relationship. It becomes easy to intuitively grasp the attenuation amount from the set value of the register.

The volume circuit of the present invention will be described with an example. FIG. 1 is an explanatory diagram showing an example of a volume register of the present invention. The attenuation characteristic of the volume circuit itself is the same as that of the conventional one shown in the figure, and the attenuation width is divided into 1 dB by 4 dB from the maximum volume and 2 dB by the following 4 steps, and the maximum attenuation amount is 12 dB. There is. The present invention has more register values, 1
A register value of 1 is applied to the attenuation width of dB. The lower four steps correspond to two register values because the attenuation width is 2 dB each.

Since the register value and the attenuation width are constant as described above, it is easy to intuitively know the attenuation amount from the set value of the register. Further, the attenuation width may be changed depending on the circuit configuration. In FIG. 1, the attenuation amount is −10.
Where it was dB and -12 dB, it was -10 dB and -1.
There is an example that changes to 1 dB. In this case, -10
Adjustment is easy by associating the register values 3 and 2 with dB and the register value 1 with −11 dB.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, an audio image processing apparatus using an audio data output unit will be described. Figure 2
FIG. 1 shows a block diagram of an audio image processing apparatus as an embodiment of the present invention.

A game software recording medium such as a CD-ROM,
32-bit CPU, control unit mainly for image / sound data transfer control and interface of each device,
The image data expansion / conversion unit, the image data output unit, the audio data output unit, the video encoder unit, the VDP unit, and the like. K-RAM, M-RAM, R-RAM, V-RA dedicated to each unit
It has a memory such as M.

FIG. 3 shows a block diagram of an audio data output unit constituting an audio image processing apparatus as an embodiment of the present invention. This audio data output unit incorporates a 6-channel programmable sound generator (PSG), left and right 2-channel ADPCM decoders # 1 and # 2, and an audio data output unit from a compact disc sound source as an external audio device. In the example, ADPCM
A volume circuit that controls the decoder output and the PSG output, and the attenuation width and the register value are made to correspond linearly.

ADPCM audio data is transferred after the control unit buffers it in K-RAM. The basic sampling frequency of the ADPCM decoder is 31.47 kHz, 15.73 kHz, 7.87 kHz
It is also possible to choose a sampling frequency of z, 3.93 kHz. The data set is 4 bits (the most significant 1 bit is a code), and the transfer unit is 1 byte.

In the audio image processing apparatus of the embodiment of the present invention,
Among the operations of the ADPCM decoder, the audio volume and sampling frequency, soft reset, and overall PSG operations are set by the CPU writing to each register.

The registers inside the ADPCM decoder will be described below. FIG. 4 is an explanatory diagram of a register that specifies an ADPCM decoder operation. Set the sampling frequency with 2 bits.

FIG. 5 is an explanatory diagram of a register for setting the audio volume of the ADPCM decoder. One channel of the ADPCM decoder has two volume controls on the left and right, and the maximum output is obtained when 3F (hexadecimal) is set in the registers D5 to D0. -1.5d for register value 1
With the attenuation width of B, the maximum attenuation amount of -52.5 dB can be obtained with the register value 1C (hexadecimal). Register value 1
When the attenuation amount in B (hexadecimal) is −54 dB or less, the output is −∞, and therefore the register values 1B to 00 are silent.

The other registers for controlling the ADPCM decoder are in the control unit. FIG. 6 is an explanatory diagram of a register for controlling the ADPCM decoder in the embodiment of the present invention. The ADPCM decoder reproduction mode register of FIG. 6A specifies the sampling frequency and the data transfer start.

The ADPCM data buffer control register of FIG. 6 (2) specifies the state of the memory in which the audio data to be transferred to the ADPCM decoders # 1 and # 2 is read and the interrupt generation.

The ADPCM start address register of FIG. 6 (3) designates the start address of memory reading.

The ADPCM end address register of FIG. 6 (4) designates the end address of memory reading.

The ADPCM half address register of FIG. 6 (5) gives an instruction of an address for generating an interrupt designated by the data buffer control register.

The ADPCM status register of FIG. 6 (6) indicates the data transfer state of ADPCM.

In this embodiment, a waveform memory system is adopted for the PSG sound source, and a waveform register (5bi) is provided for each channel.
A waveform is generated in accordance with the contents of (T × 32 words form one cycle of waveform). FIG. 7 is an explanatory diagram of each register that sets the operation of the PSG. Each register will be described below.

FIG. 7A shows the channel selection register R0.
FIG. After setting the channel address in R0, R2 to R7 are designated by A0 to A3.

FIG. 7B shows an explanatory diagram of the main volume register R1. R1 controls the volume of the whole sound after mixing the sounds of each channel. LMAL is the left output (LO
UT) and RMAL adjusts the right output (ROUT). Both LMAL and RMAL are 4-bit data, and the maximum volume is obtained when F (hexadecimal) is set for each. It has an attenuation width of -3 dB with respect to the register value 1.

FIG. 7C shows an explanatory view of the frequency fine adjustment register R2. The output frequency is determined in combination with the following frequency coarse adjustment register R3.

FIG. 7 (4) shows an explanatory diagram of the frequency coarse adjustment register R3. The lower 4 bits are the frequency coarse adjustment data,
The output frequency is determined together with R2.

FIG. 7 (5) shows an explanatory diagram of channel ON, direct D / A, and channel volume register R4.
The highest bit relates to the output control of the sound of that channel and the write control to the waveform register, and the second bit from the top relates to the control of direct D / A.

When the most significant bit is "1", the sound of that channel is output (mixed). When this bit becomes "0", the output sound is turned off and data can be written in the waveform register R6.

The direct D / A mode is controlled in the second highest bit. When this bit becomes "1", the address counter of the waveform register is reset and the data signal is directly sent to the D / A converter.

The lower 5 bits are registers for controlling the channel volume. 1F (16
Set to 0 for maximum output. Register value 1
Has an attenuation width of −3 dB.

FIG. 7 (6) shows an explanatory diagram of the LR volume register R5. This is a register that determines the left / right distribution of channel sounds. LAL controls the volume of the left output, and RAL controls the volume of the right output. Both LAL and RAL are 4-bit data, and each has a maximum volume when F (hexadecimal), and has an attenuation width of -3 dB with respect to the register value 1.

FIG. 7 (7) is an explanatory diagram of the waveform register R6. Waveform data for 32 words is stored with 5 bit / word data for each channel, and the entire 32 words form one cycle of the waveform.

FIG. 7 (8) is an explanatory diagram of noise enable and noise frequency register R7. The most significant bit controls switching between noise sound and musical sound. The lower 5 bits are a noise frequency control register, which controls the clock signal input to the noise generator.

FIG. 7 (9) shows an explanatory view of the low frequency oscillator frequency register R8. It controls the frequency of the low frequency oscillator (LFO) for frequency modulation control.

FIG. 7 (10) shows an explanatory view of the LFO control register R9. The LFO is set / reset, and the modulation degree of frequency modulation using the LFO is controlled.

The registers as described above are prepared for each channel. Registers R2-R7 are addressed by A0-A3 and register R0. However, registers R0, R1, R8 and R9 are addressed only by A0 to A3. FIG. 8 shows an explanatory diagram of the relationship between the values of the addresses A0 to A3 and the registers.

Since the PSG volume control used in the embodiment of the present invention has a dynamic range of 45 dB, the left output is the sum of the attenuation amounts of the register R01 (LMAL) + register R04 (AL) + register R05 (LAL). The output on the right side is silent when the sum of the attenuation amounts of the register R01 (RMAL) + register R04 (AL) + register R05 (RAL) is -45 dB or less and the output is -∞.

CP when setting the registers of FIGS. 6 and 7
The timing of writing data from U will be described. FIG. 9 is an explanatory diagram of the input voltage of each terminal of the audio data output unit that receives a signal from the CPU. -C
S and A0 to A4 are a chip select signal and a write address signal from the CPU, -WR is a write signal, and D7 to D0 are data input signals, which are passed through a bus between the CPU and the audio data output device.

Data is written to the register designated by the chip select signal and the address signal from the CPU through D7 to D0 when the write signal -WR is in the low level write mode. Data is latched every time the write signal -WR recovers from writing and rises to the high-level recovery mode (the timing of the dotted line in the figure), and the data held at this time is valid at the trailing edge of the sampling clock pulse. Becomes When data is written twice or more in one sampling cycle, the data written immediately before is valid.

[0049]

As described above, according to the volume circuit in the audio image processing apparatus of the present invention, the register value and the attenuation width have a linear relationship, and the attenuation amount can be intuitively grasped from the register value. I can. When producing a musical tone by programming, it is necessary to grasp the volume from the numerical value of the register, and the volume circuit of the present invention facilitates the musical tone production. In addition, even if the circuit has attenuation characteristics that do not have evenly-spaced attenuation widths, by applying register values to equal attenuation widths, not only can the volume be grasped, but also when the attenuation characteristics change due to the circuit configuration. There is an effect that it can be dealt with easily.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of a volume register of the present invention.

FIG. 2 is a block diagram of an audio image processing apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram of an audio data output unit according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a register that specifies an operation of an ADPCM decoder.

FIG. 5 is an explanatory diagram of a register for setting a sound volume of the ADPCM decoder.

FIG. 6 is an explanatory diagram of a register for controlling an ADPCM decoder.

FIG. 7 is an explanatory diagram of each register that sets the PSG operation.

FIG. 8 is an explanatory diagram of a relationship between PSG addresses A0 to A3 and registers.

FIG. 9 is an explanatory diagram of the input voltage of each terminal of the audio data output unit that receives a signal from the CPU.

FIG. 10 is an explanatory diagram showing an example of a conventional volume register.

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[Procedure amendment]

[Submission date] November 20, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (1)

[Claims] 1. An audio image processing apparatus having an audio output function, comprising means for setting attenuation widths of a volume circuit at equal intervals so as to make a one-to-one correspondence between a register value of a volume control register and an attenuation width. An audio image processing device characterized by the above.