JPH061777B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention provides a diffusion layer in a substrate below a power supply line for a leak current due to a crack near the power supply line, which is often found in a semiconductor integrated circuit device using a plastic package. The present invention relates to a semiconductor integrated circuit device which is designed to prevent this.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly, it relates to a semiconductor integrated circuit device in which a leak current caused by a crack generated in a chip is prevented.

[Problems to be Solved by Prior Art and Invention]

FIG. 4 is an enlarged cross-sectional view of a power supply line portion arranged on the outermost peripheral portion of a conventional semiconductor integrated circuit device (IC chip), and FIG.
The drawing is a plan view of the IC chip having the power supply line shown in FIG. In most cases, a relatively wide power supply line 2 made of metal such as aluminum is provided on the outermost periphery of the IC chip 1. As shown in FIG. 4, the structure of this portion is such that insulating films PSG-1 and PSG-2 made of phosphosilicate glass sandwich the power supply line 2 and a silicon oxide film SiO ₂ is provided below them. Is provided on the ntype substrate layer and is entirely covered with plastic.

In such a structure, the insulating film PS on both sides of the power supply line 2 especially in the case of a plastic package which is often seen recently.
As shown in the figure, cracks C may occur in G-1 and G-2. This portion is a portion where stress due to various factors is the largest and cracks are likely to occur. The cause of cracking is considered to be stress due to the difference in the coefficient of thermal expansion of each material, and it is particularly often found in the stepped portion and the corner portion where the stress is likely to occur. If moisture accumulates in such cracks, a leak current may occur, which adversely affects the performance of the IC chip.

Heretofore, in order to prevent such a leaky defect due to cracks, various problems have been solved by arranging the wiring of the power supply line and reinforcing it with an adhesive in a later step. That is, countermeasures have been taken by making the leak current larger than a certain level defective or making the pattern in which cracks are less likely to occur. However, as the density of the pattern becomes higher, there are many parts that cannot be dealt with anymore by devising such a pattern, and improvement has been demanded.

[Means for solving problems]

The present invention is to provide a semiconductor integrated circuit device which solves the above-mentioned problems, and a means thereof is, in a MOS type semiconductor integrated circuit device, a power source line in contact with a silicon oxide layer in a substrate below the power source line. And a diffusion layer having a predetermined thickness wider than that of the substrate and having a property opposite to that of the substrate, and preventing a leak current caused by a crack generated in an insulating film near the power supply line. To do.

〔Example〕

FIG. 1 is an enlarged cross-sectional view of a power supply line portion arranged in the outermost peripheral portion of a semiconductor integrated circuit device according to an embodiment of the invention, and FIG. 2 is an IC chip having the power supply line shown in FIG. It is a top view. As is clear from FIG. 1, n under the power line 2
The n type substrate is characterized in that the diffusion layer 3 having the same potential as the power supply line 2 is provided on the silicon oxide film SiO ₂ side as shown by the dotted line. In this case, since the substrate is an nn type, a p ⁻ type diffusion layer is provided, but if the substrate is a p type, an n ⁻ type diffusion layer is provided. That is, a diffusion layer having a property opposite to that of the substrate is provided. The diffusion layer 3 is provided below the power line 2 as shown by the dotted line in FIG.
It is provided with a certain width, which is slightly wider than the width of the power supply line. This will be described in more detail with reference to FIGS. 3 (a) and 3 (b).

FIG. 3 (a) shows a case of a general PMOS type, that is, an ntype substrate. In this case, the positive electrode side of the ntype substrate is at Vcc level. The p ^- type diffusion layer 3 forms a diode in the direction indicated by the dotted line in the figure, and the power supply line 2 is connected to the negative side Vcc.
When it is set to (normally the ground side), it has a role of preventing a leak current due to the crack C from the ntype substrate side.

FIG. 3 (b) shows a case of the CMOS type, in which the power supply line 2 is on the positive side Vcc. In this case, the p ^- type diffusion layer 4
If it is already provided, the n ⁺ type diffusion layer 3 may be provided below the power supply line 2. As a result, the leak current due to the crack C from the Vcc side can be prevented. Further, when the p ^- type diffusion layer 4 is not provided, the substrate is on the positive electrode side, so that even if there is a crack C, no leak current naturally flows.

The diffusion layer 3 for blocking the leak current can be formed without increasing the number of steps in the CMOS manufacturing process. That is, the formation of the p ⁻ diffusion layer can be performed by the same process as the formation of the n-channel transistor formation region, and the formation of the n ⁺ diffusion layer can be performed together with the formation of the n-channel transistor.

〔The invention's effect〕

According to the present invention, a leak current, which is often found in plastic packages and caused by cracks near the power supply line, can be prevented by providing a diffusion layer in the substrate below the power supply line.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of a power supply line portion of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view of the power supply line portion of the semiconductor integrated circuit device shown in FIG. 1, and FIG. Is a sectional view showing an example applied to a PMOS, FIG. 3 (b) is a sectional view showing an example applied to a CMOS, FIG. 4 is an enlarged sectional view of a power supply line portion of a conventional semiconductor integrated circuit device, and FIG. FIG. 5 is a plan view of the power supply line portion of the semiconductor integrated circuit device shown in FIG. [Description of Reference Signs] 1 ... Semiconductor integrated circuit device, 2 ... Power supply line, 3 ... Diffusion layer.

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which a semiconductor substrate on which an integrated circuit is formed is housed in a plastic package, the insulating film covering the semiconductor substrate, and formed on the semiconductor substrate via the insulating film. And an extended power line, and formed in the semiconductor substrate located under the power line,
A diffusion layer having a conductivity type opposite to that of the semiconductor substrate, wherein the diffusion layer has a width wider than that of the power supply layer, and extends along the power supply line; A semiconductor integrated circuit device, wherein a leak current flowing from the power supply line to the semiconductor substrate is blocked by the diffusion layer when a crack occurs in the film.