JPH06177328A - Mis transistor for i/o protecting element - Google Patents

Abstract

PURPOSE:To prevent a phenomenon that a junction is destructed before snap- back occurs and a semiconductor integrated circuit can not be operated, by forming a polycrystalline silicon on the field end in contact with a drain diffusion layer. CONSTITUTION:After a field oxide film 109 is formed on a substrate 105, a polycrystalline silicon gate 103B is formed on the end portion of the field oxide film in contact with a drain diffusion layer, in addition to a polycrystalline silicon gate 103A. By the above constitution, the boundary distance between the polycrystalline silicon gate and the drain diffusion layer can be doubled, so that snap-back characteristics restricted by LDD can be compensated without enlarging chip area and increasing the number of manufacturing processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MIS transistor for input / output protection, and more particularly to an MI having improved input / output protection capability.
The present invention relates to an SFET semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional input / output protection device is, as shown in FIG. 3, an N-channel MIS transistor T ₁ having a source terminal and a gate terminal connected to ground and a P-channel MIS transistor having a source terminal and a gate terminal connected to a power supply. It consists T _2, and the contacts M connected N-channel MIS transistors T ₁ and P-channel MIS transistor T ₂ of the drain terminal each other to each other, connect the input and output terminals of the external input and output terminals and the internal circuit to the contact M.

FIG. 4 shows the drain-source voltage dependence of the drain (substrate) current of an N-channel MIS transistor in which the gate terminal is connected to the source terminal.

Further, FIG. 5A shows a plan view of the N-channel MIS transistor T ₁ , and FIG. 5B shows a sectional view of T _{1 taken along} the solid line C-C ₁ shown in FIG. 5A.

The N-channel MIS transistor T ₁ comprises a drain N-type diffusion layer 501, a source N-type diffusion layer 502, a gate polysilicon 503, and a P-type substrate contact 504. When a large positive voltage is applied between the input / output terminal of the semiconductor integrated circuit and the ground, a voltage is applied to the drain N-type diffusion layer 501 of FIG. 5 through the contact M shown in FIG.
When this voltage exceeds the voltage BV _DS shown in FIG. 4, the diffusion layer 5
From 01 to the substrate 505, contact 5
It flows toward 04. At this time, since the substrate 505 has a finite resistance, a potential difference is generated so that positive charges flow into the contact 504, and a negative voltage is applied to the substrate 505 from the source N-type diffusion layer 502 connected to the contact 504.

At this time, the contact 50 is formed from the diffusion layer 501.
4 flows over the substrate current I ₁ shown in FIG.
When the negative voltage from 2 to the substrate 505 increases, negative voltage flows from the diffusion layer 502 into the substrate 505 due to this voltage and flows toward the diffusion layer 501. This negative charge is accelerated by a large voltage applied between the diffusion layer 501 and the diffusion layer 502 and collides with neutral silicon atoms to generate a positive charge and a negative charge, and the generated positive charge flows into the contact 504 again. The voltage between the substrate and the substrate 505 is increased. Due to the voltage, more negative charges are generated in the diffusion layer 50.
2 to the substrate 505. Due to such a synergistic effect, a very large current flows through the transistor T ₁ to the contact M.
Flows from to ground.

By utilizing this phenomenon, a large current is caused to flow when a large voltage is applied to cancel the voltage in the input / output protection element, so that the internal circuit can be protected from the large voltage. Further, when a large negative voltage is applied between the contact M and the ground through the input / output terminal of the semiconductor integrated circuit, the diffusion layer 502 of the transistor T _{1 and} the substrate 5 are connected.
Negative charge flows as a forward current of the diode in 05 to protect the internal circuit. Also between the power supply and the contact M, the P-channel MIS transistor T ₂ has the same function. However, in this conventional MIS transistor for an input protection element, the LDD 5 formed in order to suppress the characteristic variation of the MIS transistor inside the semiconductor integrated circuit due to hot carriers.
If 06 is also formed at the gate end of the MIS transistor for the input / output protection element, the outflow of charges from the drain diffusion layer 501 to the substrate 505 is blocked when a large voltage is applied to the drain terminal, and the source diffusion layer is formed. Before the substrate current necessary to obtain a larger drain current is obtained by causing a potential difference from 502 to the substrate 505 to flow the charges, the drain diffusion layer 501 and the substrate 505 are
Due to the high voltage applied across the broken line 510 in FIG.
There is a problem that junction breakdown occurs between the drain diffusion layer 501 and the substrate 505 indicated by the symbol, the drain terminal and the substrate are short-circuited, and the semiconductor integrated circuit becomes unusable.

As a countermeasure against this, the conventional MI for input / output protection is used.
In the S transistor, an impurity introduction step is added when the LDD 506 is formed, and the LD of the MIS transistor for input / output protection is added.
Only the impurity concentration of D506 is raised to suppress the action of inhibiting the outflow of charges from the drain diffusion layer 501 to the substrate 505 when a high voltage is applied to the drain terminal,
It solves the above problem.

[0009]

In this conventional input / output protection MIS transistor, the phenomenon expected in the input / output protection MIS transistor is hindered by the formation of the LDD, and a junction breakdown is caused between the drain diffusion layer and the substrate. Occurs,
In order to avoid the phenomenon of becoming unusable, it is necessary to add an impurity introduction step, which results in a problem that the manufacturing period of the semiconductor integrated circuit is lengthened and the manufacturing cost is increased.

An object of the present invention is to provide a MIS for input / output protection device.
When the LDD is formed in the transistor and the snapback characteristic is suppressed, the impurity introduction process is increased or the circuit area is increased to prevent the phenomenon that the junction is destroyed before the snapback occurs and the semiconductor integrated circuit becomes unusable. It is an object of the present invention to provide an MIS transistor for an input / output protection element, which can achieve the object without causing any trouble and can prevent a long manufacturing period and an increase in manufacturing cost.

[0011]

An MIS transistor for an input / output protection element of a MISFET semiconductor integrated circuit according to the present invention has a polycrystalline silicon gate on a field end in contact with a drain diffusion layer.

[0012]

The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a MIS transistor for a protection element according to an embodiment of the present invention and a sectional view taken along line AA ₁ thereof.

As shown in FIG. 1, after forming a field oxide film 109 on a substrate 105, a polysilicon gate 103B is formed on the end of the field oxide film in contact with the drain diffusion layer in addition to the polysilicon gate 103A. . With such a configuration, the distance between the boundaries of the polycrystalline silicon gate and the drain diffusion layer can be doubled, and the LDD can be suppressed without increasing the chip area or the number of manufacturing steps. It is possible to compensate for the snapback characteristic that is set.

FIG. 2 shows a protective element M according to another embodiment of the present invention.
FIG. 3 is a plan view of an IS transistor and a cross-sectional view taken along line BB ₁ thereof.

As shown in FIG. 2, the drain diffusion layers 201 are placed on both sides of the source diffusion layer 202, and the polycrystalline silicon gate 203B is formed on the end of the field oxide film connected to the drain diffusion layer 201 and parallel to the channel direction. With such a structure, it is possible to further increase the distance between the drain diffusion layer and the polycrystalline silicon gate per device, and to cause a junction breakdown before the snap-back occurs in the MIS transistor for protection device. The problem that the integrated circuit becomes unusable can be prevented.

[0016]

As described above, the MIS transistor for input / output protection device of the present invention is formed on the end of the field oxide film in contact with the drain diffusion layer in the same manufacturing process as that of the polycrystalline silicon gate of the normal MIS transistor. By providing a polycrystalline silicon gate that is formed, the perimeter of the boundary between the drain diffusion layer and the polycrystalline silicon gate is lengthened,
The current flowing from the drain diffusion layer to the substrate increases and snapback easily occurs. As a result, the MIS transistor for a protection element of the present invention does not hinder the manufacturing process of the semiconductor integrated circuit or increases the circuit area, and the junction breakdown occurs before the snapback occurs due to the formation of the LDD and the semiconductor integration. It is possible to prevent the phenomenon that the circuit becomes unusable.

As a result, the conventional MIS for input / output protection element
It is possible to solve the problems that the manufacturing period of a semiconductor integrated circuit is lengthened and the manufacturing cost is increased due to an increase in the number of steps for introducing impurities into a transistor.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention and its AA ₁
It is sectional drawing in a line.

FIG. 2 is a plan view of another embodiment of the present invention and its BB.
It is a sectional view taken along line ₁ .

FIG. 3 is a circuit diagram of a conventional input / output protection circuit.

FIG. 4 is a current characteristic diagram of an N-channel MIS transistor for an input / output protection element.

5A and 5B are a plan view of a conventional MIS transistor for an input / output protection device and a cross-sectional view taken along line C-C ₁ thereof.

[Explanation of symbols]

101, 201, 501 Drain diffusion layer 102, 202, 502 Source diffusion layer 103, 203, 503 Polycrystalline silicon gate 103B, 203B Polycrystalline silicon gate on field edge 105, 205, 505 Substrate 106, 206, 506 LDD 108, 208, 508 Sidewalls 109, 209, 509 Field oxide film 504 Substrate contact 510 Bonding of drain diffusion layer and substrate that causes junction breakdown

Claims (2)

[Claims] 1. An input / output protection device for an input / output protection device of a MISFET semiconductor integrated circuit, comprising: a wiring material formed at the same time as a gate electrode on a field end in contact with a drain diffusion layer. MIS transistor. 2. In a MIS transistor for an input / output protection device of a MISFET semiconductor integrated circuit, a drain diffusion layer is formed on both sides of a source diffusion layer, and on a field oxide film end parallel to the channel direction and in contact with the drain diffusion layer. An MIS transistor for an input / output protection device, which further comprises a wiring material formed at the same time as the gate electrode.