JPH061772B2 - Wiring layer formation method - Google Patents

Wiring layer formation method

Info

Publication number
JPH061772B2
JPH061772B2 JP61055314A JP5531486A JPH061772B2 JP H061772 B2 JPH061772 B2 JP H061772B2 JP 61055314 A JP61055314 A JP 61055314A JP 5531486 A JP5531486 A JP 5531486A JP H061772 B2 JPH061772 B2 JP H061772B2
Authority
JP
Japan
Prior art keywords
wiring layer
substrate
alloy
formation method
layer formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61055314A
Other languages
Japanese (ja)
Other versions
JPS62211936A (en
Inventor
秀夫 丹羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61055314A priority Critical patent/JPH061772B2/en
Publication of JPS62211936A publication Critical patent/JPS62211936A/en
Publication of JPH061772B2 publication Critical patent/JPH061772B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔概要〕 Al配線層の形成に、通常のSi1〜3%含むAl−S
i合金を用いるとn型基板とのコンタクトではp型固相
エピタキシャル層が成長してコンタクト特性を劣化させ
る。本発明はSi40%以上を含むAl−Si合金と純
Alの2層配線層構造とし、その成長温度の制御を行っ
てコンタクト特性の改善を図つた。
DETAILED DESCRIPTION [Outline] Al-S containing 1 to 3% of normal Si for forming an Al wiring layer
When the i alloy is used, the p-type solid phase epitaxial layer grows in contact with the n-type substrate, which deteriorates the contact characteristics. The present invention has a two-layer wiring layer structure of an Al-Si alloy containing 40% or more of Si and pure Al, and the growth temperature is controlled to improve the contact characteristics.

〔産業上の利用分野〕[Industrial application field]

本発明は、コンタクト特性の良好なるAl配線層の形成
に関する。
The present invention relates to formation of an Al wiring layer having good contact characteristics.

集積回路では配線層の材料としてAlが広く使用されて
いる。然し、純Alを使用すると配線層あるいはコンタ
クト面でスパイク、エレクトロ・マイグレーション、ヒ
ロック等の信頼性を低下させる問題があり、AlにS
i、Cu、リフラクトリ・メタル等を混入させる合金を
用いることが多い。
In integrated circuits, Al is widely used as a material for wiring layers. However, if pure Al is used, there is a problem that the reliability of spikes, electromigration, hillocks, etc. in the wiring layer or the contact surface deteriorates.
An alloy containing i, Cu, refractory metal or the like is often used.

その中でもAlにSiを数%混入させるAl−Si合金
が多く用いられているが、この方法ではコンタクト・ホ
ール内でp型Siの固相エピタキシャル成長の問題があ
り改善が要望されている。
Among them, an Al-Si alloy in which Si is mixed with a few percent of Si is often used, but this method has a problem of solid phase epitaxial growth of p-type Si in a contact hole, and improvement thereof is desired.

〔従来の技術〕[Conventional technology]

電極コンタクト面におけるスパイク、エレクトロ・マイ
グレーション等の防止対策として配線層の材料として
は、AlにSiを1〜3%、Cuを4%以下、あるいは
Ti,Mo,W等のリフラクトリ・メタルを1%以下等
で混入させるAl合金が使用される。
As a material for the wiring layer as a measure for preventing spikes and electromigration on the electrode contact surface, Al is 1 to 3% Si, Cu is 4% or less, or refraction metal such as Ti, Mo, W is 1%. An Al alloy to be mixed in as described below is used.

この中でもコンタクト特性の良好なるAl−Si合金が
最も広く使用されている。
Among these, the Al-Si alloy, which has good contact characteristics, is most widely used.

また配線層の積層の方法としては真空蒸着法、あるいは
スパッタリング法があるが、最近では量産に適している
マグネトロン・スパッタリング法が主として適用されて
いる。
Further, as a method of laminating the wiring layers, there are a vacuum vapor deposition method and a sputtering method, but recently, a magnetron sputtering method suitable for mass production is mainly applied.

マグネトロン・スパッタリング法は、スパッタリング・
レートが大きく、付着力も大きい特徴があるがコンタク
ト・ホールでのステップ・カバレジを良くするため蒸着
時に基板を200〜300℃に加熱することが通常行われる。
The magnetron sputtering method is
Although the rate is large and the adhesive force is large, the substrate is usually heated to 200 to 300 ° C. during the deposition in order to improve the step coverage in the contact hole.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記に述べた、1〜3%Siを混入させるAl−Si合
金ターゲットを用い、基板を例えば200℃に加熱しつつ
マグネトロン・スパッタリング法で配線層を積層する
と、コンタクト・ホール内でp型Siの固相エピタキシ
ャル層成長の問題を生ずる。
Using the Al-Si alloy target in which 1 to 3% Si is mixed as described above, the wiring layers are stacked by the magnetron sputtering method while heating the substrate at 200 ° C., for example. The problem of solid phase epitaxial layer growth arises.

AlはSiに対してp型不純物の特性を示し、Al−S
iの積層工程直後のコンタクト抵抗は低くとも、その後
のウエハー・プロセス、あるいは集積回路として動作時
の加熱等によりコンタクト孔にp型Siの固相エピタキ
シャル層成長が進む。
Al exhibits p-type impurity characteristics with respect to Si, and Al-S
Even though the contact resistance is low immediately after the step of stacking i, the solid phase epitaxial layer growth of p-type Si proceeds in the contact hole due to the subsequent wafer process or heating during operation as an integrated circuit.

このためSi基板のn型領域とのコンタクト面では、コ
ンタクト抵抗が増大し、トランジスタの特性の劣化を伴
う。
Therefore, the contact resistance of the contact surface with the n-type region of the Si substrate increases, and the characteristics of the transistor deteriorate.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は、Siを40%以上含むAl−Si合金膜
の薄膜を基板を非加熱条件にて形成した後、該薄膜上に
実質的純Alの厚膜を積層し、基板側にSiの高濃度領
域を形成したことを特徴とする配線層の形成方法により
解決される。
The above-mentioned problem is that after forming a thin film of an Al-Si alloy film containing Si in an amount of 40% or more on a substrate under non-heating conditions, a thick film of substantially pure Al is laminated on the thin film, and Si on the substrate side. This is solved by a method of forming a wiring layer, which is characterized in that a high concentration region is formed.

〔作用〕[Action]

p型の固相エピタキシャル層の成長は、Al−Siの含
有比率と成長温度の条件により著しく影響を受ける。
The growth of the p-type solid phase epitaxial layer is significantly affected by the conditions of Al—Si content and growth temperature.

本発明では配線層の形成を2層構造とし、Al−Si層
は薄膜成長のみとしてコンタクト面でのスパイクの発生
を防止し、且つp型Siの固相エピタキシャル層の成長
を極力抑え、主配線層としては純Alを用いて最も良い
条件を実験的に求めたものである。
In the present invention, the formation of the wiring layer has a two-layer structure, the Al-Si layer is only a thin film growth to prevent the generation of spikes on the contact surface, and the growth of the solid phase epitaxial layer of p-type Si is suppressed as much as possible. The best condition was experimentally obtained by using pure Al for the layer.

〔実施例〕〔Example〕

本発明による一実施例を詳細説明する。本実施例ではマ
グネトロン・スパッタリング装置を2台使用し、マグネ
トロン・スパッタガンのターゲットとしては、それぞれ
Al−Si合金(Si含有率は45%)と純Alのターゲ
ットを用いた。
An embodiment according to the present invention will be described in detail. In this example, two magnetron sputtering apparatuses were used, and targets of the magnetron sputter gun were Al—Si alloy (Si content rate 45%) and pure Al targets, respectively.

マグネトロン・スパッタリング装置にはそれぞれ予備真
空室を備え、予備真空室は基板を装置の基板支持機構に
着脱するのに真空雰囲気を破らずに行うことを可能とす
るもので、必要に応じて基板の加熱も行うことが出来
る。
Each magnetron sputtering device has a preliminary vacuum chamber, which allows the substrate to be attached to and detached from the substrate support mechanism of the device without breaking the vacuum atmosphere. Heating can also be performed.

本発明の方法では最初の工程では予備真空室で基板は加
熱されることなく、第1のマグネトロン・スパッタリン
グ装置に導入される。
In the method of the present invention, the substrate is introduced into the first magnetron sputtering apparatus without being heated in the preliminary vacuum chamber in the first step.

Al−Si合金よりなるマグネトロン・スパッタガンに
より約400Åの膜厚のAl−Si(45%)の成長を行
う。次いで基板を予備真空室に移し、200℃の予備加熱
を行う。
A magnetron sputter gun made of an Al-Si alloy is used to grow Al-Si (45%) having a film thickness of about 400Å. Then, the substrate is transferred to a preliminary vacuum chamber and preheated to 200 ° C.

次いで、基板を第2のスパッタリング装置に移し、純A
lのスパッタリングを膜厚約9500Åまで行って、予備真
空室より基板を取出す。以上で配線層の積層が完了す
る。
Then, the substrate is transferred to the second sputtering device and pure A
l is sputtered to a film thickness of about 9500Å, and the substrate is taken out from the preliminary vacuum chamber. This completes the stacking of wiring layers.

上記の説明では基板の加熱を予備真空室で行ったが、ス
パッタリング装置の中で基板の裏面より加熱を行っても
同様である。
Although the substrate is heated in the preliminary vacuum chamber in the above description, the same applies when the substrate is heated from the back surface in the sputtering apparatus.

本実施例ではSiの含有比率を45%としたが、40%以上
であればほぼ満足すべき結果が得られる。Siの含有比
率が50%以上にもなるとターゲット自体の製作は困難と
なり、またAlに比して高融点のSiの率が大である
と、スパッタリングの特性も劣化し、成長せる膜質も悪
くなる。
In this embodiment, the Si content ratio is set to 45%, but if it is 40% or more, almost satisfactory results can be obtained. If the Si content exceeds 50%, it will be difficult to manufacture the target itself, and if the ratio of Si having a high melting point is higher than that of Al, the sputtering characteristics will deteriorate and the quality of the grown film will also deteriorate. .

図面では従来の方法でAl−Si(1%)を200℃で加熱し
て一回で成長させる場合(特性曲線I)、本実施例の方
法(特性曲線II)、Al−Si(45%)と純Alの成長を
共に200℃で加熱せる場合(特性曲線III)、本実施例と
同様の方法でSiの含有率を40%とせる場合(特性曲線
IV)にて示す。
In the drawing, when Al-Si (1%) is grown at a temperature of 200 ° C. and grown at one time by the conventional method (characteristic curve I), the method of this embodiment (characteristic curve II), Al-Si (45%) is used. And growth of pure Al are both heated at 200 ° C. (characteristic curve III), and when the Si content is 40% by the same method as in this embodiment (characteristic curve)
IV).

データの測定は、n型Si基板上にコンタクトをそれぞ
れ両端2箇所にもつ配線層を10個形成してこれをシリー
ズ結合して両端の抵抗にを測定した。
The data was measured by forming 10 wiring layers each having contacts at two positions on both ends on an n-type Si substrate and connecting them in series to measure the resistance at both ends.

縦軸はコンタクト抵抗の相対値を示し、横軸は試料を強
制的に500℃に加熱せる時間を表している。
The vertical axis represents the relative value of contact resistance, and the horizontal axis represents the time for forcibly heating the sample to 500 ° C.

本実施例で説明せるAl−Si(45%)を非加熱で、純A
lを加熱条件で2段成長せる特性曲線IIIが最も望まし
い結果を得ている。
Al-Si (45%) explained in this example is not heated and pure A
The most desirable result is obtained by the characteristic curve III in which 1 is grown in two stages under heating conditions.

以上のように、本発明の一実施例では、Alとして、全
く不純物の含まれないアルミニウムを例として説明した
が、多少このアルミニュウムに不純物,混合物が含まれ
ていても構わない。このようなアルミニュウム配線層で
も、同様の問題点に対して同様の作用・効果を及ぼし、
問題点の解決手段となることはもちろんである。
As described above, in one embodiment of the present invention, aluminum containing no impurities at all has been described as an example. However, the aluminum may contain impurities or a mixture to some extent. Even such an aluminum wiring layer exerts the same action / effect to the same problem,
Of course, it can be a solution to problems.

〔発明の効果〕〔The invention's effect〕

以上に説明せるごとく、本発明の配線層の形成方法を用
いることにより良好なるコンタクト特性をもつ配線層を
形成することが可能となった。
As described above, it becomes possible to form a wiring layer having good contact characteristics by using the method for forming a wiring layer of the present invention.

【図面の簡単な説明】[Brief description of drawings]

図面は本発明の方法により形成せる配線層のコンタクト
抵抗特性を比較説明する図を示す。
The drawings show diagrams for comparatively explaining contact resistance characteristics of wiring layers formed by the method of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】Siを40%以上含むAl−Si合金膜の
薄膜を基板を非加熱条件にて形成した後、該薄膜上に実
質的純Alの厚膜を積層し、基板側にSiの高濃度領域
を形成したことを特徴とする配線層の形成方法。
1. A thin film of an Al--Si alloy film containing 40% or more of Si is formed on a substrate under non-heating conditions, and then a thick film of substantially pure Al is laminated on the thin film. A method of forming a wiring layer, characterized in that a high concentration region is formed.
JP61055314A 1986-03-12 1986-03-12 Wiring layer formation method Expired - Lifetime JPH061772B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61055314A JPH061772B2 (en) 1986-03-12 1986-03-12 Wiring layer formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61055314A JPH061772B2 (en) 1986-03-12 1986-03-12 Wiring layer formation method

Publications (2)

Publication Number Publication Date
JPS62211936A JPS62211936A (en) 1987-09-17
JPH061772B2 true JPH061772B2 (en) 1994-01-05

Family

ID=12995097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61055314A Expired - Lifetime JPH061772B2 (en) 1986-03-12 1986-03-12 Wiring layer formation method

Country Status (1)

Country Link
JP (1) JPH061772B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5381094A (en) * 1976-12-27 1978-07-18 Hitachi Ltd Prodduction of silicon-contained aluminum wirings
JPS5524471A (en) * 1978-08-11 1980-02-21 Oki Electric Ind Co Ltd Formation of electrodes
JPH0614511B2 (en) * 1983-05-10 1994-02-23 ソニー株式会社 Crystallization method of semiconductor thin film

Also Published As

Publication number Publication date
JPS62211936A (en) 1987-09-17

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