JPS62211936A - Formation of interconnection layer - Google Patents
Formation of interconnection layerInfo
- Publication number
- JPS62211936A JPS62211936A JP5531486A JP5531486A JPS62211936A JP S62211936 A JPS62211936 A JP S62211936A JP 5531486 A JP5531486 A JP 5531486A JP 5531486 A JP5531486 A JP 5531486A JP S62211936 A JPS62211936 A JP S62211936A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- interconnection layer
- thin film
- pure aluminium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims abstract description 6
- 229910021364 Al-Si alloy Inorganic materials 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims description 11
- 239000007790 solid phase Substances 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 4
- 229910052782 aluminium Inorganic materials 0.000 abstract 4
- 239000004411 aluminium Substances 0.000 abstract 4
- 229910018125 Al-Si Inorganic materials 0.000 abstract 2
- 229910018520 Al—Si Inorganic materials 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 2
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000012071 phase Substances 0.000 description 4
- 229910000676 Si alloy Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010030 laminating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
Aβ配線層の形成に、通常のSi 1〜3%含むAf
fi−Si合金を用いるとn型基板とのコンタクトでは
p型同相エピタキシャル層が成長してコンタクト特性を
劣化させる。本発明は5i40%以」二を含むA7!−
Si合金と純ANの2層配線層構造とし、その成長温度
の制御を行ってコンタクト特+z[の改善を図った。[Detailed Description of the Invention] [Summary] For the formation of the Aβ wiring layer, ordinary Af containing 1 to 3% Si is used.
When a fi-Si alloy is used, a p-type in-phase epitaxial layer grows in contact with an n-type substrate, deteriorating the contact characteristics. The present invention includes 5i40% or more of A7! −
A two-layer wiring structure of Si alloy and pure AN was adopted, and the growth temperature was controlled to improve the contact characteristic +z[.
本発明は、コンタクト特性の良好なるAn配線層の形成
に関する9
集積回路では配線層の材料としてAffか広く使用され
ている。然し、純A7!を使用すると配線層あるいはコ
ンタクト面でスパイク、エレクl−「r・マイグレーシ
ョン、ヒロック等の信頼性ヲ低F、’\せる問題があり
、A1にSi 、C1l 、リフラクトリ・メタル等を
混入せる合金を用いることが多い。The present invention relates to the formation of an An wiring layer with good contact characteristics.Aff is widely used as a material for wiring layers in integrated circuits. However, pure A7! If A1 is used, there are problems such as spikes, electronic migration, and hillocks on the wiring layer or contact surface, reducing reliability. Often used.
その中でもAl2にSiを数%混入せるAff−Si合
金が多く用いられているが、この方法では、:zンタク
ト・ホール内でp型Si の同相エピタキシャル成長の
問題があり改善が要望されている。Among these, an Aff-Si alloy in which several percent of Si is mixed into Al2 is often used, but this method has the problem of in-phase epitaxial growth of p-type Si in the :z contact hole, and an improvement is desired.
電極コンタクト面におけるスパイク、エレクトロ・マイ
グレーション等の防止対策として配線層の材料としては
、A/にStを1〜3%、Cuを4%以下、あるいはT
i、Mo、W等のりフラクトリ・メタルを1%以下等で
混入せるA1合金が使用される。To prevent spikes, electromigration, etc. on the electrode contact surface, the material for the wiring layer should be A/ with 1 to 3% St, 4% or less Cu, or T.
An A1 alloy is used in which a flux metal such as i, Mo, or W is mixed in an amount of 1% or less.
この中でもコンタク1〜特性の良好なるAe−3i合金
が最も広く使用されている。Among these, the Ae-3i alloy, which has good properties of contact 1 and above, is most widely used.
また配線層の積層の方法としては真空蒸着法、あるいは
スパッタリング法があるが、最近ではIX産に適してい
るマグネトロン・スパッタリング法が主として適用され
ている。Further, methods for laminating wiring layers include vacuum evaporation and sputtering, but recently magnetron sputtering, which is suitable for IX production, has been mainly applied.
マグネトロン・スパッタリング法は、スパッタリング・
レートが大きく、付着力も大きい特徴があるがコンタク
ト・ホールでのステップ・カバレジを良くするため蒸着
時に基板を200〜300°Cに加熱することが通常行
われる。The magnetron sputtering method is a sputtering method.
Although it is characterized by a high rate and strong adhesion, the substrate is usually heated to 200 to 300° C. during vapor deposition to improve step coverage in contact holes.
上記に述べた、1〜3%Siを混入せるAl4−3i合
金ターゲットを用い、基板を例えば200°Cに加熱し
つつマグネトロン・スパッタリング法で配線層を積層す
ると、コンタクト・ホール内でp型Siの固相エピタキ
シャル層成長の問題を生ずる。When a wiring layer is laminated by magnetron sputtering while heating the substrate to, for example, 200°C using the Al4-3i alloy target mixed with 1 to 3% Si as described above, p-type Si is formed in the contact hole. This gives rise to the problem of solid phase epitaxial layer growth.
A7!はSt に月してp型不純物の特性を示し、Al
1−3i の積層工程直後のコンタクl−11E抗は低
くとも、その後のウェハー・プr:Iセス、あるい番」
集積回路として動作時の加熱等によりコンタクト孔にp
型Siの同相エピタキシャル層成長が進む。A7! shows the characteristics of p-type impurity compared to St, and Al
Although the contact resistance immediately after the lamination process of 1-3i is low, the subsequent wafer process, or number.
P is generated in the contact hole due to heating etc. during operation as an integrated circuit.
In-phase epitaxial layer growth of Si type progresses.
このためSi基板のn型領域とのコンタクト面では、コ
ンタクト抵抗が増大し、トランジスタの特性の劣化を伴
う。For this reason, contact resistance increases at the contact surface with the n-type region of the Si substrate, accompanied by deterioration of transistor characteristics.
上記問題点の解決のため、第1段階としてSiの混入比
率を40%以上としたAl−3i合金の薄膜を基板を非
加熱の条件で成長させ、次いで第2段階として、基板を
加熱して該基板上に純A1を厚く積層して配線層を形成
することよりなる本発明の方法により解決される。In order to solve the above problems, in the first step, a thin film of Al-3i alloy with a Si content of 40% or more was grown on the substrate without heating, and then in the second step, the substrate was heated. This problem is solved by the method of the present invention, which comprises forming a wiring layer by laminating a thick layer of pure Al on the substrate.
p型の同相エピタキシャル層の成長は、Al−3i の
含有比率と成長温度の条件により著しく影芝!を受ける
。The growth of a p-type in-phase epitaxial layer is significantly affected by the Al-3i content ratio and growth temperature conditions! receive.
本発明では配線層の形成を2層構造とし、Al−3i層
は薄膜成長のみとしてコンタクト面でのスパイクの発生
を防止し、且つp型Siの固相エピタキシャル層の成長
を極力抑え、主配線層としては純Affを用いて最も良
い条件を実験的に求めたものである。In the present invention, the wiring layer is formed in a two-layer structure, and the Al-3i layer is grown only as a thin film to prevent the occurrence of spikes on the contact surface, and the growth of the p-type Si solid-phase epitaxial layer is suppressed as much as possible. The best conditions were experimentally determined using pure Aff as the layer.
本発明による一実施例を詳細説明する。本実施例ではマ
グネトロン・スパッタリング装置を2台使用し、マグネ
トロン・スパッタガンのターゲットとしては、それぞれ
Aj!−3i合金(Si含有率は45%)と純Affの
ターゲットを用いた。An embodiment according to the present invention will be described in detail. In this embodiment, two magnetron sputtering devices are used, and the targets of each magnetron sputter gun are Aj! -3i alloy (Si content: 45%) and pure Aff targets were used.
マグネトロン・スパッタリング装置にはそれぞれ予備真
空室を備え、予備真空室は基板を装置の基板支持機構に
着脱するのに真空雰囲気を破らずに行うことを可能とす
るもので、必要に応じて基板の加熱も行うことが出来る
。Each magnetron sputtering device is equipped with a preliminary vacuum chamber, which allows the substrate to be attached to and removed from the substrate support mechanism of the device without breaking the vacuum atmosphere. Heating can also be performed.
本発明の方法では最初の工程では予備真空室で基板は加
熱されることなく、第1のマグネトロン・スパッタリン
グ装置に導入される。In the method of the invention, in the first step, the substrate is introduced into the first magnetron sputtering device without being heated in a preliminary vacuum chamber.
Al−3i合金よりなるマグネトロン・スパッタガンに
より約400人の膜厚のAIf−3i(45%)の成長
を行う。次いで基板を予備真空室に移し、200℃の予
備加熱を行う。An AIf-3i (45%) film with a thickness of approximately 400 mm is grown using a magnetron sputter gun made of an Al-3i alloy. Next, the substrate is transferred to a pre-vacuum chamber and pre-heated at 200°C.
次いで、基板を第2のスパッタリング装置に移し、純A
1のスパッタリングを膜厚約9500人まで行って、予
備真空室より基板を取出す。以上で配線層の積層が完了
する。The substrate is then transferred to a second sputtering device and pure A
After performing sputtering in step 1 to a film thickness of about 9,500 mm, the substrate was taken out from the preliminary vacuum chamber. This completes the stacking of wiring layers.
上記の説明では基板の加熱を予備真空室で行ったが、ス
パッタリング装置の中で基板の裏面より加熱を行っても
同様である。In the above explanation, the substrate was heated in the preliminary vacuum chamber, but the same effect can be achieved by heating the substrate from the back side in the sputtering apparatus.
本実施例ではStの含有比率を45%としたが、40%
以上であればほぼ満足すべき結果が得られる。In this example, the content ratio of St was 45%, but 40%
With the above conditions, almost satisfactory results can be obtained.
Siの含有比率が50%以上にもなるとターゲット自体
の製作は困難となり、また/lに比して高融点のStの
率が大であると、スパッタリングの特性も劣化し、成長
せる膜質も悪くなる。If the content ratio of Si exceeds 50%, it becomes difficult to manufacture the target itself, and if the ratio of St, which has a high melting point compared to /l, is large, the sputtering characteristics will deteriorate and the quality of the grown film will be poor. Become.
図面では従来の方法でAl−3i(1%)を200°C
で加熱して一回で成長せる場合(特性曲線I)、本実施
例のJJ法(特性曲線II) 、、 A l−8i(4
5%)と純/lの成長を共に200°Cで加熱せる場合
(特+?1曲線III)一本実施例と同様の方法でSi
の含有率を40%と一ロる場合(特性曲線IV)にて示
す。In the drawing, Al-3i (1%) was heated at 200°C using the conventional method.
When the growth can be performed at one time by heating with (characteristic curve I), the JJ method of this example (characteristic curve II)
5%) and pure/l growth at 200°C (special +?1 curve III).
The case where the content is 40% (characteristic curve IV) is shown.
データの測定は、n型Si基板−Lにコンタクトをそれ
ぞれ両端2箇所にもつ配線層を10(IIil形成して
これをシリース結合して両端の抵抗にを測定した。The data was measured by forming 10 (IIil) wiring layers each having contacts at two ends on an n-type Si substrate-L, connecting them in series, and measuring the resistance at both ends.
縦軸はコンタクト抵抗の相対値を示し、横軸は試t′−
1を強制的に500°Cに加熱せる時間を表している。The vertical axis shows the relative value of contact resistance, and the horizontal axis shows the test t'-
1 is forcibly heated to 500°C.
本実施例で説明せるAff−3i(45%)を非加熱で
、純AIを加熱条件で2段成長廿る特性曲線■が最も望
ましい結果を得ている。The most desirable result was obtained with the characteristic curve (2), which is described in this example, in which Aff-3i (45%) is grown in two stages under non-heating conditions and pure AI is grown under heating conditions.
以上に説明せるごとく、本発明の配線層の形成方法を用
いることにより良好なるコンタクト特性をもつ配線層を
形成することが可能となった。As explained above, by using the wiring layer forming method of the present invention, it has become possible to form a wiring layer with good contact characteristics.
図面は本発明の方法により形成せる配線層のコンタクト
抵抗特性を比較説明する図を示す。The drawings are diagrams for comparing and explaining contact resistance characteristics of wiring layers formed by the method of the present invention.
Claims (1)
非加熱条件にて積層した後、基板を加熱して該薄膜上に
純Alの厚膜を積層することを特徴とする配線層の形成
方法。A wiring layer characterized in that a thin film of an Al-Si alloy film containing 40% or more of Si is laminated on a substrate under non-heating conditions, and then a thick film of pure Al is laminated on the thin film by heating the substrate. Formation method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61055314A JPH061772B2 (en) | 1986-03-12 | 1986-03-12 | Wiring layer formation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61055314A JPH061772B2 (en) | 1986-03-12 | 1986-03-12 | Wiring layer formation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62211936A true JPS62211936A (en) | 1987-09-17 |
JPH061772B2 JPH061772B2 (en) | 1994-01-05 |
Family
ID=12995097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61055314A Expired - Lifetime JPH061772B2 (en) | 1986-03-12 | 1986-03-12 | Wiring layer formation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH061772B2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5381094A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Prodduction of silicon-contained aluminum wirings |
JPS5524471A (en) * | 1978-08-11 | 1980-02-21 | Oki Electric Ind Co Ltd | Formation of electrodes |
JPS59205713A (en) * | 1983-05-10 | 1984-11-21 | Sony Corp | Crystallization of semiconductor thin film |
-
1986
- 1986-03-12 JP JP61055314A patent/JPH061772B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5381094A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Prodduction of silicon-contained aluminum wirings |
JPS5524471A (en) * | 1978-08-11 | 1980-02-21 | Oki Electric Ind Co Ltd | Formation of electrodes |
JPS59205713A (en) * | 1983-05-10 | 1984-11-21 | Sony Corp | Crystallization of semiconductor thin film |
Also Published As
Publication number | Publication date |
---|---|
JPH061772B2 (en) | 1994-01-05 |
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