JPH06177046A - Hetero-epitaxial growth method - Google Patents

Abstract

PURPOSE:To reduce a surface pit of a compound semiconductor hetero-epitaxial layer, upgrade the evenness of the layer and reduce carrier concentration in terms of a hetero-epitaxial layer growth method for GaAs or the like on a silicon substrate. CONSTITUTION:A natural oxide film on a silicon substrate is removed and a compound semiconductor low temperature growth layer 2 required to generate a growth core is formed thereon. Then, a first compound semiconductor epitaxial layer 3 is formed at a temperature of 600 deg.C or higher but less than 700 deg.C. A second compound semiconductor epitaxial layer 4, which minimizes the number of pits is formed thereon at a temperature of 700 deg.C or higher where a third compound semiconductor epitaxial layer 5 whose carrier concentration is low, is formed at a temperature lower than 700 deg.C. V/III ratio, annealing temperature, annealing atmosphere and raw material gas of Ga or the like are optimized during the formation of each compound semiconductor epitaxial layer, which makes it possible to reduce the number of pits and enhance the evenness of the surface.

Description

Detailed Description of the Invention

[0001]

The present invention relates to GaAs on a Si substrate.
Etc. of a compound semiconductor epitaxial layer. In recent years, as satellite communication and mobile communication technology have advanced, demand for semiconductor devices such as HEMTs using compound semiconductors such as GaAs as low-noise high-frequency amplifiers has increased, and large-diameter GaAs substrates have been developed to improve their productivity. Development is required.

However, since compound semiconductors such as GaAs are mechanically fragile, they are easily broken during the manufacturing process, and
It is difficult to produce a large diameter single crystal. Therefore,
A method has been developed in which a compound semiconductor layer is grown on a Si substrate that is mechanically strong and is easy to manufacture a large-diameter crystal, and this is used as a compound semiconductor substrate.

[0003]

2. Description of the Related Art Ga is formed on a conventionally known Si substrate.
In the method of growing a compound semiconductor epitaxial layer of As or the like, after heating the Si substrate to remove the natural oxide film formed on the surface of the Si substrate, 400 to 450
An amorphous low temperature growth layer (also called a growth nucleation layer or a growth initial layer) is formed at a low temperature of ℃
A two-step growth method (also referred to as a two-temperature growth method) of raising the temperature to 750 ° C. and growing a compound semiconductor epitaxial layer at that temperature is adopted.

[0004]

However, according to the conventional two-step growth method described above, a large number of pits are formed on the surface of the compound semiconductor epitaxial layer, and the surface unevenness is large, resulting in poor surface flatness. Further, when the growth is performed at a high temperature, the pits are reduced, but there is a problem that the carrier concentration is increased. An object of the present invention is to provide a heteroepitaxial growth method that reduces pits on the surface of a compound semiconductor epitaxial layer, improves flatness, and reduces carrier concentration.

[0005]

In a heteroepitaxial growth method according to the present invention, a compound semiconductor low temperature growth layer is formed on a group IV substrate in heteroepitaxial growth in which a compound semiconductor epitaxial layer is formed on a group IV substrate such as a Si substrate. After forming, the temperature is raised to form a first compound semiconductor epitaxial layer, and then the temperature is further raised to form a second compound semiconductor epitaxial layer,
Then, the step of lowering the temperature to form the third compound semiconductor epitaxial layer was adopted.

In this case, the first compound semiconductor epitaxial layer is formed at 600 ° C. or more and less than 700 ° C., the second compound semiconductor epitaxial layer is formed at 700 ° C. or more, and the third compound semiconductor epitaxial layer is 700 ° C. Can be formed in less than.

In this case, the V / III ratio when the first compound semiconductor epitaxial layer is formed is changed to the V / II ratio when the second compound semiconductor epitaxial layer is formed.
It can be lower than the I ratio.

In this case, the V / III ratio during the growth of the first compound semiconductor epitaxial layer and the V / III ratio during the growth of the second compound semiconductor epitaxial layer are set to the third compound semiconductor epitaxial layer. The V / III ratio is lower than that in the case of, for example, 20 or less.

In the heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate such as a Si substrate, the compound semiconductor low-temperature growth layer is formed on the group IV substrate and then heated to raise the temperature of the first compound semiconductor. An epitaxial layer is formed, and the first compound semiconductor epitaxial layer is formed at a point A at a reaction tube internal pressure of 76 Torr, a group V source gas partial pressure of 0.35 Torr, and a reaction tube internal pressure of 760.
Torr, point B of group V source gas partial pressure 0.6 Torr,
Reaction tube internal pressure 760 Torr, Group V source gas partial pressure 5.7
Annealing is performed under the condition of a region surrounded by a point C of Torr and a point D of a reaction tube internal pressure of 76 Torr and a group V source gas partial pressure of 1.3 Torr to improve crystallinity and surface flatness of the first compound semiconductor epitaxial layer. Adopted a process to improve.

In the heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate such as a Si substrate, a compound semiconductor low temperature growth layer is grown on this group IV substrate and a first compound semiconductor epitaxial layer is grown thereon. The layer is grown from triethylgallium as a raw material at a temperature higher than that for growing the compound semiconductor low-temperature growth layer, and the second compound semiconductor epitaxial layer is grown at a temperature higher than that for growing the first compound semiconductor epitaxial layer. The process of growing layers was adopted.

In the heteroepitaxial growth method of forming a compound semiconductor epitaxial layer on a group IV substrate such as a Si substrate, a compound semiconductor low temperature growth layer is first grown on this group IV substrate, and then a compound semiconductor epitaxial layer is grown. After that, the compound semiconductor epitaxial layer is polished and flattened, then annealed at a temperature higher than the temperature for growing the compound semiconductor epitaxial layer, and then the compound semiconductor epitaxial layer is grown at a temperature lower than the annealing temperature. The process of doing is adopted.

In addition, in the heteroepitaxial growth method of forming a compound semiconductor epitaxial layer on a group IV substrate such as a Si substrate which is tilted from (100) in the [011] direction, the native oxide film is removed by heating the group IV substrate. This is performed at 875 ° C. or lower in an atmosphere containing a Group V element.
A step of forming a compound semiconductor low-temperature growth layer on a group V substrate and then raising the temperature to form a compound semiconductor epitaxial layer, and during the growth of the compound semiconductor epitaxial layer,
Alternatively, a step of performing annealing after growth at a temperature equal to or lower than the step of removing the natural oxide film of the Si substrate is adopted.

Further, in the heteroepitaxial growth method of forming a compound semiconductor epitaxial layer on a group IV substrate such as a Si substrate, the reaction tube and the parts in the reaction tube are exposed to an atmosphere containing oxygen before starting the growth of the compound semiconductor epitaxial layer. The process of annealing is adopted.

[0014]

When the first compound epitaxial layer is formed at a relatively low temperature after the formation of the compound semiconductor low temperature growth layer as in the present invention, the growth nucleus of the compound semiconductor concentrates and grows in a lump, so-called coalescence is suppressed. You can
By forming the second compound semiconductor epitaxial layer at a temperature higher than the formation temperature of the first compound semiconductor epitaxial layer, it is possible to suppress pits and improve flatness.

Further, when the second compound semiconductor epitaxial layer is formed at a high temperature, the carrier concentration increases, but when the temperature is lowered to form the third compound semiconductor epitaxial layer, the carrier concentration of this layer is suppressed. be able to.

Further, if the V / III ratio in the case of forming the first compound semiconductor epitaxial layer is made lower than the V / III ratio in the case of forming the second compound semiconductor epitaxial layer, the cause is currently clarified. Not done, but the number of pits will decrease.

Further, after forming the compound semiconductor low-temperature growth layer on the group IV substrate such as the Si substrate, the temperature is raised to form the first compound semiconductor epitaxial layer, and the first compound semiconductor epitaxial layer is subjected to the pressure in the reaction tube. 76 Torr, point A of group V source gas partial pressure 0.35 Torr, reaction tube internal pressure 760 Torr, group V source gas partial pressure 0.6 Torr Point B, reaction tube internal pressure 760 Torr, group V source gas partial pressure 5.7 Torr Point C, the pressure in the reaction tube is 76 Torr,
When the annealing is performed under the condition of the region surrounded by the group D source gas partial pressure of 1.3 Torr and the point D, the crystallinity and surface flatness of the first compound semiconductor epitaxial layer can be improved.

In the case where a compound semiconductor low temperature growth layer is grown on a group IV substrate such as a Si substrate, a first compound semiconductor epitaxial layer is grown on the compound semiconductor low temperature growth layer, and a compound semiconductor low temperature growth layer is grown from triethylgallium as a raw material. Growing at a temperature higher than the temperature can reduce roughness of the compound semiconductor low temperature growth layer.

In the heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate such as a Si substrate, a low temperature compound growth layer is first grown on this group IV substrate, and then a compound semiconductor epitaxial layer is grown. After that, the compound semiconductor epitaxial layer is polished to be flattened, and then annealed at a temperature higher than the temperature for growing the compound semiconductor epitaxial layer, for example, 800 ° C. or higher, and the compound semiconductor epitaxial layer is further annealed at a temperature lower than the annealing temperature. Growing the layer can reduce the pit density.

In addition, in the heteroepitaxial growth method of forming a compound semiconductor epitaxial layer on a group IV substrate such as a Si substrate inclined from the (100) direction to the [011] direction, the native oxide film is removed by heating the group IV substrate. This is performed at 875 ° C. or lower in an atmosphere containing a Group V element.
A step of forming a compound semiconductor low-temperature growth layer on a group V substrate and then raising the temperature to form a compound semiconductor epitaxial layer; and annealing the compound semiconductor crystal epitaxial layer during or after the growth. When the temperature is lower than the step of removing the natural oxide film, the flatness and crystallinity of the compound semiconductor crystal epitaxial layer can be improved.

When the reaction tube and the parts inside the reaction tube are annealed in an atmosphere containing oxygen before starting the growth of the compound semiconductor layer, the GaAs component is deposited on the inner wall of the chamber and drops on the growth layer to contaminate it. Can be prevented.

[0022]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIG. 1 shows G grown according to the first embodiment.
It is a structure explanatory view of an aAs heteroepitaxial layer. In this figure, 1 is a Si substrate, 2 is a compound semiconductor low temperature growth layer, 3 is a first compound semiconductor epitaxial layer, 4 is a second compound semiconductor epitaxial layer, and 5 is a third compound semiconductor epitaxial layer.

The GaAs heteroepitaxial layer formed according to the first embodiment, as shown in this figure,
A compound semiconductor low temperature growth layer 2 made of GaAs is formed on a Si substrate 1, and MOCVD (metal) is formed thereon.
organic chemical vapor de
The first compound semiconductor epitaxial layer 3 made of GaAs and the second compound semiconductor made of GaAs
The compound semiconductor epitaxial layer 4 and the third compound semiconductor epitaxial layer 5 made of GaAs are formed. The GaAs heteroepitaxial layer shown in this figure is formed by the following growth method.

FIG. 2 is a growth temperature profile of the GaAs heteroepitaxial growth method of the first embodiment. With reference to this growth temperature profile, Ga of this example
The As heteroepitaxial growth method will be described.

First stage (see a in FIG. 2) The Si substrate 1 is heat-treated at 1000 ° C. for about 10 minutes in a reducing atmosphere to remove the natural oxide film.

Second Step (See B in FIG. 2) A thickness 10 for forming growth nuclei by MOCVD on the Si substrate 1 at a temperature of 350 to 500 ° C. for 5 minutes.
A compound semiconductor low temperature growth layer 2 made of 0Å GaAs is grown.

Third stage (see C in FIG. 2) Further, the temperature is raised to 600 ° C. or higher and lower than 700 ° C.
By MOCVD for 0.5 min
First compound semiconductor epitaxial layer 3 made of aAs
To grow. By growing in this temperature range, coalescence can be suppressed and flatness can be improved.

Fourth stage (see D in FIG. 2) Then, the temperature is raised to 700 ° C. or higher and MOC is performed for about 40 minutes.
The second compound semiconductor epitaxial layer 4 made of GaAs and having a thickness of 2.0 μm is grown by VD.
The pits can be reduced by forming the second compound semiconductor epitaxial layer made of GaAs at 700 ° C. or higher.

Fifth step (see E in FIG. 2) Then, the temperature is lowered to less than 700 ° C., and MOC is performed for about 10 minutes.
By VD, the third compound semiconductor epitaxial layer 5 made of GaAs and having a thickness of 0.5 μm is grown.

FIG. 3 is a photomicrograph of the surface of the GaAs epitaxial layer according to the conventional and the growth method of the first embodiment, where (A) shows the case of the conventional MOCVD growth.
(B) shows the surface when grown by the growth method of the first embodiment. These photographs are atomic force microscope (A
FM) photograph. FIG. 3A shows the surface of a GaAs layer grown by conventional MOCVD, and 20 pits are observed. Further, FIG. 3B shows the surface of the GaAs layer by the growth method of the present invention, and only 4 pits are observed.

FIG. 4 is a comparison diagram of the number of pits on the surface of the GaAs epitaxial layer by the conventional and the growth method of the first embodiment. The horizontal axis of this figure shows a GaAs epitaxial layer grown by the conventional two-step growth method (growth temperatures of 650 ° C. and 700 ° C.) and the four-step growth method of the first embodiment.
The vertical axis represents the number of pits on those surfaces.

As shown in this comparative diagram, in the conventional two-step growth method, the number of pits is the largest when the growth temperature is 650 ° C., and it is greatly reduced when the growth temperature is 700 ° C. It is observed that the number of pits is reduced to a fraction by the inventive four-step growth method.

FIG. 5 is a comparison diagram of the surface flatness of the GaAs epitaxial layer by the conventional and the growth method of the first embodiment. The horizontal axis of this figure shows the GaAs epitaxial layers grown by the conventional two-step growth method (growth temperatures of 650 ° C. and 700 ° C.) and the four-step growth method of the first embodiment, and the vertical axis shows the flatness of their surface. Shows the standard deviation value (nm) of irregularities measured by an atomic force microscope. As a matter of course, the smaller the standard deviation value, the smaller the surface irregularities and the better the flatness.

As shown in this comparative diagram, in the conventional two-step growth method, the flatness is poor when the growth temperature is 650 ° C., and it is slightly improved when the growth temperature is 700 ° C. It can be seen that the flatness is remarkably improved by the four-step growth method.

FIG. 6 shows the Ga according to the growth method of the first embodiment.
It is a relational diagram of the growth temperature of As epitaxial layer and the number of pits. The horizontal axis of this figure shows the growth temperature of the GaAs epitaxial layer which is the third compound semiconductor epitaxial layer, and the vertical axis shows the number of pits. According to this relationship diagram, it is observed that the number of pits decreases as the growth temperature of the uppermost GaAs epitaxial layer decreases, and in particular, the number of pits decreases below 700 ° C.

In the above embodiment, the case of growing a GaAs epitaxial layer has been described, but for example, GaAs, AlAs, InAs, GaP, AlP,
In the growth of other compound semiconductor heteroepitaxial layers such as InP and their mixed crystals, the same effect as described above can be obtained.

(Second Embodiment) In the heteroepitaxial growth method of the compound semiconductor of the first embodiment, S
Compound semiconductor low temperature growth layer 2 made of GaAs, first compound semiconductor epitaxial layer 3 made of GaAs, second compound semiconductor epitaxial layer 4 made of GaAs, and third compound semiconductor epitaxial made of GaAs on the i substrate 1. Layer 5 was all grown at the same V / III ratio (see Figures 1 and 2).

In the heteroepitaxial growth method of the first embodiment, the first compound semiconductor epitaxial layer 3 is formed for the purpose of suppressing coalescence of the compound semiconductor low temperature growth layer 2 and reducing surface roughness. It was found that surface roughness remains because the suppression of coalescence is not sufficient. Further, the second compound semiconductor epitaxial layer 4 is a layer grown to reduce pits,
It was also found that the number of pits had not been reduced significantly.

FIG. 7 is a growth temperature profile of the GaAs heteroepitaxial growth method of the second embodiment. With reference to this growth temperature profile, Ga of this example
The As heteroepitaxial growth method will be described. In addition,
The Si substrate 1, the compound semiconductor low temperature growth layer 2 made of GaAs, the first compound semiconductor epitaxial layer 3 made of GaAs, the second compound semiconductor epitaxial layer 4 made of GaAs, and the third compound semiconductor epitaxial layer 5 made of GaAs are Please refer to FIG.

First Step (See B in FIG. 7) The Si substrate 1 is heated in a reducing atmosphere at 1000 ° C. for about 10 minutes to remove the natural oxide film formed on the surface.

Second stage (see B in FIG. 7) Next, the temperature of the Si substrate is lowered to 350 to 500 ° C. and MOCVD is performed for about 5 minutes to form growth nuclei. The semiconductor low temperature growth layer 2 is grown.

Third stage (see C in FIG. 7) Next, the substrate temperature is raised to 600 ° C. or higher and lower than 700 ° C., the V / III ratio is set to 13, and MOCVD is performed for about 10 minutes.
By doing so, the first compound semiconductor epitaxial layer 3 made of GaAs and having a thickness of 0.5 μm is grown.

Fourth stage (see D in FIG. 7) Next, the temperature of the Si substrate is raised to 700 ° C. or higher to increase V / I.
A second GaAs layer having a thickness of 2.0 μm was formed by performing MOCVD for about 40 minutes while maintaining the II ratio at 13.
The compound semiconductor epitaxial layer 4 is grown.

Fifth Step (See E in FIG. 7) Finally, the temperature of the Si substrate is lowered to less than 700 ° C., and V / II is set.
The compound semiconductor epitaxial layer 5 made of the third GaAs is grown by MOCVD with the I ratio set to 27 for about 10 minutes.

FIG. 8 is a comparison diagram of the states of the GaAs epitaxial layer by the conventional and the growth method of the second embodiment.
Indicates the surface unevenness standard deviation, and (B) indicates the pit density. As shown in this figure, according to the heteroepitaxial growth method of this embodiment, V / when growing the first compound semiconductor epitaxial layer made of GaAs
By lowering the III ratio, the coalescence of the compound semiconductor low temperature growth layer 2 made of GaAs is effectively suppressed, and the surface unevenness standard deviation is 3.1 nm to 2.7 nm as compared with the conventional two-step growth method. Has been reduced to. Further, by lowering the X / III ratio at the time of growing the second compound semiconductor epitaxial layer 4 made of GaAs, the pit density becomes 5 compared with the conventional two-step growth method.
It is reduced from × 10 ⁵ cm ^-2 to 3 × 10 ⁵ cm ^-2 .

In the compound semiconductor hetero-epitaxial growth method of this embodiment, the compound semiconductor low temperature growth layer is formed on the Si substrate, and the V / III ratio and the second ratio when the first compound semiconductor epitaxial layer is grown on the compound semiconductor low temperature growth layer are formed. V / II when growing the compound semiconductor epitaxial layer
By setting the I ratio to a value lower than the V / III ratio during the growth of the third compound semiconductor epitaxial layer, particularly 20 or less, the surface roughness and the pit density are reduced.

(Third Embodiment) In the compound semiconductor heteroepitaxial growth method of this embodiment, a compound semiconductor growth initial layer is grown on a Si substrate, and the first compound semiconductor epitaxial layer grown thereon is subjected to various conditions. The inventors have found conditions for flattening the surface of the uppermost compound semiconductor epitaxial layer forming a semiconductor device or an integrated circuit by annealing.

After the compound semiconductor growth initial layer is deposited on the Si substrate, when the compound semiconductor epitaxial layer is grown, the temperature is raised to the growth temperature in the atmosphere of the reaction tube internal pressure and the group V source gas partial pressure within a certain range. Then, it is already known that the surface flatness of the compound semiconductor growth initial layer is improved. In the compound semiconductor hetero-epitaxial growth method of this embodiment, a compound semiconductor growth initial layer is grown on a Si substrate, and the compound semiconductor epitaxial layer grown on the Si semiconductor substrate is subjected to a predetermined range of reaction tube internal pressure and group V source gas partial pressure. It is characterized in that the surface of the compound semiconductor epitaxial layer further grown thereon is flattened by annealing in the atmosphere.

According to various experiments, the inventors have found that the condition of the atmosphere for improving the flatness when the temperature of the Si substrate is raised after growing the compound semiconductor growth initial layer is grown on the compound semiconductor growth initial layer. It was discovered that it is also effective when annealing the compound semiconductor epitaxial layer.

FIG. 9 is an explanatory diagram of annealing conditions of the compound semiconductor heteroepitaxial growth method of the third embodiment. In this figure, the horizontal axis represents the group V source gas partial pressure, and the vertical axis represents the reaction tube internal pressure. The pressure in the reaction tube in this figure is 76 Tor
r, point A of group V source gas partial pressure of 0.35 Torr, reaction tube internal pressure 760 Torr, group V source gas partial pressure of 0.6 Tor
rr point B, reaction tube internal pressure 760 Torr, group V source gas partial pressure 5.7 Torr point C, and reaction tube internal pressure 76 T
When the compound semiconductor epitaxial layer grown on the compound semiconductor growth initial layer grown on the Si substrate is annealed under the condition of the region surrounded by orr and the group D source gas partial pressure of 1.3 Torr and point D, The surface flatness of the compound semiconductor epitaxial layer formed in step 1 is greatly improved, and a compound semiconductor epitaxial layer suitable for forming a semiconductor element or an integrated circuit can be obtained.

An experimental example of epitaxially growing GaAs on a Si substrate by MOCVD in the compound semiconductor heteroepitaxial growth method of this embodiment will now be described.

[First Experiment] First Stage In the reaction tube, H ₂ of 12 slm and AsH ₃ of 34 sccm were used.
After the introduction, the pressure in the reaction tube was set to 76 Torr and the Si substrate was heated at 1000 ° C. for 10 minutes to remove the natural oxide film.
The flow rate of H ₂ does not change in the subsequent steps. The pressure in the reaction tube does not change except in the annealing process. Also, Ga
Ga attached inside the reaction tube except the process of growing As
AsH ₃ is added at 34 sccm to prevent As from decomposing.
Introduced.

Second stage The temperature of the Si substrate is lowered to about 400 ° C. and AsH ₃ is added to 2
66 sccm, trimethylgallium
lgallium TMG) is introduced at 18 sccm and G
An aAs low temperature growth layer was deposited to a thickness of about 10 nm.

Third Stage Next, the temperature of the Si substrate is raised, and AsH _{3 is} placed on it at 650 ° C.
Of 67 sccm and 2.5 sccm of TMG were introduced to grow a first GaAs epitaxial layer having a thickness of 0.5 μm.

Step 4 The growth of the first GaAs epitaxial layer is interrupted and Si
The substrate was heated to 900 ° C. and annealed for 15 minutes.
At this time, the pressure in the reaction tube was set to 76 Torr, and the AsH ₃ partial pressure was changed in the range of 0.1 to 1.6 Torr. The range of the pressure inside the reaction tube and the partial pressure of AsH ₃ is shown by a straight line A-D in FIG. 9.

Fifth Step After that, the temperature of the Si substrate is lowered again, and AsH ₃ is added at 650 ° C.
Of 67 sccm and TMG of 2.5 sccm were introduced to grow an upper second GaAs epitaxial layer having a thickness of 2.5 μm.

FIG. 10 is a relationship diagram (1) between the partial pressure of arsine and the surface flatness of the GaAs epitaxial layer. The abscissa of this figure shows the partial pressure of arsine, and the ordinate shows the standard deviation of the surface roughness of the second GaAs epitaxial layer. The surface irregularity standard deviation is quantified by observing the surface of the GaAs epitaxial layer with an atomic force microscope, and the smaller the value, the flatter the surface.

Observation of the second uppermost GaAs epitaxial layer, when the first GaAs epitaxial layer grown on the GaAs low temperature growth layer grown on the Si substrate was not annealed, is shown in this figure. As can be seen, the RMS was 4.0 nm. RMS is 4.0 nm
Below, it is understood that the improvement of the surface flatness by annealing is observed under the condition of AsH ₃ partial pressure of 0.35 to 1.3 Torr.

[Second Experiment] First Stage In the reaction tube, H ₂ was 12 slm and AsH ₃ was 34 sccm.
After the introduction, the pressure in the reaction tube was set to 76 Torr and the Si substrate was heated at 1000 ° C. for 10 minutes to remove the natural oxide film.
The flow rate of H ₂ does not change in the subsequent steps. The pressure in the reaction tube does not change except in the annealing process. Also, Ga
Ga attached inside the reaction tube except the process of growing As
AsH ₃ is added at 34 sccm to prevent As from decomposing.
Introduced.

Second stage The temperature of the Si substrate is lowered to about 400 ° C., and AsH ₃ is added to 2
Introducing 66 sccm and 18 sccm of TMG to GaAs
A low temperature growth layer was deposited on the order of 10 nm.

Third Step Next, the temperature of the Si substrate is raised, and AsH _{3 is} placed on the Si substrate at 650 ° C.
Of 67 sccm and 2.5 sccm of TMG were introduced to grow a first GaAs epitaxial layer having a thickness of 0.5 μm.

Step 4 The growth of the first GaAs epitaxial layer is interrupted and Si
The substrate was heated to 900 ° C. and annealed for 15 minutes.
At this time, the pressure in the reaction tube was set to 760 Torr and AsH ₃
The partial pressure was changed in the range of 0 to 10 Torr. The range of the pressure in the reaction tube and the partial pressure of AsH ₃ is a straight line B- in FIG.
Indicated by C.

Fifth Step After that, the temperature of the Si substrate is lowered again, and the AsH _{3 is} heated at 650 ° C.
Of 67 sccm and TMG of 2.5 sccm were introduced to grow an upper second GaAs epitaxial layer having a thickness of 2.5 μm.

FIG. 11 is a relationship diagram (2) between the partial pressure of arsine and the surface flatness of the GaAs epitaxial layer. The abscissa of this figure shows the partial pressure of arsine, and the ordinate shows the standard deviation of the surface roughness of the GaAs epitaxial layer. RMS is 4.0n
It can be seen that the condition where the AsH ₃ partial pressure is 0.6 to 5.7 Torr is the reason why the surface flattening by the annealing is improved.

[Third Experiment] First Stage: 12 slm of H ₂ and 34 sccm of AsH ₃ in the reaction tube.
After the introduction, the pressure in the reaction tube was set to 76 Torr and the Si substrate was heated at 1000 ° C. for 10 minutes to remove the natural oxide film.
The flow rate of H ₂ does not change in the subsequent steps. The pressure in the reaction tube does not change except in the annealing process. Also, Ga
Ga attached inside the reaction tube except the process of growing As
AsH ₃ is added at 34 sccm to prevent As from decomposing.
Introduced.

Second stage The temperature of the Si substrate is lowered to about 400 ° C., and AsH _{3 is changed} to 2
Introducing 66 sccm and 18 sccm of TMG to GaAs
A low temperature growth layer was deposited on the order of 10 nm.

Third Step Next, the temperature of the Si substrate is raised, and AsH ₃ is applied at 650 ° C.
Of 67 sccm and 2.5 sccm of TMG were introduced to grow a first GaAs epitaxial layer having a thickness of 0.5 μm.

Step 4 The growth of the first GaAs epitaxial layer is stopped, and Si
The substrate was heated to 900 ° C. and annealed for 15 minutes.
At this time, the AsH ₃ flow rate was set to 34 sccm, and the pressure in the reaction tube was changed within the range of 50 to 760 Torr. At this time, the AsH ₃ partial pressure was in the range of 0.14 to 2.1 Torr.

Fifth Step After this, the temperature of the Si substrate is lowered again, and AsH ₃ is added at 650 ° C.
Of 67 sccm and TMG of 2.5 sccm were introduced to grow an upper second GaAs epitaxial layer having a thickness of 2.5 μm.

FIG. 12 is a diagram showing the relationship between the pressure in the reaction tube and the surface flatness of the GaAs epitaxial layer. The horizontal axis of this figure shows the pressure in the reaction tube, and the vertical axis shows the standard deviation of the surface roughness of the GaAs epitaxial layer. The RMS is 4.0 nm or less, and the improvement of the surface flattening by annealing can be seen when the pressure in the reaction tube is 220 Torr or more
_It can be seen that the ₃ partial pressure is 0.62 or more. This is contained in the area ABCD of FIG.

In the above embodiment, the in-tube pressure during the growth of the GaAs low temperature growth layer, the first GaAs epitaxial layer and the upper second GaAs epitaxial layer was 7
Although the pressure is set to 6 Torr, if it is 110 Torr or less, an upper second GaAs epitaxial layer having a flat surface similar to the above can be obtained. In this embodiment, GaAs, AlAs, InA are used as compound semiconductors.
s, GaP, AlP, InP or a mixed crystal thereof can be used.

(Fourth Embodiment) As described above, the conventional S
A two-step growth method in which a compound semiconductor low temperature growth layer is grown on an i substrate at a low temperature of about 400 to 500 ° C., and a desired compound semiconductor epitaxial layer is grown thereon at a high temperature of about 600 to 750 ° C., or A three-step growth method is known in which a compound semiconductor layer serving as a buffer is grown on the compound semiconductor low temperature growth layer at a temperature slightly higher than that, and a desired compound semiconductor epitaxial layer is grown thereon at a higher temperature.

However, in the above-mentioned two-step growth method, when the temperature of the compound semiconductor low temperature growth layer is raised to the desired growth temperature of the compound semiconductor low temperature growth layer after the growth of the compound semiconductor low temperature growth layer, the surface of the compound semiconductor low temperature growth layer becomes rough and There is a problem that the flatness of the surface of the epitaxially grown layer becomes poor.

Before the surface of the low temperature growth layer is thus roughened, some improvement can be seen by using the three-step growth method in which the buffer layer is grown at a temperature lower than the normal desired growth temperature of the epitaxial growth layer. However, at this time, when trimethylgallium (TMG) is used as a Ga raw material, the decomposition temperature of TMG is high, so that the growth temperature of the buffer layer grown on the compound semiconductor low temperature growth layer cannot be sufficiently lowered.

In the heteroepitaxial growth method of this embodiment, triethylgallium (TEG), which has a lower decomposition temperature than that of trimethylgallium (TMG) and can be grown at a low temperature, is used as a Ga source, and the compound semiconductor low temperature growth layer is formed. Is characterized in that a buffer layer of a compound semiconductor is grown on top of it.

This occurs when the buffer layer is grown at a lower temperature than when TMG is used as the Ga raw material, and then the temperature is raised to the temperature at which the desired compound semiconductor epitaxial growth layer is grown after the compound semiconductor low temperature growth layer is grown. The surface of the low temperature growth layer can be prevented from being roughened, and the flatness of the surface of the target compound semiconductor epitaxial layer grown thereon can be improved. Further, when triethylgallium (TEG) having a slow growth rate is used as a Ga source for growing the buffer layer, and when another layer such as the compound semiconductor low temperature growth layer or the target compound semiconductor epitaxial layer is grown, By using trimethylgallium (TMG) having a high growth rate, it is possible to prevent the entire process from being prolonged.

In this example, a step of growing a GaAs epitaxial layer on a Si substrate by MOCVD will be described.

First stage 12 slm of H ₂ and 34 sccm of AsH ₃ in the reaction tube.
Is introduced at a flow rate of
The i substrate is heated to 1000 ° C. and maintained for 10 minutes to remove the natural oxide film. In the subsequent steps, the flow rate of H ₂ does not change, and the pressure inside the reaction tube does not change except in the annealing step. In addition, the G adhering to the inside of the reaction tube at times other than growth
To prevent the decomposition of aAs, add 34 sccc of AsH ₃ .
Introduce m.

Second step The temperature of the Si substrate is lowered to about 400 ° C., and AsH ₃ is added to 2
Introducing 66 sccm and 18 sccm of TMG to GaAs
The low temperature growth layer is grown to about 10 nm.

Third Step Next, the temperature of the Si substrate is raised and a buffer layer is grown under the following conditions. AsH ₃ flow rate 67 sccm TMG flow rate 2.5 sccm TEG flow rate 2.6 sccm Buffer layer growth temperature (° C.) and Ga raw material 450 ° C. TEG 500 ° C. TEG 520 ° C. TEG 550 ° C. TMG, TEG 570 ° C. TMG, TEG 600 ° C. TMG 650 ° C. TMG , TEG Transmembrane pressure 5000 Å

Fourth stage The temperature of the Si substrate is raised to 650 ° C. and AsH is introduced into the reaction tube.
₃ is introduced at a flow rate of 67 sccm and TMG at a flow rate of 2.5 sccm to grow a GaAs epitaxial layer having a thickness of 2.5 μm.

FIG. 13 is a diagram showing the relationship between the flatness of the GaAs epitaxial layer of the fourth embodiment and the growth temperature of the buffer layer.
(A) shows the pit density, and (B) shows the flatness. As shown in FIGS. 13 (A) and 13 (B), when TMG is used as a Ga raw material, when the buffer layer is grown at 570 ° C. or lower, the pit density and the flatness of the surface of the low temperature growth layer rapidly deteriorate. To do. However, when TEG is used as a Ga raw material, even if the buffer layer is grown at 570 ° C. or lower, the pit density and flatness of the surface of the buffer layer do not deteriorate up to about 500 ° C.

As described above, by suppressing the surface roughness of the GaAs low temperature growth layer, a GaAs epitaxial layer having a flatter surface was obtained. From these experimental results, it can be seen that the growth temperature of 490 ° C. to 580 ° C. is appropriate. The compound semiconductor in this example is GaA.
s, AlAs, InAs, GaP, AlP, InP and mixed crystals thereof can be used.

(Fifth Embodiment) Conventionally, I of a Si substrate or the like has been used.
When a compound semiconductor epitaxial layer such as GaAs is formed on a group V substrate, a compound semiconductor low-temperature growth layer is first grown on a group IV substrate, and then the unevenness of the surface of the grown compound semiconductor epitaxial layer is polished to be flattened. After that, an attempt has been made to grow a compound semiconductor epitaxial layer and flatten the surface of the compound semiconductor epitaxial layer. However, this method can provide a compound semiconductor epitaxial layer having less surface irregularities, but has a problem that many pits are generated on the surface of the compound semiconductor epitaxial layer. This is because the stacking fault that causes the pits cannot be eliminated by polishing.

In the hetero-epitaxial growth method of this embodiment, a compound semiconductor low-temperature growth layer is grown on a group IV substrate such as a Si substrate, and subsequently, the unevenness of the surface of the grown compound semiconductor epitaxial layer is polished and flattened. Later, the compound semiconductor epitaxial layer to be grown later is annealed at a temperature higher than the growth temperature to reduce stacking faults, thereby reducing pits on the surface of the compound semiconductor epitaxial layer and improving crystallinity. To do. A process of growing a GaAs layer on a Si substrate by the heteroepitaxial growth method of this embodiment will be described.

FIG. 14 is a process explanatory view of the heteroepitaxial growth method of the fifth embodiment, and (A) to (C) show each process. In this figure, 11 is a Si substrate, 12
Is a GaAs low temperature growth layer, 13 is a GaAs epitaxial layer, and 14 is a GaAs epitaxial layer. The hetero-epitaxial growth method of this embodiment will be described with reference to the process explanatory drawing.

First stage (see FIG. 14 (A)) By a growth method such as MOCVD on the Si substrate 11,
A GaAs low temperature growth layer 12 having a thickness of 100 Å is grown, and then a GaAs epitaxial layer 13 having a thickness of 3 μm is grown.

Second stage (see FIG. 14B) The surface of the GaAs epitaxial layer 13 having irregularities is polished by about 1 μm to leave a flat GaAs epitaxial layer 13 having a thickness of 2 μm.

Third stage (see FIG. 14C) On the flattened GaAs epitaxial layer 13, 65
GaAs is grown again at 0 ° C. to form a GaAs epitaxial layer 14.

FIG. 15 is an atomic force microscope photograph of the surface of a GaAs layer grown by the heteroepitaxial growth method of the fifth embodiment. (A) shows the case where the conventional growth method is used, and (B) shows the case of this embodiment. Shows the case of growing by the growth method of. FIG. 15 (A) shows M on the Si substrate 11.
GaA with a thickness of 100Å is grown by the growth method such as OCVD
s low-temperature growth layer 12 is grown, followed by 3 μm thick GaA
s epitaxial layer 13 is grown and its surface is about 1 μm
The surface of the case where a GaAs epitaxial layer is grown at 650 ° C. after being polished and flattened is shown, and it can be seen that many pits are present on the surface.

FIG. 15B shows the MO on the Si substrate 11.
GaAs with a thickness of 100 Å by a growth method such as CVD
A low temperature growth layer 12 is grown, followed by GaAs having a thickness of 3 μm.
The epitaxial layer 13 is grown, the surface thereof is polished to about 1 μm and flattened, then annealed at 650 ° C., and then the GaAs epitaxial layer is grown at 650 ° C. The surface is shown. It can be seen that the pit has disappeared.

Further, the X-ray diffraction half-value width of the GaAs layer by the heteroepitaxial growth method of this embodiment is 170 s.
It was ec, and it was found that the crystallinity was improved as compared with the conventional method (X-ray diffraction half-value width 220 sec). According to the heteroepitaxial growth method of this embodiment, the G
It was found that the same effect can be obtained with general compound semiconductors in addition to aAs. Further, it was found that the same effect as described above is produced when the annealing temperature after polishing the GaAs epitaxial layer 13 is 800 ° C. or higher.
Further, if the annealing after polishing the compound semiconductor epitaxial layer 13 is performed in a group V source gas atmosphere, it is possible to prevent evaporation of a group V element having a high vapor pressure. As the group V source gas, a group V hydride-based gas or a halide-based gas can be used, or an organic substance or solid arsenic vapor can be used.

(Sixth Embodiment) Conventionally, MOC is formed on a Si substrate.
When a compound semiconductor epitaxial layer such as GaAs is grown by VD, (100)-[011] 2 ° off
It was grown by a two-step growth method using a Si substrate.

FIG. 16 shows G having a conventional annealing process.
It is a growth temperature profile (1) of an aAs heteroepitaxial growth method. In this method, a Si substrate is prebaked in an AsH ₃ atmosphere at a temperature of usually 1000 ° C. for 10 minutes (a), and a GaAs low temperature growth layer for forming a growth nucleus of 100 Å is grown at 400 ° C. (b). Finally, a single crystal GaAs epitaxial layer with a thickness of 3.0 μm was grown at 650 ° C. (c).
GaA grown on GaAs low temperature growth layer on Si substrate
The s epitaxial layer becomes an inverted mesa when stripe etching is performed in the [011] direction on the Si substrate.
It has a phase which becomes a forward mesa when stripe etching is performed in the −1] direction. In addition, in the above [01-1] [-
1] indicates a crystal orientation usually indicated by adding a bar on [1].

Further, by pre-treating the Si substrate with an NH ₄ OH / H ₂ O ₂ solution, pre-baking the Si substrate in an AsH ₃ atmosphere at 875 ° C. or lower is carried out in the [01-1] direction on the Si substrate. A single-crystal GaAs epitaxial layer having a phase which becomes an inverted mesa when stripe-etched and a forward mesa when stripe-etched in the [011] direction is obtained. And this crystal is the same as the normal G
It is known that the crystallinity and surface flatness are better than those of aAs crystals.

This change in crystal orientation shows that a strong zinc-blend bond of Si-As can be formed when the pre-baking temperature of the Si substrate is 1000 ° C., whereas a bond of Si-As is not formed when the pre-baking temperature of the Si substrate is 875 ° C. or less. It is considered that the first layer is replaced with a Ga atomic layer during the formation of growth nuclei.

The reason why pre-baking at 875 ° C. or lower is more excellent in the crystallinity and surface flatness of GaAs is that the bond between Si and Ga is weak, and the chemical reaction with the second As layer is used. Since there is no static bond, Si / GaA
It is considered that the lattice mismatch of s is relaxed.
Further, it is generally known that introduction of an annealing step during or after the GaAs crystal growth can suppress defects in the GaAs crystal and improve the surface flatness.

FIG. 17 shows G having a conventional annealing process.
It is a growth temperature profile (2) of an aAs heteroepitaxial growth method. In this method, a Si substrate is pre-baked in an AsH ₃ atmosphere at 1000 ° C. for 10 minutes (a), and a GaAs low temperature growth layer for forming a growth nucleus of 100 Å is grown at 400 ° C. (b), 500 A single-crystal GaAs epitaxial layer having a thickness of 1.5 μm is grown at ℃ (C), annealing is performed at 900 ° C. for 10 minutes (D), and a single-crystal G having a thickness of 1.5 μm at 500 ° C. is again formed.
The aAs epitaxial layer is growing. This single crystal G
By annealing during the growth of the aAs layer, defects can be suppressed and the surface flatness can be improved.

FIG. 18 shows G having a conventional annealing process.
4 is a growth temperature profile (3) of the aAs heteroepitaxial growth method. In this method, a Si substrate is pre-baked in an AsH ₃ atmosphere at 1000 ° C. for 10 minutes (a), and a GaAs low temperature growth layer for forming a growth nucleus of 100 Å is grown at 400 ° C. (b), 500 A single-crystal GaAs epitaxial layer having a thickness of 1.5 μm is grown at ℃ (C), and thermal cycle annealing is repeated to repeat annealing at 900 ° C. three times (D). Is growing a GaAs epitaxial layer. By annealing during the growth of this single crystal GaAs epitaxial layer, defects can be suppressed and the surface flatness can be further improved.

However, the Si substrate was replaced with NH ₄ OH / H ₂ O.
After pretreatment with ₂ solutions, pre-bak the Si substrate to 875
When performed in an AsH ₃ atmosphere at a temperature of ℃ or less, when anneal or thermal cycle anneal is performed at the same temperature as in the above-mentioned conventional technique, the GaAs crystal is polycrystallized, and GaAs having good flatness and crystallinity on the Si substrate. A single crystal layer cannot be obtained, which is an obstacle to forming a semiconductor element on this single crystal layer. The reason for this is that if annealing is performed at 875 ° C. or higher, the bond of Si—Ga that is formed very early is broken, and S
It is considered that this is due to the formation of a strong zinc blend structure of i-As.

In this embodiment, (100) to [011]
In the growth of the compound semiconductor epitaxial layer on the Si substrate tilted in the direction, there is a step of removing the oxide film by heating the Si substrate in a group V element gas atmosphere at 875 ° C. or lower, and further growing the compound semiconductor epitaxial layer. Annealing during or after growth is performed below the temperature of the step of removing the native oxide film on the Si substrate, and the flatness and crystallinity are remarkably improved as compared with those formed by the conventional technique on the Si substrate. It is characterized by obtaining a GaAs layer.

The conventional method of growing the compound semiconductor layer on the Si substrate and the method of this embodiment will be described below in comparison. [Conventional Method for Growing Compound Semiconductor Layer on Si Substrate]
I Pre-baking step (see FIG. 16 for growth temperature profile) (100)-[011] 2 ° off Si substrate, tube pressure 76 Torr temperature 1000 ° C., 10 minutes H ₂ 12 slm AsH ₃ 0.05 slm

Growth Nucleation Layer Forming Step Tube Pressure 76 Torr Temperature 400 ° C. H ₂ 12 slm TMG (15 ° C.) H ₂ Bubbling Gas 100
sccm AsH ₃ 0.40 slm Growth rate 25Å / min Film thickness 100Å

GaAs single crystal layer forming step Tube pressure 76 Torr Temperature 650 ° C. H ₂ 12 slm TMG (15 ° C.) H ₂ bubbling gas 14 s
ccm AsH ₃ 0.10 slm Growth rate 710 Å / min Film thickness 3.0 μm

[Conventional Method for Growing Compound Semiconductor Layer on Si Substrate] II Using a NH ₄ OH / H ₂ O ₂ wet-treated Si substrate, prebaking step was performed at 875 ° C. for 60 minutes at 0.0
It is performed under the condition of 5 slm. This allows GaAs on
The phase of the GaAs crystal of Si is shifted by 90 ° from that of [Conventional method for growing compound semiconductor layer on Si substrate] I.

[Conventional Method for Growing Compound Semiconductor Layer on Si Substrate] III After growing the GaAs layer by 1.5 μm in the above step [Method for growing compound semiconductor layer on Si substrate] I , Anneal at 900 ℃ for 20 minutes, and again GaA
The s layer is grown by 1.5 μm (see FIG. 17 for the growth temperature profile).

[Conventional Method for Growing Compound Semiconductor Layer on Si Substrate] IV In the above step [Method for growing compound semiconductor layer on Si substrate] I, after growing the GaAs layer by 1.5 μm , Thermal cycle annealing at 300-900 ° C
This is repeated three times, and the GaAs layer is grown again to 1.5 μm. (See FIG. 18 for growth temperature profile)

[Conventional Method for Growing Compound Semiconductor Layer on Si Substrate] V In the above [Method for growing compound semiconductor layer on conventional Si substrate] II, after growing the GaAs layer by 1.5 μm, anneal Is carried out at 900 ° C. for 20 minutes, and a GaAs layer is grown again to 1.5 μm.

[Conventional Method for Growing Compound Semiconductor Layer on Si Substrate] VI After growing the GaAs layer by 1.5 μm in the above step [Method for growing compound semiconductor layer on conventional Si substrate] II , Thermal cycle annealing is performed by applying a temperature of 300 to 900 ° C. three times, and the GaAs layer is again formed to a thickness of 1.5 μm.
Grow.

[Method of growing compound semiconductor layer on Si substrate of this embodiment] I In [Conventional method of growing compound semiconductor layer on Si substrate] V, the annealing temperature is set to 875 ° C.

[Method for growing compound semiconductor layer on Si substrate in this example] II In the above-mentioned [Method for growing compound semiconductor layer on conventional Si substrate] VI, the upper limit temperature of thermal cycle annealing is 875 ° C. To

A surface obtained by observing the surface of the GaAs epitaxial layer formed on the Si substrate formed by the above-described conventional growth method and the growth method according to this embodiment with an AFM (atomic force microscope). The standard deviation of roughness and the full width at half maximum of the X-ray double crystal diffraction (400) peak are shown below.

Standard deviation of surface roughness σ (nm) Conventional 3.90 to 4.10 3.30 to 3.50 3.40 to 3.60 3.20 to 3.40 10 or more 10 or more The present invention 2.50 to 2.70 2.30 to 2.50

X-ray double crystal diffraction (400) Peak half-width (″) Conventional 240 to 250 220 to 230 200 to 220 180 to 190 300 or more 300 or more Present invention 180 to 200 160 to 180

From the above results, the Ga formed on the Si substrate by the heteroepitaxial growth method of this embodiment
It can be seen that the crystallinity and flatness of the As layer are considerably improved. As a result, the GaAs formed on the Si substrate
The characteristics and yield of the HEMT, MESFET, etc. formed on the layer are improved.

In the hetero-epitaxial growth method of this embodiment, the Si substrate is heated to remove the natural oxide film from V.
The reason why the temperature is set to 875 ° C. or lower in the group-element-containing atmosphere is that experimentally, a high quality crystal can be formed into a single domain only by a preheating temperature of 875 ° C. or lower. Further, it has been experimentally known that when the annealing temperature of the GaAs single crystal layer is made higher than this preheat temperature, the state of the single domain is destroyed and the GaAs single crystal layer becomes cloudy.

Although it is possible to lower the preheating temperature even if the Si substrate is pretreated with HF, it is possible to reduce the SI
According to the MS data, the GaAs layer formed on the HF-treated Si substrate had many defects and was in an unstable state.
In contrast, when treated with ammonia / hydrogen peroxide solution as in this example, it was stable for a long time.
In this embodiment, MOCVD, MBE, or a crystal growth method similar to these can be adopted.

Further, as the group V source gas, hydride series, halide series, organic matter, and solid arsenic vapor can be used. Further, the heteroepitaxial growth method of this embodiment is applied to GaAs, AlAs, InAs, Ga.
It can be applied to III-V group compound semiconductors such as P, AlP and InP, or mixed crystals thereof.

(Seventh Embodiment) In this embodiment, the contamination of the compound semiconductor epitaxial layer such as GaAs grown on the Si substrate is reduced, and the characteristics of the semiconductor device formed in this GaAs epitaxial growth layer are improved. Characterize.

FIG. 19 is a diagram showing the structure of a MOCVD growth apparatus for compound semiconductor layers. In this figure, 21 is a chamber, 22 is a susceptor, 23 is a Si substrate, 24 is a gate valve, 25 is a gas introduction pipe, 26 is an exhaust pump,
27 is a high frequency coil, and 28 is a carrier. When the GaAs epitaxial layer is grown using the conventional MOCVD growth apparatus for compound semiconductor layers, the quartz chamber 2 is used.
The Si substrate 23 is set on the susceptor 22 of No. 1, and H ₂ , AsH ₃ , and TMG are introduced from the gas introduction pipe 25 while controlling the flow rate, exhausted by the exhaust pump 26, and the Si substrate 23 is 500 by the high frequency coil 27. The temperature is raised to a predetermined temperature in the range of up to 700 ° C., and GaAs is deposited on the Si substrate 23.
Grow layers. The gate valve 24 is opened and closed, and the Si substrate 23 is transferred by the transfer device 28.

However, in the process of growing the GaAs layer, the GaAs component deposited on the upper portion of the Si substrate 23 on the inner wall of the susceptor and the chamber evaporates in the process of growing the GaAs layer on the next Si substrate and contaminates the growing GaAs layer. The problem arises. Therefore, normally, before growing the GaAs layer, calcination is performed in a hydrogen atmosphere at a temperature of about 800 to 1000 ° C. to deposit GaAs deposited on the periphery of the susceptor.
Take measures such as removing.

However, even when air-baked in a hydrogen atmosphere, the GaAs component does not evaporate sufficiently, and the GaAs deposit grows as the GaAs layer grows, and remains on the Si substrate above the susceptor and the chamber inner wall. Finally, it falls onto the Si substrate on which the GaAs layer is grown and Ga
It has been found that the As layer is contaminated and becomes a major obstacle in forming a semiconductor device on the layer. The heteroepitaxial growth method of this embodiment is characterized in that the above-mentioned baking is performed in an atmosphere containing oxygen, for example, an argon-oxygen atmosphere. According to this embodiment, the residual GaAs component on the upper part of the Si substrate on the inner wall of the sesater and the chamber becomes gallium oxide and is easily evaporated, and the contamination of the GaAs epitaxial substrate is remarkably improved. In the heteroepitaxial growth method of this embodiment, a case of growing a GaAs layer will be described.

A Si substrate 23 is set on the susceptor 22 of the MOCVD apparatus shown in FIG. 18 to grow a GaAs layer. The growth conditions for the GaAs layer are as follows. Tube pressure 76 Torr Temperature 650 ° C. H ₂ 12 slm TMG (15 ° C.) 14 sccm AsH ₃ 0.10 slm Growth rate 710 Å / min Film thickness 3.0 μm

When growing a conventional GaAs layer, each time the GaAs layer was grown, it was heated to 1000 ° C. in an atmosphere of argon and hydrogen and annealed for about 1 hour. However, in this example, annealing was performed using an argon-oxygen atmosphere instead of hydrogen.

The number of dust particles obtained by observing the surface of the 3-inch GaAs epitaxial substrate with an optical microscope using the conventional method and the heteroepitaxial growth method of this embodiment is as follows. It can be seen that the pollution from Conventional type 200 to 300 (piece / 3 inch substrate) Inventive type 30 to 40 (piece / 3 inch substrate) The epitaxial growth method of the GaAs layer in this embodiment can be performed by using a MOCVD apparatus or an MBE apparatus. . In addition, the epitaxial growth method of this embodiment uses GaAs, AlAs, InAs, GaP, Al.
The same can be applied to P, InP and mixed crystal layers thereof.

[0126]

As described above, according to the present invention,
It is possible to provide a growth substrate having a compound semiconductor heteroepitaxial layer having a small number of pits, good surface flatness, and a low carrier concentration on the surface, which contributes to the practical application of a high-speed semiconductor device using a compound semiconductor. large.

[Brief description of drawings]

FIG. 1 is a structural explanatory view of a GaAs heteroepitaxial layer grown according to a first embodiment.

FIG. 2 is a growth temperature profile of the GaAs heteroepitaxial growth method of the first embodiment.

FIG. 3 is a photomicrograph of the surface of a GaAs epitaxial layer formed by the conventional and the growth methods of the first embodiment.
In the case of growing by OCVD, (B) shows the surface when grown by the growing method of the first embodiment.

FIG. 4 is a comparison diagram of the number of pits on the surface of a GaAs epitaxial layer according to the conventional and the growth methods of the first embodiment.

FIG. 5 is a comparison diagram of the surface flatness of the GaAs epitaxial layer by the conventional and the growth method of the first embodiment.

FIG. 6 is a graph showing the relationship between the growth temperature of a GaAs epitaxial layer and the number of pits according to the growth method of the first embodiment.

FIG. 7 is a growth temperature profile of the GaAs heteroepitaxial growth method of the second embodiment.

FIG. 8 is a comparison diagram of the states of the GaAs epitaxial layer by the conventional and the growth method of the second embodiment, in which (A) is the surface roughness,
(B) shows the pit density.

FIG. 9 is an explanatory diagram of annealing conditions of the compound semiconductor heteroepitaxial growth method of the third embodiment.

FIG. 10 is a relationship diagram (1) between arsine partial pressure and surface flatness of a GaAs epitaxial layer in the third embodiment.

FIG. 11 is a diagram (2) showing the relationship between the partial pressure of arsine and the surface flatness of the GaAs epitaxial layer in the third embodiment.

FIG. 12 is a relationship diagram between the pressure in the reaction tube and the surface flatness of the GaAs epitaxial layer.

FIG. 13 is a relationship diagram of the flatness of the GaAs epitaxial layer and the growth temperature of the buffer layer in the fourth embodiment. (A) shows the pit density and (B) shows the flatness.

FIG. 14 is a process explanatory view of the heteroepitaxial growth method of the fifth embodiment, and (A) to (C) show each process.

FIG. 15 is an atomic force microscope photograph of the surface of a GaAs layer grown by the heteroepitaxial growth method of the fifth embodiment, where (A) shows the case where the conventional growth method is used.
(B) shows the case of growing by the growing method of this embodiment.

FIG. 16: Growth temperature profile (1) of a GaAs heteroepitaxial growth method having a conventional annealing step
Is.

FIG. 17: Growth temperature profile of GaAs heteroepitaxial growth method with conventional annealing process (2)
Is.

FIG. 18: Growth temperature profile (3) of a GaAs heteroepitaxial growth method having a conventional annealing step
Is.

FIG. 19 is a structural explanatory view of a MOCVD growth apparatus for a compound semiconductor layer.

[Explanation of symbols]

 1 Si Substrate 2 Compound Semiconductor Low Temperature Growth Layer 3 First Compound Semiconductor Epitaxial Layer 4 Second Compound Semiconductor Epitaxial Layer 5 Third Compound Semiconductor Epitaxial Layer 11 Si Substrate 12 GaAs Low Temperature Growth Layer 13 GaAs Epitaxial Layer 14 GaAs Epitaxial Layer 21 Chamber 22 Susceptor 23 Si substrate 24 Gate valve 25 Gas introduction pipe 26 Exhaust pump 27 High frequency coil 28 Transfer device

[Procedure amendment]

[Submission date] July 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

FIG. 3 is a graph showing a GaAs layer formed by the conventional and the growth methods of the first embodiment.
Of the surface of the epitaxial layerCrystal structureIn micrograph,
When (A) is grown by conventional MOCVD,
(B) isthisWhen grown by the growth method of the example
Shows the surface.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] Figure 15

[Correction method] Change

[Correction content]

FIG. 15 is an atomic force microscope photograph of the crystal structure of the surface of a GaAs layer grown by the heteroepitaxial growth method of the fifth embodiment, where (A) shows the case where the conventional growth method is used and (B) shows the case of this embodiment. Shows the case of growing by the growth method of.

[Procedure 3]

[Document name to be corrected] Drawing

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[Figure 3] ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 15, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

FIG. 3, by conventional growth method of the first embodiment in micrographs of the crystal structure of the surface of the GaAs epitaxial layer, (A) if grown by conventional MOCVD, (B) is in this embodiment The surface when grown by the growth method is shown. These pictures are atomic force microscope (AFM) pictures. FIG. 3A shows a conventional MOCV.
The surface of the GaAs layer grown by D is shown, and 20 pits are observed. Further, FIG. 3B shows the surface of the GaAs layer by the growth method of this embodiment, and only 4 pits are observed.

[Procedure Amendment 2]

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FIG. 15 is an atomic force microscope photograph of the crystal structure of the surface of the GaAs layer grown by the conventional hetero-epitaxial growth method of the fifth embodiment. FIG. B) shows the case of growing by the growing method of this embodiment. FIG. 15A shows S
A 100 Å-thick GaAs low-temperature growth layer 12 is grown on the i-substrate 11 by a growth method such as MOCVD, and then a 3 μm-thick GaAs epitaxial layer 13 is grown.
The surface is shown when the GaAs epitaxial layer is grown at 650 ° C. after polishing the surface by about 1 μm and flattening, and it is understood that many pits are present on the surface.

Front page continued (72) Inventor Takashi Eshita 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (22)

[Claims] 1. In a heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate, a compound semiconductor low temperature growth layer is formed on a group IV substrate and then heated to form a first compound semiconductor epitaxial layer. Then, the temperature is further raised to form a second compound semiconductor epitaxial layer, and then the temperature is lowered to form a third compound semiconductor epitaxial layer, which is a heteroepitaxial growth method. 2. A first compound semiconductor epitaxial layer is formed at 600 ° C. or higher and lower than 700 ° C., a second compound semiconductor epitaxial layer is formed at 700 ° C. or higher, and a third compound semiconductor epitaxial layer is formed.
2. The hetero-epitaxial growth method according to claim 1, wherein the compound semiconductor epitaxial layer is formed at a temperature lower than 700.degree. 3. The V / III ratio in the case of forming the first compound semiconductor epitaxial layer is lower than the V / III ratio in the case of forming the second compound semiconductor epitaxial layer. Alternatively, the heteroepitaxial growth method according to claim 2. 4. The V / III ratio during the growth of the first compound semiconductor epitaxial layer and the V / III ratio during the growth of the second compound semiconductor epitaxial layer are set to the V / III ratio when the third compound semiconductor epitaxial layer is formed. V / II
A heteroepitaxial growth method characterized in that the ratio is lower than the I ratio. 5. The V / III ratio when forming the first compound semiconductor epitaxial layer and the V / III ratio when forming the second compound semiconductor epitaxial layer are 20.
The heteroepitaxial growth method according to claim 4, wherein: 6. A heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate, wherein the compound semiconductor low-temperature growth layer is formed on the group IV substrate and then heated to form a first compound semiconductor epitaxial layer. , The first compound semiconductor epitaxial layer has a reaction tube internal pressure of 76 Torr and a group V source gas partial pressure of 0.35 Torr.
Point A of r, reaction tube internal pressure of 760 Torr, point V of group V source gas partial pressure of 0.6 Torr, reaction tube internal pressure of 760 T
Orr, point C of group V source gas partial pressure of 5.7 Torr, reaction tube internal pressure 76 Torr, group V source gas partial pressure of 1.3 Tor
A heteroepitaxial growth method characterized by annealing under the condition of a region surrounded by the point D of rr and improving crystallinity and surface flatness of the first compound semiconductor epitaxial layer. 7. The hetero-epitaxial growth method according to claim 6, wherein the pressure in the reaction tube in the step of growing the compound semiconductor epitaxial layer is set to 110 Torr or less. 8. A heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate, wherein a compound semiconductor low temperature growth layer is grown on the group IV substrate,
The first compound semiconductor epitaxial layer is grown thereon at a temperature higher than that for growing the compound semiconductor low temperature growth layer using triethylgallium as a raw material, and the temperature for growing the first compound semiconductor epitaxial layer thereon. A heteroepitaxial growth method comprising growing a second compound semiconductor epitaxial layer at a higher temperature. 9. The heteroepitaxial growth method according to claim 8, wherein the compound semiconductor low temperature growth layer and the second compound semiconductor epitaxial layer are grown using trimethylgallium. 10. The heteroepitaxial growth method according to claim 8, wherein the temperature when growing the first compound semiconductor thin epitaxial layer is set to 490 to 580 ° C. 11. A hetero-epitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate, wherein a compound semiconductor low temperature growth layer is first grown on a group IV substrate, and then a compound semiconductor epitaxial layer is grown and then compound semiconductor epitaxial is grown. The layer is polished and flattened, and then annealed at a temperature higher than that for growing the compound semiconductor epitaxial layer, and then,
A heteroepitaxial growth method comprising growing a compound semiconductor epitaxial layer at a temperature lower than an annealing temperature. 12. The heteroepitaxial growth method according to claim 11, wherein the annealing temperature after polishing the compound semiconductor epitaxial layer is set to 800 ° C. or higher. 13. The hetero-epitaxial growth method according to claim 11, wherein the annealing after polishing the compound semiconductor epitaxial layer is performed in a group V source gas atmosphere. 14. In a heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate tilted from (100) in the [011] direction, the removal of the natural oxide film by heating the group IV substrate is performed in a group V source-containing atmosphere. And forming a compound semiconductor low temperature growth layer on a group IV substrate and then raising the temperature to form a compound semiconductor epitaxial layer, and during or during the growth of the compound semiconductor epitaxial layer. A heteroepitaxial growth method, characterized in that the subsequent annealing is performed at a temperature equal to or lower than the step of removing the native oxide film of the group IV substrate. 15. In a heteroepitaxial growth method for forming a compound semiconductor epitaxial layer on a group IV substrate, annealing the reaction tube and components in the reaction tube in an atmosphere containing oxygen before starting the growth of the compound semiconductor epitaxial layer. A heteroepitaxial growth method characterized by: 16. The heteroepitaxial growth method according to claim 1, wherein the group IV substrate is a Si substrate. 17. The heteroepitaxial growth method according to claim 6, wherein the group V source material is a group V hydride system. 18. The hetero-epitaxial growth method according to claim 6, wherein the group V raw material is a group V halide system. 19. The hetero-epitaxial growth method according to claim 6, wherein the group V source material is an organic material. 20. The hetero-epitaxial growth method according to claim 6, 13 or 14, wherein the group V source material is solid arsenic vapor. 21. The compound semiconductor is GaAs, AlAs,
The hetero-epitaxial growth method according to any one of claims 1 to 15, wherein the hetero-epitaxial growth method is InAs, GaP, AlP, InP, or a mixed crystal thereof. 22. The hetero-epitaxial growth method according to claim 1, wherein MOCVD, MBE or a method similar to these is used as a method for growing the compound semiconductor epitaxial layer. .